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| to our customers, old company name in catalogs and other documents on april 1 st , 2010, nec electronics corporation merged with renesas technology corporation, and renesas electronics corporation took over all the business of both companies. therefore, although the old company name remains in this document, it is a valid renesas electronics document. we appreciate your understanding. renesas electronics website: http://www.renesas.com april 1 st , 2010 renesas electronics corporation issued by: renesas electronics corporation ( http://www.renesas.com ) send any inquiries to http://www.renesas.com/inquiry .
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property ri ghts of third parties by or arising from the use of renesas electronics products or technical information described in this document . no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property right s of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operat ion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: ?standard?, ?high quality?, an d ?specific?. the recommended applications for each renesas electronics product depends on the product?s quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as ?specific? without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for a n application categorized as ?specific? or for which the product is not intended where you have failed to obtain the prior writte n consent of renesas electronics. the quality grade of each renesas electronics product is ?standard? unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. ?standard?: computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. ?high quality?: transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; an ti- crime systems; safety equipment; and medical equipment not specifically designed for life support. ?specific?: aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics , especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions o r damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. fur ther, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renes as electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) ?renesas electronics? as used in this document means renesas electronics corporation and also includes its majority- owned subsidiaries. (note 2) ?renesas electronics product(s)? means any product developed or manufactured by or for renesas electronics. sh7144 group, sh7145 group hardware manual 32 users manual rev.4.00 2008.03 renesas 32-bit risc microcomputer superhtm risc engine family/sh7144 series sh7114 hd64f7144 hd6437144 hd6417144 sh7145 hd64f7145 hd6437145 hd6417145 rev.4.00 mar. 27, 2008 page ii of xliv rej09b0108-0400 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas products for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor g rants any license to any intellectual property ri g hts or any other ri g hts of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for dama g es or infrin g ement of any intellectual property or other ri g hts arisin g out of the use of any information in this document, includin g , but not limited to, product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples. 3. you should not use the products or the technolo g y described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exportin g the products or technolo g y described herein, you should follow the applicable export control laws and re g ulations, and procedures required by such laws and re g ulations. 4. all information included in this document such as product data, dia g rams, charts, pro g rams, al g orithms, and application circuit examples, is current as of the date this document is issued. such information, however, is subject to chan g e without any prior notice. before purchasin g or usin g any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay re g ular and careful attention to additional and different information to be disclosed by renesas such as that disclosed throu g h our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compilin g the information included in this document, but renesas assumes no liability whatsoever for any dama g es incurred as a result of errors or omissions in the information included in this document. 6. when usin g or otherwise relyin g on the information in this document, you should evaluate the information in li g ht of the total system before decidin g about the applicability of such information to the intended application. renesas makes no representations, warranties or g uaranties re g ardin g the suitability of its products for any particular application and specifically disclaims any liability arisin g out of the application and use of the information in this document or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi g ned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially hi g h quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considerin g the use of our products for such purposes, please contact a renesas sales office beforehand. renesas shall have no liability for dama g es arisin g out of the uses set forth above. 8. notwithstandin g the precedin g para g raph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) sur g ical implantations (3) healthcare intervention (e. g ., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for dama g es arisin g out of the uses set forth in the above and purchasers who elect to use renesas products in any of the fore g oin g applications shall indemnify and hold harmless renesas technolo g y corp., its affiliated companies and their officers, directors, and employees a g ainst any and all dama g es arisin g out of such applications. 9. you should use the products described herein within the ran g e specified by renesas, especially with respect to the maximum ratin g , operatin g supply volta g e ran g e, movement power volta g e ran g e, heat radiation characteristics, installation and other product characteristics. renesas shall have no liability for malfunctions or dama g es arisin g out of the use of renesas products beyond such specified ran g es. 10. althou g h renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to g uard a g ainst the possibility of physical injury, and injury or dama g e caused by fire in the event of the failure of a renesas product, such as safety desi g n for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for a g in g de g radation or any other applicable measures. amon g others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowin g by infants and small children is very hi g h. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for dama g es arisin g out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from renesas. 13. please contact a renesas sales office if you have any questions re g ardin g the information contained in this document, renesas semiconductor products, or if you have any other inquiries. notes re g ardin g these materials rev.4.00 mar. 27, 2008, page iii of xliv rej09b0108-0400 general precautions in the handling of mpu/mcu products the following usage notes are applicable to all mpu/ mcu products from renesas. for detailed usage notes on the products covered by this manual, refer to the rele vant sections of the manua l. if the descriptions under general precautions in the handli ng of mpu/mcu products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. handling of unused pins handle unused pins in accord with the directi ons given under handling of unused pins in the manual. ? the input pins of cmos products are gen erally in the high-impedance state. in operation with an unused pin in the open-circui t state, extra electromagnetic noise is induced in the vicinity of lsi, an associated shoot-through current flows internally, and malfunctions may occur due to the false recogni tion of the pin state as an input signal. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. ? the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at t he moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from t he moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from t he moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. ? the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operat ion of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. ? when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. differences between products before changing from one product to anothe r, i.e. to one with a different type number, confirm that the change will not lead to problems. ? the characteristics of mpu/mcu in the sa me group but having different type numbers may differ because of the differences in inte rnal memory capacity and layout pattern. when changing to products of different type numbers, implement a system-evaluation test for each of the products. rev.4.00 mar. 27, 2008 page iv of xliv rej09b0108-0400 configuration of this manual this manual comprises the following items: 1. general precautions in the handling of mpu/mcu products 2. configuration of this manual 3. preface 4. contents 5. overview 6. description of functional modules ? cpu and system-control modules ? on-chip peripheral modules the configuration of the functional description of each module differs according to the module. however, the generic style includes the following items: i) feature ii) input/output pin iii) register description iv) operation v) usage note when designing an application system that includes this lsi, take notes into account. each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. list of registers 8. electrical characteristics 9. appendix 10. main revisions for this edition (only for revised versions) the list of revisions is a summary of points that have been revised or added to earlier versions. this does not include all of the revised contents . for details, see the actual locations in this manual. 11. index rev.4.00 mar. 27, 2008, page v of xliv rej09b0108-0400 preface the sh7144 group and sh7145 group single-chip risc (reduced instruction set computer) microcomputers integrate a renesa s technology corp. original ri sc cpu core with peripheral functions required for system configuration. target users: this manual was written for users who will be using this lsi in the design of application systems. user s of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of this lsi to the above users. refer to the sh-1/sh-2/sh-dsp software manual for a detailed description of the instruction set. notes on reading this manual: ? product names the following products are covered in this manual. product classifications and abbreviations basic classification on-chip rom classification part no. sh7144f flash memory version (rom: 256 kbytes) hd64f7144 masked rom version (rom: 256 kbytes) hd6437144 sh7144 (112-pin version) sh7144m rom less version hd6417144 sh7145 (144-pin version) sh7145f flash memory version (rom: 256 kbytes) hd64f7145 sh7145m masked rom version (rom: 256 kbytes) hd6437145 rom less version hd6417145 rev.4.00 mar. 27, 2008 page vi of xliv rej09b0108-0400 in this manual, the product abbreviations are used to distinguish products. for example, 112- pin products are collectively refe rred to as the sh7144, an ab breviation of the basic type's classification code, while 144-pin products are collectively referred to as the sh7145. there are three versions of each: a flash memory version, masked rom version, and rom less version. when a description is limited to the fl ash memory version alone, the character f is added at the end of the abbreviation, such as sh7144f. when a description is limited to the masked rom version or rom less version, th e character m is added at the end of the abbreviation, such as sh7144m. ? the typical product the hd64f7144 is taken as the typical product for the descriptions in this manual. accordingly, when using an hd6437144, hd6417144, hd64f7145, hd6437145, or hd6417145 simply replace the hd 64f7144 in those references where no differences between products are pointed out with hd6437144, hd6417144, hd64f7145, hd6437145, or hd6417145. where differences ar e indicated, be aware that each specification applies to the products as indicated. ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, periph eral functions, and elect rical characteristics. ? in order to understand the details of the cpu's functions read the sh-1/sh-2/sh-d sp software manual. ? in order to understand the details of a register when the user knows its name read the index that is the final part of the manual to find the page number of the entry on the register. the addresses, bit names, and initial va lues of the registers are summarized in section 25, list of registers. rules: register name: the following notatio n is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: xxx_n (xxx is the register name and n is the channel number) bit order: the msb is on the left and the lsb is on the right. numerical expression: binary is b xxxx, hexadecimal is h xxxx, and decimal is xxxx. signal expression: low activ e signals are expressed as xxxx . related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.renesas.com/ rev.4.00 mar. 27, 2008, page vii of xliv rej09b0108-0400 sh7144 group, sh7145 group manuals: document title document no. sh7144 group, sh7145 group hardware manual this manual sh-1/sh-2/sh-dsp software manual rej09b0171 user's manuals for development tools: document title document no. c/c++ compiler, assembler, optimized linkage editor user's manual rej10b0047 simulator/debugger (for windows) user's manual ade-702-283 high-performance embedded workshop user's manual rej10j1737 application notes: document title document no. c/c++ compiler edition rej05b0463 rev.4.00 mar. 27, 2008 page viii of xliv rej09b0108-0400 all trademarks and registered trademarks ar e the property of th eir respective owners. rev.4.00 mar. 27, 2008, page ix of xliv rej09b0108-0400 contents section 1 overview........................................................................................... 1 1.1 features ....................................................................................................................... ......2 1.2 internal bloc k diagram.....................................................................................................4 1.3 pin arrangement ...............................................................................................................6 1.4 pin functions .................................................................................................................. ..8 section 2 cpu................................................................................................... 15 2.1 features ....................................................................................................................... ......15 2.2 register conf iguratio n ......................................................................................................15 2.2.1 general regist ers (rn).........................................................................................15 2.2.2 control registers .................................................................................................17 2.2.3 system registers..................................................................................................18 2.2.4 initial values of registers....................................................................................18 2.3 data formats ................................................................................................................... ..19 2.3.1 data format in registers......................................................................................19 2.3.2 data formats in memory .....................................................................................19 2.3.3 immediate data format .......................................................................................20 2.4 instruction features........................................................................................................... 21 2.4.1 risc-type instruction set...................................................................................21 2.4.2 addressing modes ...............................................................................................25 2.4.3 instruction format................................................................................................29 2.5 instruction set ................................................................................................................ ...32 2.5.1 instruction set by classifica tion ..........................................................................32 2.6 processing states.............................................................................................................. .45 2.6.1 state tran sitions...................................................................................................45 section 3 mcu operating modes..................................................................... 47 3.1 selection of operating modes...........................................................................................47 3.2 input/output pins .............................................................................................................. 49 3.3 operating modes...............................................................................................................5 0 3.3.1 mode 0 (mcu exte nsion mode 0) ......................................................................50 3.3.2 mode 1 (mcu exte nsion mode 1) ......................................................................50 3.3.3 mode 2 (mcu exte nsion mode 2) ......................................................................50 3.3.4 mode 3 (single chip mode) ................................................................................50 3.3.5 clock mode..........................................................................................................50 3.4 address map .................................................................................................................... .51 3.5 initial state in this lsi .....................................................................................................5 2 rev.4.00 mar. 27, 2008 page x of xliv rej09b0108-0400 3.6 note on changing operating mode .................................................................................. 52 section 4 clock pulse generator .......................................................................53 4.1 oscilla tor..................................................................................................................... ...... 55 4.1.1 connecting crysta l resona tor ............................................................................. 55 4.1.2 external clock input method............................................................................... 56 4.2 function for detecti ng oscillato r halt.............................................................................. 57 4.3 usage notes .................................................................................................................... .. 58 4.3.1 note on crysta l resonator ................................................................................... 58 4.3.2 notes on board design ........................................................................................ 58 section 5 exception processing.........................................................................61 5.1 overview....................................................................................................................... .... 61 5.1.1 types of exception pro cessing and priority ........................................................ 61 5.1.2 exception processi ng operations......................................................................... 62 5.1.3 exception processing vector table ..................................................................... 63 5.2 resets ......................................................................................................................... ....... 65 5.2.1 types of reset ..................................................................................................... 65 5.2.2 power-on reset ................................................................................................... 65 5.2.3 manual re set ....................................................................................................... 66 5.3 address errors ................................................................................................................. .67 5.3.1 cause of address e rror exception....................................................................... 67 5.3.2 address error excep tion processing.................................................................... 68 5.4 interrupts..................................................................................................................... ...... 69 5.4.1 interrupt sources.................................................................................................. 69 5.4.2 interrupt priority level ........................................................................................ 70 5.4.3 interrupt exceptio n proces sing ............................................................................ 70 5.5 exceptions triggered by instructions ............................................................................... 71 5.5.1 types of exceptions trig gered by instructions ................................................... 71 5.5.2 trap instructions .................................................................................................. 71 5.5.3 illegal slot in structions ........................................................................................ 72 5.5.4 general illegal instructions.................................................................................. 72 5.6 cases when exception sour ces are not accepted............................................................ 73 5.6.1 immediately after delayed branch inst ruction .................................................... 73 5.6.2 immediately after interrupt- disabled inst ruction ................................................ 73 5.7 stack status after excep tion processing ends .................................................................. 74 5.8 usage notes .................................................................................................................... .. 75 5.8.1 value of stack pointer (sp) ................................................................................. 75 5.8.2 value of vector base register (vbr) ................................................................. 75 5.8.3 address errors caused by stacking of address error exception processing...... 75 rev.4.00 mar. 27, 2008, page xi of xliv rej09b0108-0400 section 6 interrupt controller (intc) .............................................................. 77 6.1 features ....................................................................................................................... ......77 6.2 input/output pins .............................................................................................................. 79 6.3 register desc riptions ........................................................................................................79 6.3.1 interrupt control re gister 1 (icr1).....................................................................80 6.3.2 interrupt control re gister 2 (icr2).....................................................................82 6.3.3 irq status regi ster (isr)....................................................................................84 6.3.4 interrupt priority registers a to j (ipra to iprj)...............................................85 6.4 interrupt sources .............................................................................................................. .87 6.4.1 external interrupts ...............................................................................................87 6.4.2 on-chip peripheral mo dule interrupts ................................................................88 6.4.3 user break interrupt ............................................................................................88 6.4.4 h-udi interrupt ...................................................................................................89 6.5 interrupt exception proces sing vectors table..................................................................90 6.6 operation...................................................................................................................... .....93 6.6.1 interrupt sequence ...............................................................................................93 6.6.2 stack after interrupt ex ception pro cessing ..........................................................95 6.7 interrupt response time ...................................................................................................96 6.8 data transfer with inte rrupt request signals ...................................................................98 6.8.1 handling interrupt request signals as sources for dtc activating and cpu interrupt, but not dmac activ ating ..........................................................99 6.8.2 handling interrupt request signals as sources for activating dmac, but not cpu interrupt and dtc activ ating ........................................................99 6.8.3 handling interrupt request signals as source for dtc activating, but not cpu interrupt an d dmac activating ....................................................99 6.8.4 handling interrupt request signals as source for cpu interrupt but not dmac and dt c activatin g ...................................................................100 section 7 user break controller (ubc) ........................................................... 101 7.1 features ....................................................................................................................... ......101 7.2 register desc riptions ........................................................................................................10 3 7.2.1 user break address re gister (ubar) ................................................................103 7.2.2 user break address mask register (ubamr) ...................................................103 7.2.3 user break bus cycle register (ubbr) .............................................................104 7.2.4 user break control register (ubcr)..................................................................105 7.3 operation...................................................................................................................... .....106 7.3.1 flow of user break operatio n .............................................................................106 7.3.2 break on on-chip memory in struction fetc h cycle ...........................................108 7.3.3 program counter (pc) values saved...................................................................108 7.4 examples of use ...............................................................................................................1 09 rev.4.00 mar. 27, 2008 page xii of xliv rej09b0108-0400 7.5 usage notes .................................................................................................................... .. 111 7.5.1 simultaneous fetching of two instru ctions ........................................................ 111 7.5.2 instruction fetches at branches ........................................................................... 111 7.5.3 contention between user break and exception pr ocessing ................................ 112 7.5.4 break at non-delay branch inst ruction jump de stinatio n.................................. 112 7.5.5 module standby m ode setting ............................................................................ 112 section 8 data transfer controller (dtc) ........................................................113 8.1 features....................................................................................................................... ...... 113 8.2 register desc riptions ........................................................................................................ 11 5 8.2.1 dtc mode regist er (dtmr).............................................................................. 116 8.2.2 dtc source address re gister (dtsar) ............................................................ 118 8.2.3 dtc destination address register (d tdar) .................................................... 118 8.2.4 dtc initial address re gister (dtiar)............................................................... 118 8.2.5 dtc transfer count regi ster a (dt cra) ......................................................... 118 8.2.6 dtc transfer count re gister b (d tcrb) ......................................................... 119 8.2.7 dtc enable regist ers (dter)............................................................................ 119 8.2.8 dtc control/status regi ster (dtcsr)............................................................... 120 8.2.9 dtc information base register (d tbr) ............................................................ 121 8.3 operation ...................................................................................................................... .... 122 8.3.1 activation so urces............................................................................................... 122 8.3.2 location of register informati on and dtc vector table ................................... 122 8.3.3 dtc operation .................................................................................................... 125 8.3.4 interrupt source ................................................................................................... 132 8.3.5 operation timing................................................................................................. 132 8.3.6 dtc execution st ate coun ts ............................................................................... 133 8.4 procedures for using dtc................................................................................................ 134 8.4.1 activation by in terrupt......................................................................................... 134 8.4.2 activation by software ........................................................................................ 134 8.4.3 dtc use example ............................................................................................... 135 8.5 usage notes .................................................................................................................... .. 136 8.5.1 prohibition against dmac/dtc re gister access by dtc................................. 136 8.5.2 module standby m ode setting ............................................................................ 136 8.5.3 on-chip ram ..................................................................................................... 136 section 9 bus state controller (bsc) ...............................................................137 9.1 features....................................................................................................................... ...... 137 9.2 input/output pins .............................................................................................................. 139 9.3 register config uration ...................................................................................................... 140 9.4 address map .................................................................................................................... .141 rev.4.00 mar. 27, 2008, page xiii of xliv rej09b0108-0400 9.5 register desc riptions ........................................................................................................14 4 9.5.1 bus control regist er 1 (bcr1) ...........................................................................144 9.5.2 bus control regist er 2 (bcr2) ...........................................................................147 9.5.3 wait control regist er 1 (wcr1).........................................................................152 9.5.4 wait control regist er 2 (wcr2).........................................................................153 9.5.5 ram emulation regist er (ramer)...................................................................153 9.6 accessing external space .................................................................................................154 9.6.1 basic timi ng........................................................................................................154 9.6.2 wait state c ontrol................................................................................................155 9.6.3 cs assert period extension .................................................................................157 9.7 waits between a ccess cycles...........................................................................................158 9.7.1 prevention of data bus conflic ts.........................................................................158 9.7.2 simplification of bus cycl e start det ection ........................................................160 9.8 bus arbitr ation................................................................................................................ ..161 9.9 memory connection example ..........................................................................................163 9.10 access to on-chip periphe ral i/o regi sters......................................................................166 9.11 cycles of no-bus mast ership release ..............................................................................166 9.12 cpu operation when program is lo cated in extern al memory.......................................166 section 10 direct memory access controller (dmac) .................................. 167 10.1 features ....................................................................................................................... ......167 10.2 input/output pins .............................................................................................................. 169 10.3 register desc riptions ........................................................................................................17 0 10.3.1 dma source address registers_0 to 3 (sar_0 to sar_3) ...............................170 10.3.2 dma destination address registers_ 0 to 3 (dar_0 to dar_3).......................171 10.3.3 dma transfer count registers_0 to 3 (dmatcr_0 to dmatcr_3)..............171 10.3.4 dma channel control registers_0 to 3 (chcr_0 to chcr_3)........................172 10.3.5 dmac operation regi ster (dmaor) ................................................................178 10.4 operation...................................................................................................................... .....180 10.4.1 dma transfer flow ............................................................................................180 10.4.2 dma transfer requests ......................................................................................182 10.4.3 channel prio rity ...................................................................................................184 10.4.4 dma transfer types ...........................................................................................187 10.4.5 number of bus cycle states and dreq pin sample timing..............................197 10.4.6 source address relo ad function .........................................................................203 10.4.7 dma transfer endi ng conditions.......................................................................204 10.4.8 dmac access fr om cpu....................................................................................205 10.5 examples of use ...............................................................................................................2 06 10.5.1 example of dma transfer between on -chip sci and external memory ..........206 rev.4.00 mar. 27, 2008 page xiv of xliv rej09b0108-0400 10.5.2 example of dma transfer between ex ternal ram and external device with dack .......................................................................................................... 207 10.5.3 example of dma transfer between a/ d converter and on-chip memory (address relo ad on)............................................................................................ 208 10.5.4 example of dma transfer be tween external memory a nd sci1 transmit side (indirect address on) .......................................................................................... 210 10.6 usage notes .................................................................................................................... .. 211 section 11 multi-function timer pulse unit (mtu)........................................213 11.1 features....................................................................................................................... ...... 213 11.2 input/output pins .............................................................................................................. 217 11.3 register desc riptions ........................................................................................................ 21 8 11.3.1 timer control regi ster (tcr)............................................................................. 220 11.3.2 timer mode regist er (tmdr) ............................................................................ 224 11.3.3 timer i/o control re gister (tior) ..................................................................... 226 11.3.4 timer interrupt enable register (tier) .............................................................. 244 11.3.5 timer status regi ster (tsr)................................................................................ 246 11.3.6 timer counter (tcnt)........................................................................................ 249 11.3.7 timer general regi ster (tgr) ............................................................................ 249 11.3.8 timer start regist er (tstr) ............................................................................... 250 11.3.9 timer synchronous re gister (tsyr).................................................................. 250 11.3.10 timer output master enab le register (toer) ................................................... 252 11.3.11 timer output control register (t ocr) .............................................................. 253 11.3.12 timer gate control re gister (tgcr) ................................................................. 255 11.3.13 timer subcounter (tcnts) ................................................................................ 257 11.3.14 timer dead time data register (tddr)............................................................ 257 11.3.15 timer period data re gister (t cdr) ................................................................... 257 11.3.16 timer period buffer register (tcbr)................................................................. 257 11.3.17 bus master in terface............................................................................................ 258 11.4 operation ...................................................................................................................... .... 259 11.4.1 basic func tions.................................................................................................... 259 11.4.2 synchronous op eration........................................................................................ 264 11.4.3 buffer operation .................................................................................................. 266 11.4.4 cascaded oper ation ............................................................................................. 269 11.4.5 pwm modes ........................................................................................................ 271 11.4.6 phase counting mode.......................................................................................... 276 11.4.7 reset-synchronized pwm mode......................................................................... 282 11.4.8 complementary pwm mode............................................................................... 285 11.5 interrupt sources.............................................................................................................. .310 11.5.1 interrupt sources an d prioritie s............................................................................ 310 rev.4.00 mar. 27, 2008, page xv of xliv rej09b0108-0400 11.5.2 dtc/dmac activ ation.......................................................................................312 11.5.3 a/d converter ac tivation ....................................................................................312 11.6 operation timing..............................................................................................................3 13 11.6.1 input/output timing ............................................................................................313 11.6.2 interrupt signal timing........................................................................................318 11.7 usage notes .................................................................................................................... ..321 11.7.1 module standby m ode setti ng.............................................................................321 11.7.2 input clock rest rictions.......................................................................................321 11.7.3 caution on peri od setting ....................................................................................322 11.7.4 contention between tcnt write and clear operations .....................................322 11.7.5 contention between tcnt write and increment op erations..............................323 11.7.6 contention between tgr write and compare match .........................................324 11.7.7 contention between buffer register write and comp are match ........................325 11.7.8 contention between tgr read and input capture..............................................326 11.7.9 contention between tgr write and input capture.............................................327 11.7.10 contention between buffer register write and input capture ............................328 11.7.11 tcnt2 write and overflow/underflow co ntention in cascade connection......328 11.7.12 counter value during comple mentary pwm mode stop ...................................330 11.7.13 buffer operation se tting in complement ary pwm mode...................................330 11.7.14 reset sync pwm mode buffer opera tion and compare match flag .................331 11.7.15 overflow flags in reset synchronous pwm mode ............................................332 11.7.16 contention between overflow/underfl ow and counter clearing........................333 11.7.17 contention between tcnt write and overflow/u nderflow...............................334 11.7.18 cautions on transition from normal operation or pwm mode 1 to reset-synchronou s pwm mode..........................................................................334 11.7.19 output level in complementary pwm mode and reset-synchronous pwm mode..........................................................................................................335 11.7.20 interrupts in module standby mode ....................................................................335 11.7.21 simultaneous capture of tcnt_1 and tcnt_2 in cascade connection...........335 11.7.22 note on buffer op eration se tting ........................................................................335 11.8 mtu output pin in itializatio n ..........................................................................................336 11.8.1 operating m odes..................................................................................................336 11.8.2 reset start op eration ...........................................................................................336 11.8.3 operation in case of re-setting due to error during operation, etc. ................337 11.8.4 overview of initialization procedures and mode transitions in case of error during opera tion, et c. .................................................................................338 11.9 port output enab le (poe).................................................................................................368 11.9.1 features................................................................................................................368 11.9.2 pin configuration.................................................................................................370 11.9.3 register desc riptions ...........................................................................................370 rev.4.00 mar. 27, 2008 page xvi of xliv rej09b0108-0400 11.9.4 operation ............................................................................................................. 375 11.9.5 usage notes ......................................................................................................... 377 section 12 watchdog timer (wdt) .................................................................379 12.1 features....................................................................................................................... ...... 379 12.2 input/output pin............................................................................................................... .380 12.3 register desc riptions ........................................................................................................ 38 1 12.3.1 timer counter (tcnt)........................................................................................ 381 12.3.2 timer control/status re gister (tcsr)................................................................ 382 12.3.3 reset control/status re gister (rstcsr)............................................................ 384 12.4 operation ...................................................................................................................... .... 385 12.4.1 watchdog time r mode ........................................................................................ 385 12.4.2 interval timer mode............................................................................................ 386 12.4.3 clearing software standby mode ........................................................................ 387 12.4.4 timing of setting ove rflow flag (ovf) ............................................................. 387 12.4.5 timing of setting watchdog ti mer overflow flag (wovf) ............................. 388 12.5 interrupt source ............................................................................................................... .388 12.6 usage notes .................................................................................................................... .. 389 12.6.1 notes on regist er access..................................................................................... 389 12.6.2 tcnt write and increm ent contention .............................................................. 390 12.6.3 changing cks2 to ck s0 bit va lues .................................................................. 391 12.6.4 changing between watchdog timer and interval timer modes ......................... 391 12.6.5 system reset by wdtovf signal...................................................................... 391 12.6.6 internal reset in watc hdog timer mode............................................................. 391 12.6.7 manual reset in watchd og timer mode ............................................................. 392 12.6.8 note on using wdtovf signal ......................................................................... 392 section 13 serial communication interface (sci) ............................................393 13.1 features....................................................................................................................... ...... 393 13.2 input/output pins .............................................................................................................. 395 13.3 register desc riptions ........................................................................................................ 39 6 13.3.1 receive shift regi ster (rsr) .............................................................................. 398 13.3.2 receive data regi ster (rdr) .............................................................................. 398 13.3.3 transmit shift regi ster (tsr) ............................................................................. 398 13.3.4 transmit data regi ster (tdr)............................................................................. 398 13.3.5 serial mode regi ster (smr) ............................................................................... 399 13.3.6 serial control re gister (s cr).............................................................................. 402 13.3.7 serial status regi ster (ssr) ................................................................................ 407 13.3.8 serial direction contro l register (sdcr)........................................................... 415 13.3.9 bit rate regist er (brr) ...................................................................................... 416 rev.4.00 mar. 27, 2008, page xvii of xliv rej09b0108-0400 13.4 operation in asynch ronous mode ....................................................................................426 13.4.1 data transfer format ...........................................................................................427 13.4.2 receive data sampling timing and r eception margin in asynchronous mode ....................................................................................................................428 13.4.3 clock....................................................................................................................429 13.4.4 sci initialization (async hronous mode) .............................................................430 13.4.5 data transmission (as ynchronous mode)...........................................................431 13.4.6 serial data reception (a synchronous mode)......................................................433 13.5 multiprocessor communi cation func tion.........................................................................437 13.5.1 multiprocessor serial da ta transmission ............................................................439 13.5.2 multiprocessor serial data reception .................................................................440 13.6 operation in clocked synchronous mode ........................................................................443 13.6.1 clock....................................................................................................................443 13.6.2 sci initialization (clocked synchronous mode) .................................................444 13.6.3 serial data transmission (clo cked synchronous mode) ....................................445 13.6.4 serial data reception (clock ed synchronous mode)..........................................447 13.6.5 simultaneous serial data tr ansmission and reception (clocked synchronous mode) .............................................................................449 13.7 smart card interface .........................................................................................................45 1 13.7.1 pin connection example......................................................................................451 13.7.2 data format (except for bl ock transfer mode) ..................................................452 13.7.3 block transfer mode ...........................................................................................453 13.7.4 receive data sampling timing and receptio n margin .......................................454 13.7.5 initializatio n .........................................................................................................455 13.7.6 serial data transmission (excep t for block transfer mode)..............................456 13.7.7 clock output control...........................................................................................459 13.8 interrupt sources .............................................................................................................. .460 13.8.1 interrupts in normal serial co mmunication inte rface mode...............................460 13.8.2 interrupts in smart ca rd interface mode .............................................................462 13.9 usage notes .................................................................................................................... ..463 13.9.1 tdr write and td re flag .................................................................................463 13.9.2 module standby m ode setti ng.............................................................................463 13.9.3 break detection and processing (asynchronous mode only).............................463 13.9.4 sending break signal (async hronous mode only) .............................................463 13.9.5 receive error flags and transmit operations (clocked synchronous mode only).....................................................................464 13.9.6 notes on dmac and dtc use ...........................................................................464 13.9.7 notes on clocked synchronous external cloc k mode ........................................464 13.9.8 note on clocked synchronous internal clock mode...........................................465 rev.4.00 mar. 27, 2008 page xviii of xliv rej09b0108-0400 section 14 i 2 c bus interface (iic) option.........................................................467 14.1 features....................................................................................................................... ...... 468 14.2 input/output pins .............................................................................................................. 470 14.3 description of registers.................................................................................................... 471 14.3.1 i 2 c bus data regist er (icdr) ............................................................................. 471 14.3.2 slave-address regi ster (sar)............................................................................. 472 14.3.3 second slave-address register (sarx) ............................................................. 473 14.3.4 i 2 c bus mode regist er (icmr)........................................................................... 474 14.3.5 i 2 c bus control regi ster (icc r)......................................................................... 477 14.3.6 i 2 c bus status regi ster (icsr)............................................................................ 486 14.3.7 serial control regi ster x (scrx)....................................................................... 490 14.3.8 icdre flag (inter nal flag ) ................................................................................. 492 14.4 operation ...................................................................................................................... .... 493 14.4.1 i 2 c bus data fo rmats........................................................................................... 493 14.4.2 initializatio n ......................................................................................................... 495 14.4.3 operations in master transmission ..................................................................... 496 14.4.4 operations in mast er reception........................................................................... 501 14.4.5 operations in slav e receptio n............................................................................. 509 14.4.6 operations in slav e transmission........................................................................ 518 14.4.7 timing for setting iric an d the control of scl................................................. 521 14.4.8 dtc operation .................................................................................................... 524 14.4.9 noise canceller.................................................................................................... 526 14.4.10 initialization of inte rnal stat e .............................................................................. 526 14.5 usage notes .................................................................................................................... .. 528 14.5.1 module stop m ode setting .................................................................................. 539 section 15 a/d converter .................................................................................541 15.1 features....................................................................................................................... ...... 541 15.2 input/output pins .............................................................................................................. 543 15.3 register desc riptions ........................................................................................................ 54 4 15.3.1 a/d data registers 0 to 7 (addr0 to addr7) ................................................. 544 15.3.2 a/d control/status register_0 , 1 (adcsr_0, adcsr_1) ................................ 545 15.3.3 a/d control register_0, 1 (adcr_0, adcr_1)................................................ 547 15.3.4 a/d trigger select re gister (adtsr) ................................................................ 548 15.4 operation ...................................................................................................................... .... 549 15.4.1 single mode......................................................................................................... 549 15.4.2 continuous scan mode ........................................................................................ 549 15.4.3 single-cycle scan mode...................................................................................... 550 15.4.4 input signal sampling and a/d conversion time .............................................. 550 15.4.5 a/d converter activa tion by mt u ..................................................................... 552 rev.4.00 mar. 27, 2008, page xix of xliv rej09b0108-0400 15.4.6 external trigger input timi ng .............................................................................552 15.5 interrupt sources and dtc, dm ac transfer requests ....................................................553 15.6 definitions of a/d co nversion accuracy .........................................................................554 15.7 usage notes .................................................................................................................... ..556 15.7.1 module standby m ode setti ng.............................................................................556 15.7.2 permissible signal s ource impedance .................................................................556 15.7.3 influences on abso lute accuracy ........................................................................556 15.7.4 range of analog power suppl y and other pi n settings ......................................557 15.7.5 notes on boar d design ........................................................................................557 15.7.6 notes on noise co untermeasures ........................................................................557 section 16 compare match timer (cmt)........................................................ 559 16.1 features ....................................................................................................................... ......559 16.2 register desc riptions ........................................................................................................56 0 16.2.1 compare match timer start register (c mstr) .................................................560 16.2.2 compare match timer control/status register_0, 1 (cmcsr_0, cm csr_1) .....................................................................................561 16.2.3 compare match timer counter_0, 1 (cmcnt_0, cmcnt_1) .........................562 16.2.4 compare match timer constant regi ster_0, 1 (cmcor_0, cmcor_1) .........562 16.3 operation...................................................................................................................... .....563 16.3.1 compare match counte r operation .....................................................................563 16.3.2 cmcnt count timing........................................................................................563 16.4 interrupts ..................................................................................................................... ......564 16.4.1 interrupt sources and dtc activa tion ................................................................564 16.4.2 compare match flag set timing.........................................................................564 16.4.3 compare match flag clear timi ng .....................................................................565 16.5 usage notes .................................................................................................................... ..566 16.5.1 contention between cmcnt write and compare match ...................................566 16.5.2 contention between cmcnt word write and counter incrementation.............567 16.5.3 contention between cmcnt byte write and counter incrementation ..............568 section 17 pin functio n controller (pfc)........................................................ 569 17.1 register desc riptions ........................................................................................................59 5 17.1.1 port a i/o register l, h (paiorl, paiorh) ...................................................596 17.1.2 port a control registers l2, l1, h (pacrl2, pacrl1, pacrh) ...................597 17.1.3 port b i/o regist er (pbior) ...............................................................................605 17.1.4 port b control registers 1, 2 (pbcr1, pbcr2) .................................................605 17.1.5 port c i/o regist er (pcior) ...............................................................................609 17.1.6 port c control re gister (p ccr) ..........................................................................609 17.1.7 port d i/o registers l, h (pdiorl, pdiorh)..................................................611 rev.4.00 mar. 27, 2008 page xx of xliv rej09b0108-0400 17.1.8 port d control registers l1, l2, h1, h2 (pdcrl1, pdcrl2, pd crh1, pdcrh 2)......................................................... 612 17.1.9 port e i/o register l (peiorl).......................................................................... 621 17.1.10 port e control registers l1 , l2 (pecrl1, pecrl2) ........................................ 622 17.1.11 high-current port contro l register (ppcr)........................................................ 630 17.2 usage notes .................................................................................................................... .. 631 section 18 i/o ports...........................................................................................633 18.1 port a......................................................................................................................... ....... 634 18.1.1 register desc riptions ........................................................................................... 636 18.1.2 port a data registers h an d l (padrh and padrl)....................................... 636 18.2 port b ......................................................................................................................... ....... 639 18.2.1 register desc riptions ........................................................................................... 639 18.2.2 port b data regi ster (pbdr) .............................................................................. 640 18.3 port c ......................................................................................................................... ....... 642 18.3.1 register desc riptions ........................................................................................... 642 18.3.2 port c data regi ster (pcdr) .............................................................................. 643 18.4 port d......................................................................................................................... ....... 645 18.4.1 register desc riptions ........................................................................................... 647 18.4.2 port d data registers h an d l (pddrh and pddrl)....................................... 647 18.5 port e ......................................................................................................................... ....... 650 18.5.1 register desc riptions ........................................................................................... 651 18.5.2 port e data regist er l (pedrl)......................................................................... 652 18.6 port f......................................................................................................................... ........ 654 18.6.1 register desc riptions ........................................................................................... 654 18.6.2 port f data regi ster (pfdr) ............................................................................... 654 section 19 flash memory (f-ztat version)...................................................657 19.1 features....................................................................................................................... ...... 657 19.2 mode tran sitions .............................................................................................................. 6 59 19.3 block confi guration.......................................................................................................... 66 3 19.4 input/output pins .............................................................................................................. 664 19.5 register desc riptions ........................................................................................................ 66 5 19.5.1 flash memory control re gister 1 (f lmcr1) ..................................................... 665 19.5.2 flash memory control re gister 2 (f lmcr2) ..................................................... 666 19.5.3 erase block regist er 1 (ebr1) ........................................................................... 667 19.5.4 erase block regist er 2 (ebr2) ........................................................................... 668 19.5.5 ram emulation regist er (ramer)................................................................... 668 19.6 on-board programmi ng modes........................................................................................ 670 19.6.1 boot mode ........................................................................................................... 671 rev.4.00 mar. 27, 2008, page xxi of xliv rej09b0108-0400 19.6.2 programming/erasing in user program mode.....................................................673 19.7 flash memory emula tion in ra m....................................................................................674 19.8 flash memory progra mming/erasing ...............................................................................676 19.8.1 program/program-ve rify mode ...........................................................................676 19.8.2 erase/erase-veri fy mode.....................................................................................678 19.8.3 interrupt handling when progra mming/erasing flash memory..........................678 19.9 program/erase pr otection..................................................................................................680 19.9.1 hardware protection ............................................................................................680 19.9.2 software protection..............................................................................................681 19.9.3 error protection....................................................................................................681 19.10 prom programme r mode ................................................................................................682 19.11 usage note..................................................................................................................... ...682 19.11.1 module standby m ode setti ng.............................................................................682 19.11.2 notes when converting the f-ztat versions to the masked-rom versions ...............................................................................................................682 19.11.3 notes on flash memory progr amming and er asing ............................................683 section 20 mask rom...................................................................................... 689 20.1 usage note..................................................................................................................... ...689 section 21 ram ............................................................................................... 691 21.1 usage note..................................................................................................................... ...691 section 22 user debugging interface (h-udi) ................................................ 693 22.1 overview....................................................................................................................... ....693 22.1.1 features................................................................................................................693 22.1.2 block diag ram .....................................................................................................694 22.2 input/output pins .............................................................................................................. 695 22.3 register desc ription..........................................................................................................6 96 22.3.1 instruction regist er (sdir) .................................................................................697 22.3.2 status register (sdsr)........................................................................................698 22.3.3 data register (sddr) .........................................................................................699 22.3.4 bypass register (sdbpr) ...................................................................................699 22.4 operation...................................................................................................................... .....700 22.4.1 h-udi interrupt ...................................................................................................700 22.4.2 bypass mode........................................................................................................703 22.4.3 h-udi reset ........................................................................................................703 22.5 usage notes .................................................................................................................... ..704 rev.4.00 mar. 27, 2008 page xxii of xliv rej09b0108-0400 section 23 advanced user debugger (aud) ...................................................705 23.1 overview....................................................................................................................... .... 705 23.1.1 features................................................................................................................ 705 23.1.2 block diag ram..................................................................................................... 706 23.2 input/output pins .............................................................................................................. 707 23.2.1 pin descript ions................................................................................................... 707 23.3 branch trace mode........................................................................................................... 710 23.3.1 overview.............................................................................................................. 710 23.3.2 operation ............................................................................................................. 710 23.4 ram monitor mode ......................................................................................................... 712 23.4.1 overview.............................................................................................................. 712 23.4.2 communication protocol ..................................................................................... 712 23.4.3 operation ............................................................................................................. 713 23.5 usage notes .................................................................................................................... .. 715 23.5.1 initializatio n ......................................................................................................... 715 23.5.2 operation in software standby mode.................................................................. 715 23.5.3 setting the pa15/ck pin ..................................................................................... 715 23.5.4 pin stat es ............................................................................................................. 716 23.5.5 aud start-up sequence....................................................................................... 716 23.5.6 ram monitor operation using the pd22/audck pin ..................................... 716 23.5.7 settings of aud-related pi ns when usin g e10a ............................................... 717 section 24 power-down modes ........................................................................719 24.1 input/output pins .............................................................................................................. 721 24.2 register desc riptions ........................................................................................................ 72 1 24.2.1 standby control regi ster (sby cr) .................................................................... 722 24.2.2 system control regi ster (sys cr) ...................................................................... 724 24.2.3 module standby control register 1 and 2 (mstcr1 and mstcr2)................. 725 24.3 operation ...................................................................................................................... .... 727 24.3.1 sleep mode .......................................................................................................... 727 24.3.2 software sta ndby mode ....................................................................................... 728 24.3.3 module standby mode......................................................................................... 730 24.4 usage notes .................................................................................................................... .. 731 24.4.1 i/o port st atus...................................................................................................... 731 24.4.2 current consumption duri ng oscillation stabiliza tion wait period.................... 731 24.4.3 on-chip peripheral mo dule interrupt.................................................................. 731 24.4.4 writing to mstcr1 and mst cr2 ..................................................................... 731 24.4.5 dmac, dtc, or aud opera tion in sleep mode................................................ 731 rev.4.00 mar. 27, 2008, page xxiii of xliv rej09b0108-0400 section 25 list of registers .............................................................................. 733 25.1 register address table (in the or der from lower addresses).........................................734 25.2 register bit li st .............................................................................................................. ..745 25.3 register states in ea ch operating mode...........................................................................758 section 26 electrical characteristics ................................................................ 767 26.1 absolute maximum ratings .............................................................................................767 26.2 dc character istics ............................................................................................................7 68 26.3 ac character istics ............................................................................................................7 71 26.3.1 test conditions for the ac character istics ...........................................................771 26.3.2 clock timin g ........................................................................................................772 26.3.3 control signal timing .........................................................................................774 26.3.4 bus timing ..........................................................................................................777 26.3.5 direct memory access cont roller (dmac) timing ...........................................781 26.3.6 multi-function timer puls e unit (mtu)t iming.................................................783 26.3.7 i/o port ti ming....................................................................................................784 26.3.8 watchdog timer (w dt)timing ..........................................................................785 26.3.9 serial communication in terface (sci) timing ....................................................786 26.3.10 i 2 c bus interfa ce timing .....................................................................................788 26.3.11 port output enable (poe) timing.......................................................................789 26.3.12 a/d converter timing .........................................................................................790 26.3.13 h-udi timi ng .....................................................................................................791 26.3.14 aud timi ng ........................................................................................................793 26.4 a/d converter char acteristic s ..........................................................................................795 26.5 flash memory char acteristic s...........................................................................................796 appendix a pin states ...................................................................................... 799 a. pin state ...................................................................................................................... ......799 appendix b pin states of bus related signals................................................. 809 b. pin states of bus re lated sign als .....................................................................................809 appendix c product code lineup.................................................................... 812 appendix d i/o port block diagrams.............................................................. 813 appendix e package dimensions..................................................................... 870 main revisions for this edition .......................................................................... 873 rev.4.00 mar. 27, 2008 page xxiv of xliv rej09b0108-0400 index .........................................................................................................879 rev.4.00 mar. 27, 2008, page xxv of xliv rej09b0108-0400 figures section 1 overview figure 1.1 internal bl ock diagram of sh7144...............................................................................4 figure 1.2 block diagram of sh7145 ........................................................................................... .5 figure 1.3 sh7144 pin arrangement............................................................................................ ..6 figure 1.4 sh7145 pin arrangement............................................................................................ ..7 section 2 cpu figure 2.1 cpu in ternal re gisters ............................................................................................ ....16 figure 2.2 data fo rmat in re gisters .......................................................................................... ...19 figure 2.3 data formats in memory............................................................................................ .19 figure 2.4 transitions between proce ssing stat es ........................................................................45 section 3 mcu operating modes figure 3.1 address map for each operating mode......................................................................51 figure 3.2 reset input timing when changing op erating mode.................................................52 section 4 clock pulse generator figure 4.1 block diagram of clock pulse generator ...................................................................53 figure 4.2 connection of cr ystal resonator (example) ...............................................................55 figure 4.3 crystal resona tor equivalent circuit ..........................................................................55 figure 4.4 example of ex ternal clock connection ......................................................................56 figure 4.5 cautions for os cillator circuit board design..............................................................58 figure 4.6 recommended exte rnal circuitry around pll ...........................................................59 section 6 interrupt controller (intc) figure 6.1 intc block diagram ................................................................................................ ..78 figure 6.2 block diagram of ir q7 to irq0 interrupts control ...................................................88 figure 6.3 interrupt sequence flowchart...................................................................................... 94 figure 6.4 stack after in terrupt exception processing..................................................................95 figure 6.5 example of pipeline oper ation when irq interr upt is accepted ...............................97 figure 6.6 interrupt control block diagram ................................................................................98 section 7 user b reak controller (ubc) figure 7.1 user break c ontroller block diagram ......................................................................102 figure 7.2 break conditio n determinatio n method ...................................................................107 section 8 data transfer controller (dtc) figure 8.1 block diagram of dtc .............................................................................................1 14 figure 8.2 activating source control block diagram................................................................122 figure 8.3 dtc register informat ion allocation in memory space..........................................123 figure 8.4 correspondence between dtc vect or address and transfer information ...............123 rev.4.00 mar. 27, 2008 page xxvi of xliv rej09b0108-0400 figure 8.5 dtc op eration flowchart......................................................................................... 12 6 figure 8.6 memory mapp ing in normal mode .......................................................................... 127 figure 8.7 memory mapp ing in repeat mode ........................................................................... 128 figure 8.8 memory mapping in block transfer mode............................................................... 130 figure 8.9 chain transfer.................................................................................................... ....... 131 figure 8.10 dtc operation ti ming example (nor mal mode) .................................................. 132 section 9 bus state controller (bsc) figure 9.1 bs c block diagram................................................................................................. .138 figure 9.2 address format .................................................................................................... ..... 141 figure 9.3 basic timing of external space access.................................................................... 154 figure 9.4 wait state ti ming of external space access (software wait only) ........................ 155 figure 9.5 wait state timi ng of external space access (two software wait states + wait signal wait state)........................................... 156 figure 9.6 cs assert period exte nsion func tion ....................................................................... 157 figure 9.7 example of idle cycle in sertion................................................................................ 159 figure 9.8 example of idle cycle inse rtion at same space consecutive access....................... 160 figure 9.9 bus mastersh ip release pr ocedure............................................................................ 162 figure 9.10 example of 8-bit data bus width ro m connectio n .............................................. 163 figure 9.11 example of 16-bit data bus width ro m connectio n ............................................ 163 figure 9.12 example of 32-bit data bu s width rom connection (only for sh7145).............. 164 figure 9.13 example of 8-bit da ta bus width sram connection............................................ 164 figure 9.14 example of 16-bit da ta bus width sram connection.......................................... 165 figure 9.15 example of 32-bit data bus width sram connection ( only for sh7145)............ 165 figure 9.16 one bus cycle.................................................................................................... ..... 166 section 10 direct memory access controller (dmac) figure 10.1 dmac block diagram............................................................................................ 168 figure 10.2 dmac tr ansfer flowchart ..................................................................................... 181 figure 10.3 (1) round robi n mode............................................................................................ 1 85 figure 10.3 (2) example of changes in priority in round robin mode .................................... 186 figure 10.4 data flow in single addr ess mode......................................................................... 188 figure 10.5 example of dma transfer timing in single address mode.................................. 189 figure 10.6 direct address oper ation during dual address mode............................................ 190 figure 10.7 example of direct address transfer timing in dual address mode ..................... 191 figure 10.8 dual address mode and indirect address operation (when external memory space is 16 bits)............................................................. 192 figure 10.9 dual address mode and indirect address transfer timing example (external memory space to external memory space, 16- bit widt h)..................... 193 figure 10.10 dual address mode and in direct address transfer timing example (on-chip memory space to on-chip memory space)........................................... 194 rev.4.00 mar. 27, 2008, page xxvii of xliv rej09b0108-0400 figure 10.11 dma transfer ex ample in cycle- steal m ode ......................................................195 figure 10.12 dma transfer example in burst mode ................................................................195 figure 10.13 bus handling when mu ltiple channels ar e operating .........................................197 figure 10.14 cycle steal, dual address an d level detection (fas test operat ion) ....................200 figure 10.15 cycle steal, dual address and level detection (n ormal operation) ...................200 figure 10.16 cycle steal, single address an d level detection (fas test operation)..................200 figure 10.17 cycle steal, single address and level detection (n ormal operation).................200 figure 10.18 burst mode, dual address an d level detection (fas test opera tion)....................201 figure 10.19 burst mode, dual address and level detection (n ormal operation)...................201 figure 10.20 burst mode, single address an d level detection (fas test operation) .................201 figure 10.21 burst mode, single address and level detection (n ormal operation) ................202 figure 10.22 burst mode, dual address and edge detection ....................................................202 figure 10.23 burst mode, single address and edge detection..................................................202 figure 10.24 source ad dress reload function...........................................................................203 figure 10.25 source address re load function timi ng chart ....................................................203 section 11 multi-functi on timer pulse unit (mtu) figure 11.1 block diagram of mtu ..........................................................................................216 figure 11.2 complementary pwm mode output leve l example .............................................254 figure 11.3 example of counte r operation setting procedure ..................................................259 figure 11.4 free-runnin g counter operation ............................................................................260 figure 11.5 periodic counter operation .....................................................................................26 1 figure 11.6 example of se tting procedure for waveform output by compare match ..............261 figure 11.7 example of 0 ou tput/1 output operation................................................................262 figure 11.8 example of t oggle output op eration .....................................................................262 figure 11.9 example of input ca pture operation settin g procedure .........................................263 figure 11.10 example of input capture op eration .....................................................................264 figure 11.11 example of synchro nous operation settin g procedure.........................................265 figure 11.12 example of synchronous op eration......................................................................266 figure 11.13 compare ma tch buffer operation .........................................................................267 figure 11.14 input capt ure buffer op eration.............................................................................267 figure 11.15 example of buffer operation setting procedure...................................................267 figure 11.16 example of buffer operation (1)...........................................................................268 figure 11.17 example of buffer operation (2)...........................................................................269 figure 11.18 cascaded op eration setting pr ocedure .................................................................270 figure 11.19 example of cascaded operation ...........................................................................270 figure 11.20 example of pw m mode setting pr ocedure ..........................................................273 figure 11.21 example of pwm mode opera tion (1) .................................................................273 figure 11.22 example of pwm mode opera tion (2) .................................................................274 figure 11.23 example of pwm mode opera tion (3) .................................................................275 figure 11.24 example of phase counting mode settin g procedure...........................................276 rev.4.00 mar. 27, 2008 page xxviii of xliv rej09b0108-0400 figure 11.25 example of phas e counting mode 1 operation .................................................... 277 figure 11.26 example of phas e counting mode 2 operation .................................................... 278 figure 11.27 example of phas e counting mode 3 operation .................................................... 279 figure 11.28 example of phas e counting mode 4 operation .................................................... 280 figure 11.29 phase counting mode applicati on example......................................................... 281 figure 11.30 procedure for selec ting reset-synchroni zed pwm mode.................................... 283 figure 11.31 reset-synchronized pwm mode operation example (when tocr?s olsn = 1 and olsp = 1) ........................................................... 284 figure 11.32 block diagram of channels 3 and 4 in complementary pwm mode .................. 287 figure 11.33 example of complement ary pwm mode setti ng procedure................................ 288 figure 11.34 complementary pw m mode counter operation.................................................. 290 figure 11.35 example of comple mentary pwm mode operation ............................................ 292 figure 11.36 example of pwm cycle up dating........................................................................ 294 figure 11.37 example of data up date in complement ary pwm mode .................................... 296 figure 11.38 example of initial output in complementary pw m mode (1)............................. 297 figure 11.39 example of initial output in complementary pw m mode (2)............................. 298 figure 11.40 example of complementar y pwm mode waveform output (1) ......................... 300 figure 11.41 example of complementar y pwm mode waveform output (2) ......................... 300 figure 11.42 example of complementar y pwm mode waveform output (3) ......................... 301 figure 11.43 example of complementary pwm mode 0% and 100% waveform output (1) .......................................................................................................................... 30 1 figure 11.44 example of complementary pwm mode 0% and 100% waveform output (2) .......................................................................................................................... 30 2 figure 11.45 example of complementary pwm mode 0% and 100% waveform output (3) .......................................................................................................................... 30 2 figure 11.46 example of complementary pwm mode 0% and 100% waveform output (4) .......................................................................................................................... 30 3 figure 11.47 example of complementary pwm mode 0% and 100% waveform output (5) .......................................................................................................................... 30 3 figure 11.48 example of toggle output wa veform synchronized with pwm output............. 304 figure 11.49 counter clearing sync hronized with anot her channel ........................................ 305 figure 11.50 example of output phas e switching by extern al input (1)................................... 306 figure 11.51 example of output phas e switching by extern al input (2)................................... 307 figure 11.52 example of output phase switching by means of uf, vf, wf bit settings (1) .......................................................................................................................... 30 7 figure 11.53 example of output phase switching by means of uf, vf, wf bit settings (2) .......................................................................................................................... 30 8 figure 11.54 count timing in internal clock operation............................................................ 313 figure 11.55 count timing in external clock operation........................................................... 313 figure 11.56 count timing in external clock operatio n (phase counting mode).................... 313 rev.4.00 mar. 27, 2008, page xxix of xliv rej09b0108-0400 figure 11.57 output compare output timing (normal m ode/pwm mode).............................314 figure 11.58 output compare output timing (complementary pwm mode/ reset synchronous pwm mode) ..........................................................................315 figure 11.59 input capt ure input signa l timing........................................................................315 figure 11.60 counter clear timing (compare match)...............................................................316 figure 11.61 counter clear timing (input capture) ..................................................................316 figure 11.62 buffer operatio n timing (compa re matc h)..........................................................317 figure 11.63 buffer operat ion timing (inpu t capture) .............................................................317 figure 11.64 tgi interrupt timing (compare match) ...............................................................318 figure 11.65 tgi interrup t timing (input capture) ...................................................................318 figure 11.66 tciv in terrupt setting timing ..............................................................................319 figure 11.67 tciu in terrupt setting timing ..............................................................................319 figure 11.68 timing for stat us flag clearin g by cpu...............................................................320 figure 11.69 timing for status flag clearing by dtc/dm ac activation................................320 figure 11.70 phase difference, overlap, and pulse width in phase counting mode ................321 figure 11.71 contention between tc nt write and clear operations .......................................322 figure 11.72 contention between tcnt write and incremen t operations ...............................323 figure 11.73 contention between tgr write and comp are match...........................................324 figure 11.74 contention between buffer regist er write and compare match (channel 0) ......325 figure 11.75 contention between buffer register write and compare match (channels 3 and 4).................................................................................................326 figure 11.76 contention between tgr read and input capture ...............................................326 figure 11.77 contention between tgr write and inpu t capture ..............................................327 figure 11.78 contention between buffer register write and input capture..............................328 figure 11.79 tcnt_2 write and overflow/underflow contention with cascade connectio n.............................................................................................................329 figure 11.80 counter value during complementary pwm mode stop.....................................330 figure 11.81 buffer oper ation and compare-match flags in reset synchronous pwm mode......................................................................................................................331 figure 11.82 reset synchronou s pwm mode ove rflow flag ...................................................332 figure 11.83 contention between overflow and coun ter clearing............................................333 figure 11.84 contention betw een tcnt write an d overfl ow...................................................334 figure 11.85 error occurrence in norm al mode, recovery in normal mode ...........................339 figure 11.86 error occurrence in norm al mode, recovery in pwm mode 1...........................340 figure 11.87 error occurrence in norm al mode, recovery in pwm mode 2...........................341 figure 11.88 error occurrence in normal mode, recovery in ph ase counting mode ..............342 figure 11.89 error occurrence in normal mode, recovery in complementary pwm mode......................................................................................................................343 figure 11.90 error occurrence in normal mode, recovery in reset-synchronous pwm mode......................................................................................................................344 rev.4.00 mar. 27, 2008 page xxx of xliv rej09b0108-0400 figure 11.91 error occurrence in pwm mode 1, recovery in normal mode........................... 345 figure 11.92 error occurrence in pwm mode 1, recovery in pwm mode 1 .......................... 346 figure 11.93 error occurrence in pwm mode 1, recovery in pwm mode 2 .......................... 347 figure 11.94 error occurrence in pwm mode 1, recovery in phase counting mode.............. 348 figure 11.95 error occurrence in pwm mode 1, recovery in complementary pwm mode ..................................................................................................................... 349 figure 11.96 error occurrence in pwm mode 1, recovery in reset-synchronous pwm mode ..................................................................................................................... 350 figure 11.97 error occurrence in pwm mode 2, recovery in normal mode........................... 351 figure 11.98 error occurrence in pwm mode 2, recovery in pwm mode 1 .......................... 352 figure 11.99 error occurrence in pwm mode 2, recovery in pwm mode 2 .......................... 353 figure 11.100 error occurrence in pwm m ode 2, recovery in phase counting mode............ 354 figure 11.101 error occurrence in phase counting mode, recovery in normal mode ............ 355 figure 11.102 error occurrence in phase counting mode, recovery in pwm mode 1............ 356 figure 11.103 error occurrence in phase counting mode, recovery in pwm mode 2............ 357 figure 11.104 error occu rrence in phase counting mode, recovery in phase counting mode ................................................................................................................... 358 figure 11.105 error occurrence in complementary pwm mode, recovery in normal mode ................................................................................................................... 359 figure 11.106 error occurrence in complementary pwm mode, recovery in pwm mode 1 ................................................................................................................ 360 figure 11.107 error occurrence in complementary pwm mode, recovery in complementary pwm mode .............................................................................. 361 figure 11.108 error occurrence in complementary pwm mode, recovery in complementary pwm mode .............................................................................. 362 figure 11.109 error occurrence in complementary pwm mode, recovery in reset-synchronou s pwm mode......................................................................... 363 figure 11.110 error occurrence in reset-synchronous pwm mode, recovery in normal mode ................................................................................................................... 364 figure 11.111 error occurrence in reset-synchronous pwm mode, recovery in pwm mode 1 ................................................................................................................ 365 figure 11.112 error occurrence in reset-synchronous pwm mode, recovery in complementary pwm mode .............................................................................. 366 figure 11.113 error occurrence in reset-synchronous pwm mode, recovery in reset-synchronou s pwm mode......................................................................... 367 figure 11.114 po e block diagram ............................................................................................ 36 9 figure 11.115 low-leve l detection op eration.......................................................................... 376 figure 11.116 output-lev el detection op eration ...................................................................... 376 figure 11.117 falling edge detection op eration ....................................................................... 377 rev.4.00 mar. 27, 2008, page xxxi of xliv rej09b0108-0400 section 12 watchdog timer (wdt) figure 12.1 block diagram of wdt ..........................................................................................380 figure 12.2 operation in watchdog ti mer mode.......................................................................386 figure 12.3 operation in interval timer mode...........................................................................386 figure 12.4 timi ng of setting ovf............................................................................................ 387 figure 12.5 timing of setting wovf ........................................................................................388 figure 12.6 writing to tcnt and tcsr ...................................................................................389 figure 12.7 writing to rstcsr................................................................................................ .390 figure 12.8 contention between tcnt write and increment....................................................390 figure 12.9 example of system reset circuit using wdtovf signal ....................................391 section 13 serial commu nication interface (sci) figure 13.1 bloc k diagram of sci ............................................................................................. 394 figure 13.2 data format in asynchronous communication (example with 8-bit data, pa rity, two stop bits) ..................................................426 figure 13.3 receive data samplin g timing in async hronous mode ........................................428 figure 13.4 relation between output clock and transmit data phase (asynchronous mode) .............................................................................................429 figure 13.5 sample sci initialization fl owchart .......................................................................430 figure 13.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one st op bit).....................................................431 figure 13.7 sample serial transmission flowchart ...................................................................432 figure 13.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit) ........................................................................................................... 433 figure 13.9 sample serial reception data flow chart (1) ..........................................................435 figure 13.9 sample serial reception data flow chart (2) ..........................................................436 figure 13.10 example of communication using multiprocessor format (transmission of data h'aa to receiving st ation a) ..........................................438 figure 13.11 sample multiprocessor serial transmission flowchart ........................................439 figure 13.12 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) .........................................................................440 figure 13.13 sample multiprocessor serial reception fl owchart (1) ........................................441 figure 13.13 sample multiprocessor serial reception fl owchart (2) ........................................442 figure 13.14 data format in clocked sy nchronous communication (for lsb-first) ..............443 figure 13.15 sample sci initialization fl owchart .....................................................................444 figure 13.16 sample sci transmission operation in clocked synchronous mode ..................446 figure 13.17 sample serial transmission flowchart .................................................................446 figure 13.18 example of sc i operation in reception ...............................................................447 figure 13.19 sample seri al reception fl owchart.......................................................................448 figure 13.20 sample flowchart of simultane ous serial transmit and receive operations.......450 figure 13.21 example of pin conn ections for smart ca rd interface .........................................451 rev.4.00 mar. 27, 2008 page xxxii of xliv rej09b0108-0400 figure 13.22 normal smart ca rd interface data format ........................................................... 452 figure 13.23 direct convention (dir = sinv = o/ e = 0)......................................................... 452 figure 13.24 inverse convention (dir = sinv = o/ e = 1)....................................................... 453 figure 13.25 receive data sampling timing in smart card interface mode (using clock of 372 times bit ra te).................................................................... 454 figure 13.26 retransfer oper ation in sci tr ansmit mode......................................................... 457 figure 13.27 tend flag generation timing in transm it operatio n......................................... 457 figure 13.28 example of transmit proces sing flow.................................................................. 458 figure 13.29 timing for fi xing clock output level.................................................................. 459 figure 13.30 example of clocked sync hronous transmission with dmac/dtc .................... 464 section 14 i 2 c bus interface (iic) option figure 14.1 a block diagram of the i 2 c bus interface .............................................................. 469 figure 14.2 example of the connection of i 2 c bus interfaces (this lsi is the ma ster device).............................................................................. 470 figure 14.3 i 2 c bus data format (i 2 c bus form at) ................................................................... 493 figure 14.4 i 2 c bus data format (s erial form at) ...................................................................... 493 figure 14.5 i 2 c bus timi ng ........................................................................................................ 494 figure 14.6 an example of iic initialization flowchart............................................................ 495 figure 14.7 example: flowchart of op erations in the mast er transmit mode .......................... 497 figure 14.8 an example of the timing of operations in master transmit mode (mls = wait = 0) ................................................................................................. 499 figure 14.9 an example of the stop condition issuance timing in master transmit mode (mls = wait = 0) ................................................................................................. 500 figure 14.10 example: flowch art of operations in the master receive mode (hnds = 1) ..... 502 figure 14.11 an example of the timing of operations in master receive mode (mls = wait = 0, hnds = 1) ............................................................................ 504 figure 14.12 an example of the stop cond ition issuance timing in master receive mode (mls = wait = 0, hnds = 1) ............................................................................ 504 figure 14.13 example: flowchart of operations in master receive mode (multiple bytes receptio n) (wait = 1) ............................................................... 505 figure 14.14 example: flowchart of operations in master receive mode (one byte receptio n) (wait = 1)........................................................................ 506 figure 14.15 an example of the timing of operations in master receive mode (mls = ackb = 0, wait = 1) ............................................................................ 508 figure 14.16 an example of the stop cond ition issuance timing in master receive mode (mls = ackb = 0, wait = 1) ............................................................................ 509 figure 14.17 example: flowch art of operations in the slav e receive mode (hnds = 1) ....... 510 figure 14.18 an example of the timing of operations in slave receive mode 1 (mls = 0, hnds = 1)........................................................................................... 512 rev.4.00 mar. 27, 2008, page xxxiii of xliv rej09b0108-0400 figure 14.19 an example of the timing of operations in slave receive mode 2 (mls = 0, hnds = 1)...........................................................................................513 figure 14.20 example: flowchart of opera tions in slave transmit mode (hnds = 0)............514 figure 14.21 an example of the timing of operations in slave receive mode 1 (mls = ackb = 0, hnds = 0)............................................................................516 figure 14.22 an example of the timing of operations in slave receive mode 2 (mls = ackb = 0, hnds = 0)............................................................................517 figure 14.23 example: flowchart of operations in slave transmit mode ................................518 figure 14.24 an example of the timing of op erations in slave transmit mode (mls = 0) ....520 figure 14.25 iric flag set timi ng and the control of scl (1) ................................................521 figure 14.26 iric flag set timi ng and the control of scl (2) ................................................522 figure 14.27 iric flag set timi ng and the control of scl (3) ................................................523 figure 14.28 block diagram of the noise ca nceller ..................................................................526 figure 14.29 points for caution in read ing data received by ma ster reception .....................533 figure 14.30 flowchart and timing of the exec ution of the instruction that sets the start condition for re-t ransmission .............................................................................534 figure 14.31 timing for the setting of the stop conditio n ........................................................535 figure 14.32 iric flag clear timing on wait operation .......................................................536 figure 14.33 timing for clearin g iric flag when wait = 1..................................................536 figure 14.34 timing for r eading icdr and accessing iccr in slave transmit mode ...........537 figure 14.35 timing for set ting trs bit in slave mode ...........................................................538 section 15 a/d converter figure 15.1 block diag ram of a/d converter............................................................................542 figure 15.2 a/d conversion timing ..........................................................................................55 1 figure 15.3 external trigger input timing ................................................................................552 figure 15.4 definitions of a/d conversion accuracy ...............................................................555 figure 15.5 definitions of a/d conversion accuracy ...............................................................555 figure 15.6 example of analog input circuit ............................................................................556 figure 15.7 example of anal og input protection circuit ...........................................................558 section 16 compare match timer (cmt) figure 16.1 cm t block diagram...............................................................................................5 59 figure 16.2 co unter operation ................................................................................................ ...563 figure 16.3 count timing ..................................................................................................... .....563 figure 16.4 cmf set timing................................................................................................... ...564 figure 16.5 timing of cmf clear by cpu ................................................................................565 figure 16.6 cmcnt write an d compare match contentio n.....................................................566 figure 16.7 cmcnt word write and increment contention ....................................................567 figure 16.8 cmcnt byte writ e and increment contention......................................................568 rev.4.00 mar. 27, 2008 page xxxiv of xliv rej09b0108-0400 section 18 i/o ports figure 18.1 port a (sh7144).................................................................................................. .... 634 figure 18.2 port a (sh7145).................................................................................................. .... 635 figure 18.3 port b........................................................................................................... ............ 639 figure 18.4 port c........................................................................................................... ............ 642 figure 18.5 port d (sh7144).................................................................................................. .... 645 figure 18.6 port d (sh7145).................................................................................................. .... 646 figure 18.7 port e (sh7144) .................................................................................................. .... 650 figure 18.8 port e (sh7145) .................................................................................................. .... 651 figure 18.9 port f ........................................................................................................... ............ 654 section 19 flash memory (f-ztat version) figure 19.1 block diag ram of flash memory............................................................................ 658 figure 19.2 flash memo ry state tran sitions .............................................................................. 659 figure 19.3 boot mode........................................................................................................ ....... 661 figure 19.4 user program mode ................................................................................................ 662 figure 19.5 flash memory block confi guration ........................................................................ 663 figure 19.6 programming/erasing flow chart example in user program mode ........................ 673 figure 19.7 flowchart for flas h memory emulatio n in ram ................................................... 674 figure 19.8 example of ra m overlap operation (ram[2:0] = b'000).................................... 675 figure 19.9 program/prog ram-verify fl owchart........................................................................ 677 figure 19.10 erase/eras e-verify flow chart ............................................................................... 679 figure 19.11 power on/off timing (boot mode)...................................................................... 685 figure 19.12 power on/off ti ming (user prog ram mode)........................................................ 686 figure 19.13 mode transit timing (example: boot mode user mode ? user program mode) ............................ 687 section 20 mask rom figure 20.1 mask rom block di agram..................................................................................... 689 section 22 user debugging interface (h-udi) figure 22.1 h-udi block diagram ............................................................................................ 69 4 figure 22.2 data input/o utput timing ch art (1)........................................................................ 701 figure 22.3 data input/o utput timing ch art (2)........................................................................ 702 figure 22.4 data input/o utput timing ch art (3)........................................................................ 702 figure 22.5 serial data inpu t/output......................................................................................... .704 section 23 advanced user debugger (aud) figure 23.1 aud block diagram............................................................................................... 7 06 figure 23.2 example of data output (32-b it output) ................................................................ 711 figure 23.3 example of output in case of successive branches ............................................... 711 figure 23.4 auda ta input fo rmat .......................................................................................... 712 rev.4.00 mar. 27, 2008, page xxxv of xliv rej09b0108-0400 figure 23.5 example of re ad operation (b yte read) ................................................................714 figure 23.6 example of writ e operation (longw ord write) .....................................................714 figure 23.7 example of erro r occurrence (longword read).....................................................714 section 24 power-down modes figure 24.1 nmi timing in software standby mode (application example) ...........................730 section 26 electrical characteristics figure 26.1 outp ut load circuit.............................................................................................. ...771 figure 26.2 sy stem clock timing .............................................................................................. 773 figure 26.3 extal clock input timing ...................................................................................773 figure 26.4 osc illation settli ng time........................................................................................ .773 figure 26.5 re set input timing ............................................................................................... ...775 figure 26.6 interrup t signal inpu t timi ng..................................................................................77 5 figure 26.7 interrupt signal output timing ...............................................................................776 figure 26.8 bu s release timing............................................................................................... ..776 figure 26.9 basi c cycle (n o waits) ........................................................................................... 778 figure 26.10 basic cycl e (one softwa re wait)..........................................................................779 figure 26.11 basic cycle (two softwa re waits + waits by wait signal) ..............................780 figure 26.12 dreq0 , dreq1 input timing (1)........................................................................781 figure 26.13 dreq0 , dreq1 input timing (2)........................................................................782 figure 26.14 drak output dela y time....................................................................................782 figure 26.15 mtu i nput/output tim ing .....................................................................................783 figure 26.16 mtu cl ock input ti ming.......................................................................................783 figure 26.17 i/o port input/output timing .................................................................................784 figure 26.18 wdt ti ming ...................................................................................................... ...785 figure 26.19 sci input timing................................................................................................ ...787 figure 26.20 sci input/output timing.......................................................................................78 7 figure 26.21 i 2 c bus interfa ce timing .......................................................................................789 figure 26.22 poe input/output timing .....................................................................................789 figure 26.23 external trigger input timing ..............................................................................790 figure 26.24 h- udi clock timing ............................................................................................79 1 figure 26.25 h-udi trst timing ............................................................................................792 figure 26.26 h-udi in put/output timing .................................................................................792 figure 26.27 aud reset timing................................................................................................ 794 figure 26.28 br anch trace timing............................................................................................. 794 figure 26.29 ram monitor ti ming ...........................................................................................794 appendix d i/o port block diagrams figure d.1 pan/rxdm .......................................................................................................... ....813 figure d.2 pan/txdm.......................................................................................................... .....814 figure d.3 pan/sckm/ dreqm / irqm .....................................................................................815 rev.4.00 mar. 27, 2008 page xxxvi of xliv rej09b0108-0400 figure d.4 pan/tclkm/ csx .................................................................................................... 816 figure d.5 pan/tclkm/ irqx .................................................................................................. 817 figure d.6 pan/function 1.................................................................................................... ..... 818 figure d.7 pa15/ck ........................................................................................................... ....... 819 figure d.8 pa16/ audsync ..................................................................................................... 820 figure d.9 pa17/ wait ............................................................................................................. 821 figure d.10 pa18/ breq /drak0............................................................................................. 822 figure d.11 pa19/ back /drak1 ............................................................................................ 823 figure d.12 pan.............................................................................................................. ........... 824 figure d.13 pan/function 2................................................................................................... .... 825 figure d.14 pbn/am ........................................................................................................... ....... 826 figure d.15 pbn/ irqm / poem /function 1 ................................................................................ 827 figure d.16 pbn/ irqm / poem .................................................................................................. 828 figure d.17 pbn/ irqm / poem / csx .......................................................................................... 829 figure d.18 pb6/ irq4 /a18/ back ........................................................................................... 830 figure d.19 pb7/ irq5 /a19/ breq ............................................................................................ 831 figure d.20 pb8/ irq6 /a20/ wait ............................................................................................ 832 figure d.21 pb9/ irq7 /a21/ adtrg ........................................................................................ 833 figure d.22 pcn/an ........................................................................................................... ........ 834 figure d.23 pdn/dn........................................................................................................... ........ 835 figure d.24 pdn/dn/audatam .............................................................................................. 836 figure d.25 pdn/dn/function 1................................................................................................ .837 figure d.26 pdn/dn/function 2................................................................................................ .838 figure d.27 pdn/dn/ irqm ........................................................................................................ 839 figure d.28 pdn/dn/ irqm /audatam................................................................................... 840 figure d.29 pdn/dn/ irqm /function 1...................................................................................... 841 figure d.30 pdn/dn/ irqm /function 2...................................................................................... 842 figure d.31 pdn/dn/function 3................................................................................................ .843 figure d.32 pdn/dn/function 4................................................................................................ .844 figure d.33 pdn/dn/ csm .......................................................................................................... 845 figure d.34 pen/ti ocxx/functio n 1......................................................................................... 846 figure d.35 pen/ti ocxx/functio n 2......................................................................................... 847 figure d.36 pe n/tiocxx/sckm ............................................................................................... 848 figure d.37 pe 9/tioc3b/sck3 ............................................................................................... 849 figure d.38 pe 11/tioc3d/ rxd3............................................................................................. 850 figure d.39 pe 12/tioc4a/ txd3............................................................................................. 851 figure d.40 pe13/tioc4b/ mres ............................................................................................ 852 figure d.41 pe 14/tioc4c/ dack0 .......................................................................................... 853 figure d.42 pe15/tioc4d/dack1/ irqout .......................................................................... 854 figure d.43 pen/tiocxx /function 1/fu nction 2....................................................................... 855 rev.4.00 mar. 27, 2008, page xxxvii of xliv rej09b0108-0400 figure d.44 pe1/tioc0b/drak0/ trst .................................................................................856 figure d.45 pe3/ tioc0d/drak1 /tdo...................................................................................857 figure d.46 pe0/tioc0a/ dreq0 /audck .............................................................................858 figure d.47 pe1/ti oc0b/drak0/ audmd ............................................................................859 figure d.48 pe2/tioc0c/ dreq1 / audrst ............................................................................860 figure d.49 pen/tiocxx /function 1/a udatam....................................................................861 figure d.50 pe4/ti oc1a/rxd3/aud ata2...........................................................................862 figure d.51 pe6/ti oc2a/sck3/a udata0............................................................................863 figure d.52 pe8/ tioc3a/sck2/ tms ......................................................................................864 figure d.53 pe9/tioc3b/sck3/ trst .....................................................................................865 figure d.54 pe10 /tioc3c/txd2 /tdi .....................................................................................866 figure d.55 pe11 /tioc3d/rxd3 /tdo ...................................................................................867 figure d.56 pe12 /tioc4a/txd3 /tck....................................................................................868 figure d.57 pf n/ann .......................................................................................................... .......869 appendix e package dimensions figure e.1 fp-112b ........................................................................................................... .........870 figure e.2 fp-144f........................................................................................................... ..........871 rev.4.00 mar. 27, 2008 page xxxviii of xliv rej09b0108-0400 rev.4.00 mar. 27, 2008, page xxxix of xliv rej09b0108-0400 tables section 2 cpu table 2.1 initial values of registers.......................................................................................18 table 2.2 sign extension of word data .................................................................................21 table 2.3 delayed branch instructions...................................................................................22 table 2.4 t bit ........................................................................................................................22 table 2.5 immediate data accessing......................................................................................23 table 2.6 absolute addre ss accessing...................................................................................23 table 2.7 displacement accessing .........................................................................................24 table 2.8 addressing modes and ef fective addresses...........................................................25 table 2.9 instruction formats .................................................................................................29 table 2.10 classification of instructions ..................................................................................32 section 3 mcu operating modes table 3.1 selection of operating modes.................................................................................47 table 3.2 clock mode setting ................................................................................................48 table 3.3 pin configuration....................................................................................................49 section 4 clock pulse generator table 4.1 operating clock fo r each module ..........................................................................54 table 4.2 damping resistance values (recommended values) ............................................55 table 4.3 crystal resonator characteris tics ...........................................................................56 section 5 exception processing table 5.1 types of exception processi ng and priority order .................................................61 table 5.2 timing for exception source detection and start of exception processing...........62 table 5.3 exception processing vector table ........................................................................63 table 5.4 calculating exception processing vector table addresses....................................64 table 5.5 reset st atus.............................................................................................................65 table 5.6 bus cycles and a ddress errors...............................................................................67 table 5.7 interrupt sources.....................................................................................................69 table 5.8 interrupt priority .....................................................................................................70 table 5.9 types of exceptions trig gered by instructions ......................................................71 table 5.10 generation of exception sources immediately after delayed branch instruction or interrupt- disabled instruction ..........................................................73 table 5.11 stack status after excep tion processing ends ........................................................74 section 6 interrupt controller (intc) table 6.1 pin configuration....................................................................................................79 table 6.2 interrupt exception processing vectors and priorities............................................90 table 6.3 interrupt response time.........................................................................................96 rev.4.00 mar. 27, 2008 page xl of xliv rej09b0108-0400 section 8 data transfer controller (dtc) table 8.1 interrupt sources, dtc vector addr esses, and corres ponding dtes ................. 124 table 8.2 normal mode regist er functions ......................................................................... 127 table 8.3 repeat mode regist er functions .......................................................................... 128 table 8.4 block transfer mode re gister functions ............................................................. 129 table 8.5 execution state of dtc ........................................................................................ 133 table 8.6 state counts needed fo r execution state ............................................................. 133 section 9 bus state controller (bsc) table 9.1 pin configuration.................................................................................................. 139 table 9.2 address ma p ......................................................................................................... 142 table 9.3 access to on-chip periphe ral i/o regi sters.......................................................... 166 section 10 direct memory access controller (dmac) table 10.1 dmac pin configuration..................................................................................... 169 table 10.2 selecting external request modes with rs bits .................................................. 182 table 10.3 selecting on-chip peripheral module request modes wi th rs bits ................... 183 table 10.4 supported dma transfers.................................................................................... 187 table 10.5 relationship of request modes and bus modes by dma transfer category ..... 196 table 10.6 transfer conditions and register set values for transfer between on-chip sci and external memory ........................................................ 206 table 10.7 transfer conditions and register set values for transfer between external ram and exte rnal device with dack................................... 207 table 10.8 transfer conditions and register set values for transfer between a/d converter (a/d1) and on-chip memory ........................................ 208 table 10.9 dmac internal status .......................................................................................... 209 table 10.10 transfer conditions and register set values for transfer between external memory an d sci1 transmit side............................................. 210 section 11 multi-functi on timer pulse unit (mtu) table 11.1 mtu functio ns..................................................................................................... 214 table 11.2 pin configuration.................................................................................................. 217 table 11.3 cclr0 to cclr2 (channels 0, 3, and 4) ............................................................ 221 table 11.4 cclr0 to cclr2 (channels 1 and 2) ................................................................. 221 table 11.5 tpsc0 to tpsc2 (channel 0) .............................................................................. 222 table 11.6 tpsc0 to tpsc2 (channel 1) .............................................................................. 222 table 11.7 tpsc0 to tpsc2 (channel 2) .............................................................................. 223 table 11.8 tpsc0 to tpsc2 (cha nnels 3 an d 4) ................................................................... 223 table 11.9 md0 to md 3 ........................................................................................................ 225 table 11.10 tiorh_0 (cha nnel 0) .......................................................................................... 228 table 11.11 tiorl_0 (channel 0)........................................................................................... 229 table 11.12 tior_1 (channel 1) ............................................................................................. 230 rev.4.00 mar. 27, 2008, page xli of xliv rej09b0108-0400 table 11.13 tior_2 (channel 2) .............................................................................................231 table 11.14 tiorh_3 (cha nnel 3) ..........................................................................................232 table 11.15 tiorl_3 (channel 3)...........................................................................................233 table 11.16 tiorh_4 (cha nnel 4) ..........................................................................................234 table 11.17 tiorl_4 (channel 4)...........................................................................................235 table 11.18 tiorh_0 (cha nnel 0) ..........................................................................................236 table 11.19 tiorl_0 (channel 0)...........................................................................................237 table 11.20 tior_1 (channel 1) .............................................................................................238 table 11.21 tior_2 (channel 2) .............................................................................................239 table 11.22 tiorh_3 (cha nnel 3) ..........................................................................................240 table 11.23 tiorl_3 (channel 3)...........................................................................................241 table 11.24 tiorh_4 (cha nnel 4) ..........................................................................................242 table 11.25 tiorl_4 (channel 4)...........................................................................................243 table 11.26 output level sel ect functio n ...............................................................................253 table 11.27 output level sel ect functio n ...............................................................................254 table 11.28 output level sel ect functio n.................................................................................256 table 11.29 register combinations in buffer oper ation .........................................................266 table 11.30 cascaded comb inations........................................................................................269 table 11.31 pwm output registers and output pins ..............................................................272 table 11.32 phase counting mode cl ock input pins ...............................................................276 table 11.33 up/down-count conditions in phase counting mode 1......................................277 table 11.34 up/down-count conditions in phase counting mode 2......................................278 table 11.35 up/down-count conditions in phase counting mode 3......................................279 table 11.36 up/down-count conditions in phase counting mode 4......................................280 table 11.37 output pins for reset-sy nchronized pwm mode ................................................282 table 11.38 register settings for reset- synchronized pwm mode ........................................282 table 11.39 output pins for comple mentary pwm mode.......................................................285 table 11.40 register settings for comp lementary pw m mode ..............................................286 table 11.41 registers and counters re quiring initiali zation ...................................................293 table 11.42 mtu interrupts .....................................................................................................311 table 11.43 mode transition co mbinations ............................................................................337 table 11.44 pin configuration..................................................................................................370 table 11.45 pin combinations..................................................................................................370 section 12 watchdog timer (wdt) table 12.1 pin configuration..................................................................................................380 table 12.2 wdt interrupt source (in interval timer mode) .................................................388 section 13 serial commu nication interface (sci) table 13.1 pin configuration..................................................................................................395 table 13.2 relationships between n setting in brr and effective bit rate b 0 ....................416 rev.4.00 mar. 27, 2008 page xlii of xliv rej09b0108-0400 table 13.3 brr settings for various bit rates (asynchronous mode) (1) ........................... 418 table 13.3 brr settings for various bit rates (asynchronous mode) (2) ........................... 418 table 13.3 brr settings for various bit rates (asynchronous mode) (3) ........................... 419 table 13.3 brr settings for various bit rates (asynchronous mode) (4) ........................... 419 table 13.4 maximum bit rate for each frequency when using baud rate generator (asynchronous mode) .......................................................................................... 420 table 13.5 maximum bit rate with external cl ock input (asynchronous mode) ................ 421 table 13.6 brr settings for various bit rates (clo cked synchronous mode) (1) ............... 422 table 13.6 brr settings for various bit rates (clo cked synchronous mode) (2) ............... 422 table 13.6 brr settings for various bit rates (clo cked synchronous mode) (3) ............... 423 table 13.6 brr settings for various bit rates (clo cked synchronous mode) (4) ............... 423 table 13.7 maximum bit rate with external clock input (clocked synchronous mode) .... 424 table 13.8 examples of bit rate for various brr settings (smart card interface mode) (when n = 0 and s = 372)..................................................................................... 425 table 13.9 maximum bit rate at various frequencies (smart card interface mode) (when s = 372)...................................................................................................... 425 table 13.10 serial transfer formats (asynchronous mode).................................................... 427 table 13.11 ssr status flags and recei ve data ha ndling ...................................................... 434 table 13.12 interrupt sources in serial co mmunication interf ace mode ................................ 461 table 13.13 interrupt sources in smart card interface mode .................................................. 462 section 14 i 2 c bus interface (iic) option table 14.1 pin configuration.................................................................................................. 470 table 14.2 transfer format .................................................................................................... 473 table 14.3 setting of the tran sfer rate .................................................................................. 476 table 14.4 the relationship between flags and tr ansfer states (master mode)................... 483 table 14.5 the relationship between flags and tr ansfer states (slave mode)..................... 484 table 14.6 i 2 c bus data format: descri ption of symbols ..................................................... 494 table 14.7 examples of operations in which the dtc is used ............................................. 525 table 14.8 i 2 c bus timing (output of scl and sda) ........................................................... 528 table 14.9 tolerance of the scl rise time (t sr ) .................................................................... 529 table 14.10 i 2 c bus timing (when the effect of t sr /t sf is at its maximum)................................ 531 section 15 a/d converter table 15.1 pin configuration.................................................................................................. 543 table 15.2 channel select list ............................................................................................... 546 table 15.3 a/d conversion time (single mode)................................................................... 551 table 15.4 a/d conversion time (scan mode) ..................................................................... 552 table 15.5 a/d converter inte rrupt sour ces .......................................................................... 553 table 15.6 analog pin speci fications..................................................................................... 558 rev.4.00 mar. 27, 2008, page xliii of xliv rej09b0108-0400 section 17 pin function controller (pfc) table 17.1 sh7144 multiplexed pins (port a) .......................................................................569 table 17.2 sh7144 multiplexed pi ns (port b) .......................................................................570 table 17.3 sh7144 multiplexed pins (port c) .......................................................................570 table 17.4 sh7144 multiplexed pins (port d) .......................................................................571 table 17.5 sh7144 multiplexed pins (port e) .......................................................................572 table 17.6 sh7144 multiplexed pins (port f)........................................................................572 table 17.7 sh7145 multiplexed pins (port a) .......................................................................573 table 17.8 sh7145 multiplexed pins (port b) .......................................................................574 table 17.9 sh7145 multiplexed pins (port c) .......................................................................574 table 17.10 sh7145 multiplexed pi ns (port d) .......................................................................575 table 17.11 sh7145 multiplexed pi ns (port e) .......................................................................576 table 17.12 sh7145 multiplexed pi ns (port f)........................................................................576 table 17.13 sh7144 pin functions in each mode (1) .............................................................577 table 17.13 sh7144 pin functions in each mode (2) .............................................................581 table 17.14 sh7145 pin functions in each mode (1) .............................................................585 table 17.14 sh7145 pin functions in each mode (2) .............................................................590 table 17.15 transmit forms of input functions allocated to mult iple pins ...........................631 section 18 i/o ports table 18.1 port a data register (padr) read/write op erations .........................................638 table 18.2 port b data register (pbdr) read/write op erations..........................................641 table 18.3 port c data register (pcdr) read/write op erations..........................................644 table 18.4 port d data register (pddr) read/write op erations .........................................649 table 18.5 port e data register l (pedrl ) read/write operations ....................................653 table 18.6 port f data register (pfdr) read/write op erations...........................................655 section 19 flash memory (f-ztat version) table 19.1 differences between boot mode and user prog ram mode...................................660 table 19.2 pin configuration..................................................................................................664 table 19.3 setting on-board prog ramming modes................................................................670 table 19.4 boot mode operation ...........................................................................................672 table 19.5 peripheral clock (p ) frequencies for which automatic adjustment of lsi bit rate is possible ........................................................................................672 section 22 user debugging interface (h-udi) table 22.1 h-udi pins ...........................................................................................................695 table 22.2 serial transfer characteristic s of h-udi registers..............................................696 section 23 advanced user debugger (aud) table 23.1 aud pin configuration ........................................................................................707 table 23.2 ready flag format................................................................................................713 rev.4.00 mar. 27, 2008 page xliv of xliv rej09b0108-0400 section 24 power-down modes table 24.1 internal operation stat es in each mode ............................................................... 720 table 24.2 pin configuration.................................................................................................. 721 section 26 electrical characteristics table 26.1 absolute maximu m ratings ................................................................................. 767 table 26.2 dc character istics ................................................................................................ 768 table 26.3 permitted output cu rrent values.......................................................................... 770 table 26.4 clock timing ........................................................................................................ 772 table 26.5 control signal timing .......................................................................................... 774 table 26.6 bus timing ........................................................................................................... 777 table 26.7 direct memory access controller ti ming ........................................................... 781 table 26.8 multi-function timer pu lse unit ti ming ............................................................. 783 table 26.9 i/o port ti ming..................................................................................................... 784 table 26.10 watchdog time r timing....................................................................................... 785 table 26.11 serial communication interface ti ming............................................................... 786 table 26.12 i 2 c bus interfa ce timing ...................................................................................... 788 table 26.13 port output enab le timi ng................................................................................... 789 table 26.14 a/d converter timing.......................................................................................... 790 table 26.15 h-udi timi ng ...................................................................................................... 791 table 26.16 aud timi ng......................................................................................................... 793 table 26.17 a/d converter char acteristic s .............................................................................. 795 table 26.18 flash memory char acteristi cs .............................................................................. 796 appendix a pin states table a.1 pin states (s h7144).............................................................................................. 799 table a.2 pin states (s h7145).............................................................................................. 803 table a.3 pin stat es .............................................................................................................. 807 table a.4 pin stat es .............................................................................................................. 807 table a.5 pin stat es .............................................................................................................. 808 appendix b pin states of bus related signals table b.1 pin states of bus rela ted signals (1).................................................................... 809 table b.1 pin states of bus rela ted signals (2).................................................................... 810 table b.1 pin states of bus rela ted signals (3).................................................................... 811 1. overview rev.4.00 mar. 27, 2008 page 1 of 882 rej09b0108-0400 section 1 overview the sh7144 group and sh7145 group single-chip risc (reduced instruction set computer) microcomputers integrate a renesas technology original risc cpu core with peripheral functions required for system configuration. the sh7144 group and sh7145 group cpu has a risc-type instruction set . most instructions can be executed in one state (one system cl ock cycle), which greatly improves instruction execution speed . in addition, the 32-bit internal-bus architecture enhances data processing power. with this cpu, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microcomputers, such as real- time control, which demands high speeds. in addition, the sh7144 group and sh7145 group includes on-chip peripheral functions necessary for system configuration, such as a direct memory access controller (dmac), large- capacity rom and ram, timers, a serial communica tion interface (sci), an a/d converter, an interrupt controller (intc), and i/o ports. as an option, an i 2 c bus interface can also be incorporated. rom and sram can be directly connected to the sh7144 group and sh7145 group mcu by means of an external memory access support fu nction. this greatly reduces system cost. there are two versions of on-chip rom: f-ztat tm * (flexible zero turn around time) that includes flash memory, and masked rom. the flash memory can be programmed with a programmer that supports sh7144 group and sh7145 group programming, and can also be programmed and erased by softwa re. this enables lsi chip to be re-programmed at a user side while mounted on a board. note: * f-ztat is a registered trad emark of renesas technology corp. 1. overview rev.4.00 mar. 27, 2008 page 2 of 882 rej09b0108-0400 1.1 features ? central processing unit with an internal 32 -bit risc (reduced instruction set computer) architecture ? instruction length: 16-bit fixed length for improved code efficiency ? load-store architecture (basic opera tions are executed between registers) ? sixteen 32-bit general registers ? five-stage pipeline ? on-chip multiplier: multiplication operations (32 bits 32 bits 64 bits) executed in two to four cycles ? c language-oriented 62 basic instructions ? various peripheral functions ? direct memory access controller (dmac) ? data transfer controller (dtc) ? multifunction timer/pulse unit (mtu) ? compare match timer (cmt) ? watchdog timer (wdt) ? asynchronous or clocked synchronous serial communication interface (sci) ? i 2 c bus interface (iic)* 1 ? 10-bit a/d converter ? clock pulse generator ? user break controller (ubc) ? user debugging interface (h-udi)* 2 ? advanced user debugger (aud)* 2 notes: 1. option 2. supported only for flash memory version. 1. overview rev.4.00 mar. 27, 2008 page 3 of 882 rej09b0108-0400 ? on-chip memory rom part no. rom ram hd64f7144f50 256 kbytes 8 kbytes flash memory version hd64f7145f50 256 kbytes 8 kbytes hd6437144f50 256 kbytes 8 kbytes masked rom version hd6437145f50 256 kbytes 8 kbytes rom less version hd6417144f50 ? 8 kbytes hd6417145f50 ? 8 kbytes ? i/o ports part no. no. of i/o pins no. of input-only pins hd64f7144f50/ hd6437144f50/ hd6417144f50 74 8 hd64f7145f50/ hd6437145f50/ hd6417145f50 98 8 ? supports various power-down states ? compact package part no. package (code) body size pin pitch hd64f7144f50/ hd6437144f50/ hd6417144f50 qfp-112 fp-112b 20.0 20.0 mm 0.65 mm hd64f7145f50/ hd6437145f50/ hd6417145f50 lqfp-144 fp-144f 20.0 20.0 mm 0.5 mm 1. overview rev.4.00 mar. 27, 2008 page 4 of 882 rej09b0108-0400 1.2 internal block diagram pe15/tioc4d/dack1/ irqout pe14/tioc4c/dack0 pe13/tioc4b/ mres pe12/tioc4a/txd3 pe11/tioc3d/rxd3 pe10/tioc3c/txd2 pe9/tioc3b/sck3 pe8/tioc3a/sck2 pe7/tioc2b/rxd2 pe6/tioc2a/sck3 pe5/tioc1b/txd3 pe4/tioc1a/rxd3/tck pe3/tioc0d/drak1/tdo pe2/tioc0c/ dreq1 /tdi pe1/tioc0b/drak0/ trst pe0/tioc0a/ dreq0 /tms peripheral address bus (12bits) peripheral data bus (16bits) internal address bus (32bits) internal upper data bus (16bits) internal lower data bus (16bits) res wdtovf md3 md2 md1 md0 nmi extal xtal pllvcc pllcap pllvss fwp * vcc vcc vcc vss vss vss vss vss vss vss vss vss vss avcc avss dbgmd asebrkak serial communication interface ( 4 channels) compare match timer ( 2 channels) i 2 c bus interface interrupt controller user break controller bus state controller a/d converter watchdo g timer multifunction timer pulse unit cpu data transfer controller direct memory access controller ram 8kb p l l pd15/d15/ audsyn c pd14/d14/audck pd13/d13/audmd pd12/d12/ audrst pd11/d11/audata3 pd10/d10/audata2 pd9/d9/audata1 pd8/d8/audata0 pd7/d7 pd6/d6 pd5/d5 pd4/d4 pd3/d3 pd2/d2 pd1/d1 pd0/d0 pf7/an7 pf6/an6 pf5/an5 pf4/an4 pf3/an3 pf2/an2 pf1/an1 pf0/an0 h-udi * pb9/ irq7 /a21/ adtrg pb8/ irq6 /a20/ wait pb7/ irq5 /a19/ breq pb6/ irq4 /a18/ back pb5/ irq3 / poe3 / cs7 pb4/ irq2 / poe2 / cs6 pb3/ irq1 / poe1 /sda0 pb2/ irq0 / poe0 /scl0 pb1/a17 pb0/a16 pc15/a15 pc14/a14 pc13/a13 pc12/a12 pc11/a11 pc10/a10 pc9/a9 pc8/a8 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pa15/ck pa14/ rd pa13/ wrh pa12/ wrl pa11/ cs1 pa10/ cs0 pa9/tclkd/ irq3 pa8/tclkc/ irq2 pa7/tclkb/ cs3 pa6/tclka/ cs2 pa5/sck1/ dreq1 / irq 1 pa4/txd1 pa3/rxd1 pa2/sck0/ dreq0 / irq 0 pa1/txd0 pa0/rxd0 aud * flash rom/ mask rom 256kb note: * pin and modules for the f-ztat reision only figure 1.1 internal block diagram of sh7144 1. overview rev.4.00 mar. 27, 2008 page 5 of 882 rej09b0108-0400 pe15/tioc4d/dack1/ irqout pe14/tioc4c/dack0 pe13/tioc4b/ mres pe12/tioc4a/txd3/tck pe11/tioc3d/rxd3/tdo pe10/tioc3c/txd2/tdi pe9/tioc3b/sck3/ trst pe8/tioc3a/sck2/tms pe7/tioc2b/rxd2 pe6/tioc2a/sck3/audata0 pe5/tioc1b/txd3/audata1 pe4/tioc1a/rxd3/audata2 pe3/tioc0d/drak1/audata3 pe2/tioc0c/ dreq1 / audrst pe1/tioc0b/drak0/audmd pe0/tioc0a/ dreq0 /audck res wdtovf md3 md2 md1 md0 nmi extal xtal pllvcc pllcap pllvss fwp * vcc vcc vcc vcc vcc vcc vcc vss vss vss vss vss vss vss vss vss vss vss vss vss avcc avref avss dbgmd asebrkak cpu ram 8kb p l l pd31/d31/ adtrg pd30/d30/ irqout pd29/d29/ cs3 pd28/d28/ cs2 pd27/d27/dack1 pd26/d26/dack0 pd25/d25/ dreq1 pd24/d24/ dreq0 pd23/d23/ irq7 / audsyn c pd22/d22/ irq6 /audck pd21/d21/ irq5 /audmd pd20/d20/ irq4 / audrst pd19/d19/ irq3 /audata3 pd18/d18/ irq2 /audata2 pd17/d17/ irq1 /audata1 pd16/d16/ irq0 /audata0 pf7/an7 pf6/an6 pf5/an5 pf4/an4 pf3/an3 pf2/an2 pf1/an1 pf0/an0 h-udi * pd15/d15 pd14/d14 pd13/d13 pd12/d12 pd11/d11 pd10/d10 pd9/d9 pd8/d8 pd7/d7 pd6/d6 pd5/d5 pd4/d4 pd3/d3 pd2/d2 pd1/d1 pd0/d0 pb9/ irq7 /a21/ adtrg pb8/ irq6 /a20/ wait pb7/ irq5 /a19/ breq pb6/ irq4 /a18/ back pb5/ irq3 / poe3 / cs7 pb4/ irq2 / poe2 / cs6 pb3/ irq1 / poe1 /sda0 pb2/ irq0 / poe0 /scl0 pb1/a17 pb0/a16 pc15/a15 pc14/a14 pc13/a13 pc12/a12 pc11/a11 pc10/a10 pc9/a9 pc8/a8 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 pa23/ wrhh pa22/ wrhl pa21/ cs5 pa20/ cs4 pa19/ back /drak1 pa18/ breq /drak0 pa17/ wait pa16/ audsync pa15/ck pa14/ rd pa13/ wrh pa12/ wrl pa11/ cs1 pa10/ cs0 pa9/tclkd/ irq3 pa8/tclkc/ irq2 pa7/tclkb/ cs3 pa6/tclka/ cs2 pa5/sck1/ dreq1 / irq1 pa4/txd1 pa3/rxd1 pa2/sck0/ dreq0 / irq0 pa1/txd0 pa0/rxd0 aud * note: * pin and modules for the f-ztat reision only serial communication interface ( 4 channels) compare match timer ( 2 channels) i 2 c bus interface interrupt controller user break controller bus state controller a/d converter watchdo g timer multifunction timer pulse unit data transfer controller direct memory access controller flash rom/ mask rom 256kb peripheral address bus (12bits) peripheral data bus (16bits) internal address bus (32bits) internal upper data bus (16bits) internal lower data bus (16bits) figure 1.2 block diagram of sh7145 1. overview rev.4.00 mar. 27, 2008 page 6 of 882 rej09b0108-0400 1.3 pin arrangement 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 pd12/d12/ audrst * 4 vss pd13/d13/audmd * 4 pd14/d14/audck * 4 pd15/d15/ audsync * 4 pa0/rxd0 pa1/txd0 pa2/sck0/ dreq0 / irq 0 pa3/rxd1 pa4/txd1 pa5/sck1/ dreq1 / irq 1 pa6/tclka/ cs2 pa7/tclkb/ cs3 pa8/tclkc/ irq2 pa9/tclkd/ irq3 pa10/ cs0 pa11/ cs1 vss pa12/ wrl vcc pa13/ wrh wdtovf pa14/ rd vss(dbgmd * 3 ) pb9/ irq7 /a21/ adtrg pb8/ irq6 /a20/ wait pb7/ irq5 /a19/ breq pb6/ irq4 /a18/ back pe14/tioc4c/dack0 pe15/tioc4d/dack1/ irqout vss pc0/a0 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pc8/a8 pc9/a9 pc10/a10 pc11/a11 pc12/a12 pc13/a13 pc14/a14 pc15/a15 pb0/a16 vcc pb1/a17 vss pb2/ irq0 / poe0 /scl0 pb3/ irq1 / poe1 /sda0 pb4/ irq2 / poe2 / cs6 * 5 asebrkak * 2 pb5/ irq3 / poe3 / cs7 * 5 res pa15/ck pllvss pllcap pllvcc md0 md1 vcc(fwp * 1 ) nmi md2 extal md3 xtal vss pd0/d0 pd1/d1 pd2/d2 pd3/d3 pd4/d4 vcc pd5/d5 pd6/d6 pd7/d7 vss pd8/d8/audata0 * 4 pd9/d9/audata1 * 4 pd10/d10/audata2 * 4 pd11/d11/audata3 * 4 pe0/tioc0a/ dreq0 /tms * 4 pe1/tioc0b/drak0/ trst * 4 pe2/tioc0c/ dreq1 /tdi * 4 pe3/tioc0d/drak1/tdo * 4 pe4/tioc1a/rxd3/tck * 4 vss pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 avss pf6/an6 pf7/an7 avcc vss pe5/tioc1b/txd3 vcc pe6/tioc2a/sck3 pe7/tioc2b/rxd2 pe8/tioc3a/sck2 pe9/tioc3b/sck3 pe10/tioc3c/txd2 vss pe11/tioc3d/rxd3 pe12/tioc4a/txd3 pe13/tioc4b/ mres qfp-112 (top view) notes : 1. fixed as vcc in the masked rom version and rom less version, and used as an fwp input pin in the f-ztat version (used as an fwe in pro g rammer mode). 2. used for e10a debu gg in g mode. used as an asebrkak output pin in the f-ztat version. refer to the table below for processin g the asebrkak pin. 3. used for e10a debu gg in g mode. fixed to vss in the masked rom version and rom less version, or used as a dbgmd input pin in the f-ztat version. 4. valid only in the f-ztat version (invalid only in the masked rom version and rom less version). 5. valid only in the masked rom version and rom less version (invalid in the f-ztat version and emulator). product type masked rom version and rom less version f-ztat version (when usin g e10a) f-ztat version (not when usin g e10a) processin g fixed to vcc yes no yes fixed to vss yes no yes pull-up yes yes yes pull-down yes no yes nc no no no asebrkak processin g figure 1.3 sh7144 pin arrangement 1. overview rev.4.00 mar. 27, 2008 page 7 of 882 rej09b0108-0400 lqfp-144 (top view) pa23/ wrhh pe14/tioc4c/dack0 pa22/ wrhl pa21/ cs5 * 5 pe15/tioc4d/dack1/ irqout vss pc0/a0 pc1/a1 pc2/a2 pc3/a3 pc4/a4 vcc pc5/a5 vss pc6/a6 pc7/a7 pc8/a8 pc9/a9 pc10/a10 pc11/a11 pc12/a12 pc13/a13 pc14/a14 pc15/a15 pb0/a16 vcc pb1/a17 vss pa20/ cs4 * 5 pa19/ back /drak1 pb2/ irq0 / poe0 /scl0 pb3/ irq1 / poe1 /sda0 pa18/ breq /drak0 pb4/ irq2 / poe2 / cs6 * 5 asebrkak * 2 pb5/ irq3 / poe3 / cs7 * 5 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 res pa15/ck pllvss pllcap pllvcc md0 md1 pa17/ wait pa16/ audsync * 4 vcc(fwp * 1 ) nmi md2 extal md3 xtal vss pd0/d0 pd1/d1 pd2/d2 pd3/d3 pd4/d4 vss pd5/d5 vcc pd6/d6 pd7/d7 pd8/d8 pd9/d9 pd10/d10 vss pd11/d11 vcc pd12/d12 pd13/d13 pd14/d14 pd15/d15 pe0/tioc0a/ dreq0 /audck * 4 pe1/tioc0b/drak0/audmd * 4 pe2/tioc0c/ dreq1 / audrst * 4 vcc pe3/tioc0d/drak1/audata3 * 4 pe4/tioc1a/rxd3/audata2 * 4 pe5/tioc1b/txd3/audata1 * 4 pe6/tioc2a/sck3/audata0 * 4 vss pf0/an0 pf1/an1 pf2/an2 pf3/an3 pf4/an4 pf5/an5 avss pf6/an6 pf7/an7 avref avcc vss pa0/rxd0 pa1/txd0 pa2/sck0/ dreq0 / irq0 pa3/rxd1 pa4/txd1 vcc pa5/sck1/ dreq1 / irq1 pe7/tioc2b/rxd2 pe8/tioc3a/sck2/tms * 4 pe9/tioc3b/ trst * 4 /sck3 pe10/tioc3c/txd2/tdi * 4 vss pe11/tioc3d/tdo * 4 /rxd3 pe12/tioc4a/tck * 4 /txd3 pe13/tioc4b/ mres pd16/d16/ irq0 /audata0 * 4 vss pd17/d17/ irq1 /audata1 * 4 pd18/d18/ irq2 /audata2 * 4 pd19/d19/ irq3 /audata3 * 4 pd20/d20/ irq4 / audrst * 4 pd21/d21/ irq5 /audmd * 4 pd22/d22/ irq6 /audck * 4 pd23/d23/ irq7 / audsync * 4 vcc pd24/d24/ derq0 vss pd25/d25/ dreq1 pd26/d26/dack0 pd27/d27/dack1 pd28/d28/ cs2 pd29/d29/ cs3 vss pa6/tclka/ cs2 pa7/tclkb/ cs3 pa8/tclkc/ irq2 pa9/tclkd/ irq3 pa10/ cs0 pa11/ cs1 pa12/ wrl pa13/ wrh pd30/d30/ irqout pd31/d31/ adtrg wdtovf pa14/ rd vss(dbgmd * 3 ) pb9/ irq7 /a21/ adtrg vcc pb8/ irq6 /a20/ wait pb7/ irq5 /a19/ breq pb6/ irq4 /a18/ back 123456789101112131415161718192021222324252627282930313233343536 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 6 3 62 61 60 59 58 57 56 55 54 5 3 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 notes : 1. fixed as vcc in the masked rom version and rom less version, and used as an fwp input pin in the f-ztat version (used as an fwe in pro g rammer mode). 2. used for e10a debu gg in g mode. used as an asebrkak output pin in the f-ztat version. refer to the table below for processin g the asebrkak pin. 3. used for e10a debu gg in g mode. fixed to vss in the masked rom version and rom less version, or used as a dbgmd input pin in the f-ztat version. 4. valid only in the f-ztat version (invalid only in the masked rom version and rom less version). 5. valid only in the masked rom version and rom less version (invalid in the f-ztat version and emulator). product type masked rom version and rom less version f-ztat version (when usin g e10a) f-ztat version (not when usin g e10a) processin g fixed to vcc yes no yes fixed to vss yes no yes pull-up yes yes yes pull-down yes no yes nc no no no asebrkak processin g figure 1.4 sh7145 pin arrangement 1. overview rev.4.00 mar. 27, 2008 page 8 of 882 rej09b0108-0400 1.4 pin functions type symbol i/o name function v cc input power supply power supply pins. connect all these pins to the system power supply. the chip does not operate when some of these pins are opened. power supply v ss input ground ground pins. connect all these pins to the system power supply (0 v). the chip does not operate when some of these pins are opened. pllv cc input power supply for pll power supply pin for supplying power to on-chip pll. pllv ss input ground for pll on-chip pll oscillator ground pin. pllcap input capacitance for pll external capacitance pin for an on-chip pll oscillator. extal input external clock for connection to a crystal resonator. (an external clock can be supplied from the extal pin.) for examples of crystal resonator connection and external clock input, see section 4, clock pulse generator. xtal input crystal for connection to a crystal resonator. for examples of crystal resonator connection and external clock input, see section 4, clock pulse generator. clock ck output system clock output supplies the system clock to external devices. operating mode control md3 to md0 input set the mode set the operating mode. inputs at these pins should not be changed during operation. fwp input protection against write operation into flash memory pin for the flash memory. this pin is only used in the f-ztat version. programming or erasing of flash memory can be protected. this pin is used as vcc in the masked rom version and rom less version. 1. overview rev.4.00 mar. 27, 2008 page 9 of 882 rej09b0108-0400 type symbol i/o name function res input power on reset when this pin is driven low, the chip becomes to power on reset state. mres input manual reset when this pin is driven low, the chip becomes to manual reset state. wdtovf output watchdog timer overflow output signal for the watchdog timer overflow. if this pin needs to be pulled-down, the resistance value must be 1 m or higher. breq input bus request external device can request the release of the bus mastership by setting this pin low. system control back output bus acknowledge shows that the bus mastership has been released for the external device. the device that had issued the breq signal can know that bus mastership has been released for itself by receiving the back signal. nmi input non-maskable interrupt non-maskable interrupt pin. if this pin is not used, it should be fixed high or low. irq7 to irq0 input interrupt request 7 to 0 these pins request a maskable interrupt. one of the level input or edge input can be selected in case of the edge input, one of the rising edge, falling edge, or both can be selected. interrupts irqout output interrupt request output shows that an interrupt cause has occurred. the interrupt cause can be recognized even in the bus release state. address bus a21 to a0 output address bus output the address. data bus sh7144: d15 to d0 sh7145: d31 to d0 input/ output data bus sh7144: bi-directional 16-bit bus sh7145: bi-directional 32-bit bus 1. overview rev.4.00 mar. 27, 2008 page 10 of 882 rej09b0108-0400 type symbol i/o name function cs3 to cs0 output chip select 3 to 0 cs5 , cs4 (sh7145 masked rom version and rom less version only) output chip select 5, 4 cs7 , cs6 (masked rom version and rom less version only) output chip select 7, 6 chip select signal fo r external memory or devices. rd output read shows reading from external devices. wrhh (sh7145 only) output write hh shows writing in to the hh 8 bits (bits 31 to 24) of the external data. wrhl (sh7145 only) output write hl shows writing in to the hl 8 bits (bits 23 to 16) of the external data. wrh output write upper half shows writing into the upper 8 bits (bits 15 to 8) of the external data. wrl output write lower half shows writing into the lower 8 bits (bit7 to bit0) of the external data. bus control wait input wait inserts the wait cycles into the bus cycle when accessing the external spaces. dreq0 , dreq1 input dma transfer request dma request input pins from an external device. direct memory access controller (dmac) drak0, drak1 output dreq request acknowledge outputs an acknowledge signal to the external device that has input a dma transfer request signal. dack0, dack1 output dma transfer strobe outputs a strobe to the i/o of the external device that has input a dma transfer request signal. 1. overview rev.4.00 mar. 27, 2008 page 11 of 882 rej09b0108-0400 type symbol i/o name function tclka to tclkd input external clock input for mtu timer these pins input an external clock. tioc0a to tioc0d input/ output mtu input capture/output compare (channel 0) the tgra_0 to tgrd_0 input capture input/output compare output/pwm output pins. tioc1a, tioc1b input/ output mtu input capture/output compare (channel 1) the tgra_1 to tgrb_1 input capture input/output compare output/pwm output pins. tioc2a, tioc2b input/ output mtu input capture/output compare (channel 2) the tgra_2 to tgrb_2 input capture input/output compare output/pwm output pins. tioc3a to tioc3d input/ output mtu input capture/output compare (channel 3) the tgra_3 to tgrd_3 input capture input/output compare output/pwm output pins. multifunction timer-pulse unit (mtu) tioc4a to tioc4d input/ output mtu input capture/output compare (channel 4) the tgra_4 to tgrb_4 input capture input/output compare output/pwm output pins. txd3 to txd0 output transmitted data data output pins. rxd3 to rxd0 input received data data input pins. serial communication interface (sci) sck3 to sck0 input/ output serial clock clock input/output pins. i 2 c bus interface (option) scl0 input/ output i 2 c clock input/ output i 2 c bus clock input/output pins, which drive a bus. output a clock in the nmos open-drain method. sda0 input/ output i 2 c data input/ output i 2 c bus data input/output pins, which drive a bus. output data in the nmos open-drain method. 1. overview rev.4.00 mar. 27, 2008 page 12 of 882 rej09b0108-0400 type symbol i/o name function output control for mtu poe3 to poe0 input port output control input pins for the signal to request the output pins of mtu waveforms to become high impedance state. an7 to an0 input analog input pins analog input pins. adtrg input input of trigger for a/d conversion pin for input of an external trigger to start a/d conversion avref (sh7145 only) input analog reference power supply analog reference power supply pin, (in sh7144, this pin is internally connected to the avcc pin). av cc input analog power supply power supply pin for the a/d converter. when the a/d converter is not used, connect this pin to the system power supply (+3.3 v). a/d converter av ss input analog ground the ground pin for the a/d converter. connect this pin to the system power supply (0 v). i/o port sh7144 pa15 to pa0 sh7145 pa23 to pa0 input/ output general purpose port sh7144: 16-bit general purpose input/output pins. sh7145: 24-bit general purpose input/output pins. pb9 to pb0 input/ output general purpose port 10-bit general purpose input/output pins. pc15 to pc0 input/ output general purpose port 16-bit general purpose input/output pins. sh7144: pd15 to pd0 sh7145: pd31 to pd0 input/ output general purpose port sh7144: 16-bit general purpose input/output pins. sh7145: 32-bit general purpose input/output pins. pe15 to pe0 input/ output general purpose port 16-bit general purpose input/output pins. pf7 to pf0 input general purpose port 8-bit general purpose input pins. 1. overview rev.4.00 mar. 27, 2008 page 13 of 882 rej09b0108-0400 type symbol i/o name function tck input test clock test clock input pin. tms input test mode select test mode select signal input pin. tdi input test data input instruction/data serial input pin. tdo output test data output instruction/data serial output pin. user debugging interface (h-udi) (flash version only) trst input test reset initializ ation signal input pin. audata3 to audata0 input/ output aud data branch trace m ode: branch destination address output pins. ram monitor mode: monitor address input/data input/output pins. audrst input aud reset reset signal input pin. audmd input aud mode mode select signal input pin. branch trace mode: low ram monitor mode: high audck input/ output aud clock branch trace mode: synchronous clock output pin. ram monitor mode: synchronous clock input pin. advanced user debugger (aud) (flash version only) audsync input/ output aud synchroniza- tion signal branch trace mode: data start position identification signal output pin. ram monitor mode: data start position identification signal input pin. e10 interface (flash version only) asebrkak output break mode acknowledge shows that e10a has entered to the break mode. refer to ?sh7144f e10a emulator user?s manual? for the detail of the connection to e10a. dbgmd input debug mode enables the functions of e10a emulator. input low to the pin in normal operation (other than the debug mode). in debug mode, input high to the pin on the user board. refer to ?sh7144f e10a emulator user?s manual? for the detail of the connection to e10a. [caution] do not pull-down the wdtovf pin. if this pin needs to be pulled-down, however, the resistor value must be 1 m or higher. 1. overview rev.4.00 mar. 27, 2008 page 14 of 882 rej09b0108-0400 2. cpu cpus201a_020020030800 rev.4.00 mar. 27, 2008 page 15 of 882 rej09b0108-0400 section 2 cpu 2.1 features ? general-register architecture ? sixteen 32-bit general registers ? sixty-two basic instructions ? eleven addressing modes ? register direct [rn] ? register indirect [@rn] ? register indirect with post-increment [@rn+] ? register indirect with pre-decrement [@-rn] ? register indirect with displacement [@disp:4,rn] ? register indirect with index [@r0, rn] ? gbr indirect with disp lacement [@disp:8,gbr] ? gbr indirect with index [@r0,gbr] ? program-counter relative with displacement [@disp:8,pc] ? program-counter relative [disp:8/disp:12/rn] ? immediate [#imm:8] 2.2 register configuration the register set consists of sixteen 32-bit general re gisters, three 32-bit cont rol registers, and four 32-bit system registers. 2.2.1 general registers (rn) the sixteen 32-bit general registers (rn) are numbered r0 to r15. general registers are used for data processing and address calculation. r0 is also used as an index register. several instructions have r0 fixed as their only usable register. r15 is used as the hardware stack pointer (sp). saving and recovering the status register (sr) and prog ram counter (pc) in exception processing is accomplished by referencing the stack using r15. 2. cpu rev.4.00 mar. 27, 2008 page 16 of 882 rej09b0108-0400 31 0 r0 * 1 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15, sp (hardware stack pointer) * 2 general re g isters (rn) status re g ister (sr) global base re g ister (gbr) vector base re g ister (vbr) multiply-accumulate re g ister (mac) procedure re g ister pro g ram counter (pc) 31 9 8 7 6 5 4 3 2 1 0 0 0 31 m gbr 31 vbr qi3i2i1i0 s t 31 0 mach 31 0 pr 31 0 pc macl notes: 1. r0 functions as an index re g ister in the indirect indexed re g ister addressin g mode and indirect indexed gbr addressin g mode. in some instructions, r0 functions as a fixed source re g ister or destination re g ister. 2. r15 functions as a hardware stack pointer (sp) durin g exception processin g . figure 2.1 cpu internal registers 2. cpu rev.4.00 mar. 27, 2008 page 17 of 882 rej09b0108-0400 2.2.2 control registers the control registers consist of three 32-bit registers: status register (sr), global base register (gbr), and vector base register (vbr). the status register indicates proces sing states. the global base register functions as a base address for the indirect gbr addressing mode to transfer data to the registers of on-chip peripheral modules. the vector base register functions as the base address of the exception processing vector area (including interrupts). status register (sr): bit bit name initial value r/w description 31 to 10 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 9 m undefined r/w used by the div0 u, div0s, and div1 instructions. 8 q undefined r/w used by the div0 u, div0s, and div1 instructions. bit bit name initial value r/w description 7 6 5 4 i3 i2 i1 i0 1 1 1 1 r/w r/w r/w r/w interrupt mask bits. 3, 2 ? all 0 r/w reserved these bits are always read as 0. the write value should always be 0. 1 s undefined r/w s bit used by the mac instruction. 0 t undefined r/w t bit the movt, cmp/cond, tas, tst, bt (bt/s), bf (bf/s), sett, and clrt instructions use the t bit to indicate true (1) or false (0). the addv, addc, subv, subc, div0u, div0s, div1, negc, shar, shal , shlr, shll, rotr, rotl, rotcr, and rotcl inst ructions also use the t bit to indicate carry/bo rrow or overflow/underflow. 2. cpu rev.4.00 mar. 27, 2008 page 18 of 882 rej09b0108-0400 global base register (gbr): indicates the base address of th e indirect gbr addressing mode. the indirect gbr addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. vector base register (vbr): indicates the base address of the exception processing vector area. 2.2.3 system registers system registers consist of four 32-bit register s: high and low multiply and accumulate registers (mach and macl), the procedure register (pr), and the program counter (pc). multiply-and-accumulate registers (mac): registers to store the results of multiply-and- accumulate operations. procedure register (pr): registers to store the return ad dress from a subroutine procedure. program counter (pc): registers to indicate the sum of current instruction addresses and four, that is, the address of the second instruction after the current instruction. 2.2.4 initial values of registers table 2.1 lists the values of the registers after reset. table 2.1 initial values of registers classification register initial value r0 to r14 undefined general registers r15 (sp) value of the sta ck pointer in the vector address table sr bits i3 to i0 are 1111 (h'f), reserved bits are 0, and other bits are undefined gbr undefined control registers vbr h'00000000 system registers mach, macl, pr undefined pc value of the program counter in the vector address table 2. cpu rev.4.00 mar. 27, 2008 page 19 of 882 rej09b0108-0400 2.3 data formats 2.3.1 data format in registers register operands are always longwords (32 bits). if the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 0 lon g word figure 2.2 data format in registers 2.3.2 data formats in memory memory data formats are classified into bytes, words, and longwords. byte data can be accessed from any address. locate, however, word data at an address 2n, longword data at 4n. otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. in such cases, the data accessed cannot be guaranteed. the hardware stack area, poin ted by the hardware stack pointer (sp, r15), uses only longword data starting from address 4n because this area holds the program counter and status register. 31 0 15 23 7 byte byte byte byte word word address 2n address 4n lon g word address m address m + 2 address m + 1 address m + 3 figure 2.3 data formats in memory 2. cpu rev.4.00 mar. 27, 2008 page 20 of 882 rej09b0108-0400 2.3.3 immediate data format byte (8 bit) immediate data re sides in an instruction code. i mmediate data accessed by the mov, add, and cmp/eq instructions is sign-extended and handled in registers as longword data. immediate data accessed by the tst, and, or , and xor instructions is zero-extended and handled as longword data. consequently, and instructions with immediate data always clear the upper 24 bits of the destination register. word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. an immediate data transfer instruction (mov) acce sses the memory table using the pc relative addressing mo de with displacement. 2. cpu rev.4.00 mar. 27, 2008 page 21 of 882 rej09b0108-0400 2.4 instruction features 2.4.1 risc-type instruction set all instructions are risc type. this section details their functions. 16-bit fixed length : all instructions are 16 bits long , increasing program code efficiency. one instruction per state : the microcomputer can execute basic instructions in one state using the pipeline system. one stat e is 25 ns at 40 mhz. data length : longword is the standard data length for all operations. memory can be accessed in bytes, words, or longwords. by te or word data accessed from memory is sign-extended and handled as longword data. immediate data is sign-extended for arithmetic operations or zero- extended for logic operations. it also is handled as longword data. table 2.2 sign extension of word data cpu of this lsi description example of conventional cpu mov.w @(disp,pc),r1 add r1,r0 ......... .data.w h'1234 data is sign-extended to 32 bits, and r1 becomes h'00001234. it is next operated upon by an add instruction. add.w #h'1234,r0 note: @(disp, pc) accesses the immediate data. load-store architecture : basic operations are executed betw een registers. for operations that involve memory access, da ta is loaded to the registers an d executed (load-store architecture). instructions such as and that manipulate bi ts, however, are executed directly in memory. delayed branch instructions: unconditional branch instructions are delayed branch instructions. with a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. this reduces the disturbance of the pipeline control in case of branch instructions. there are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. 2. cpu rev.4.00 mar. 27, 2008 page 22 of 882 rej09b0108-0400 table 2.3 delayed branch instructions cpu of this lsi description example of conventional cpu bra trget add r1,r0 executes the add before branching to trget. add.w r1,r0 bra trget multiply/multiply-and-ac cumulate operations: 16-bit 16-bit 32-bit multiply operations are executed in one and two states. 16-bit 16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two and three states. 32-bit 32-bit 64-bit multiply and 32-bit 32- bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four states. t bit : the t bit in the status regist er changes according to the resu lt of the comparison. whether a conditional branch is taken or not taken depends upon the t bit condition (true/false). the number of instructions that change the t bit is kept to a minimum to improve the processing speed. table 2.4 t bit cpu of this lsi description example of conventional cpu cmp/ge r1,r0 bt trget0 bf trget1 t bit is set when r0 r1. the program branches to trget0 when r0 r1 and to trget1 when r0 < r1. cmp.w r1,r0 bge trget0 blt trget1 add # ? 1,r0 cmp/eq #0,r0 bt trget t bit is not changed by add. t bit is set when r0 = 0. the program branches if r0 = 0. sub.w #1,r0 beq trget immediate data : byte (8-bit) immediate data is located in an instruction code. word or longword immediate data is not located in instruction c odes but in a memory table. an immediate data transfer instruction (mov) accesses the memory tabl e using the pc relative addressing mode with displacement. 2. cpu rev.4.00 mar. 27, 2008 page 23 of 882 rej09b0108-0400 table 2.5 immediat e data accessing classification cpu of this lsi example of conventional cpu 8-bit immediate mov #h'12,r0 mov.b #h'12,r0 16-bit immediate mov.w @(disp,pc),r0 ................. .data.w h'1234 mov.w #h'1234,r0 32-bit immediate mov.l @(disp,pc),r0 ................. .data.l h'12345678 mov.l #h'12345678,r0 note: @(disp, pc) accesses the immediate data. absolute address : when data is accessed by absolute addre ss, the value in the absolute address is placed in the memory table in advance. that valu e is transferred to the register by loading the immediate data during the execution of the instru ction, and the data is accessed in the indirect register addressing mode. table 2.6 absolute address accessing classification cpu of this lsi example of conventional cpu absolute address mov.l @(disp,pc),r1 mov.b @r1,r0 .................. .data.l h'12345678 mov.b @h'12345678,r0 note: @(disp,pc) accesses the immediate data. 16-bit/32-bit displacement : when data is accessed by 16-b it or 32-bit displacement, the displacement value is placed in the memory table in advance. that value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect indexe d register addressing mode. 2. cpu rev.4.00 mar. 27, 2008 page 24 of 882 rej09b0108-0400 table 2.7 displacement accessing classification cpu of this lsi example of conventional cpu 16-bit displacement mov.w @(disp,pc),r0 mov.w @(r0,r1),r2 .................. .data.w h'1234 mov.w @(h'1234,r1),r2 note: @(disp,pc) accesses the immediate data. 2. cpu rev.4.00 mar. 27, 2008 page 25 of 882 rej09b0108-0400 2.4.2 addressing modes table 2.8 describes addressing modes and effective addr ess calculation. table 2.8 addressing modes and effective addresses addressing mode instruction format effective address calculation equation direct register addressing rn the effective address is register rn. (the operand is the contents of register rn.) ? indirect register addressing @rn the effective address is t he contents of register rn. rn rn rn post-increment indirect register addressing @rn+ the effective address is the contents of register rn. a constant is added to t he content of rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. rn rn 1/2/4 + rn + 1/2/4 rn (after the instruction executes) byte: rn + 1 rn word: rn + 2 rn longword: rn + 4 rn pre-decrement indirect register addressing @-rn the effective address is the value obtained by subtracting a constant from rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. rn 1/2/4 rn ? 1/2/4 ? rn ? 1/2/4 byte: rn ? 1 rn word: rn ? 2 rn longword: rn ? 4 rn (instruction is executed with rn after this calculation) 2. cpu rev.4.00 mar. 27, 2008 page 26 of 882 rej09b0108-0400 addressing mode instruction format effective address calculation equation indirect register addressing with displacement @(disp:4, rn) the effective address is the sum of rn and a 4-bit displacement (disp). the value of disp is zero- extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. rn rn + disp 1/2/4 + 1/2/4 disp (zero-extended) byte: rn + disp word: rn + disp 2 longword: rn + disp 4 indirect indexed register addressing @(r0, rn) the effective address is the sum of rn and r0. rn r0 rn + r0 + rn + r0 indirect gbr addressing with displacement @(disp:8, gbr) the effective address is the sum of gbr value and an 8-bit displacement (disp). the value of disp is zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. gbr 1/2/4 gbr + disp 1/2/4 + disp (zero-extended) byte: gbr + disp word: gbr + disp 2 longword: gbr + disp 4 indirect indexed gbr addressing @(r0, gbr) the effective address is the sum of gbr value and r0. gbr r0 gbr + r0 + gbr + r0 2. cpu rev.4.00 mar. 27, 2008 page 27 of 882 rej09b0108-0400 addressing mode instruction format effective address calculation equation indirect pc addressing with displacement @(disp:8, pc) the effective address is the sum of pc value and an 8-bit displacement (disp). the value of disp is zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. for a longword operation, the lowest two bits of the pc value are masked. pc h'fffffffc pc + disp 2 or pc & h'fffffffc + disp 4 + 2/4 & (for lon g word) disp (zero-extended) word: pc + disp 2 longword: pc & h'fffffffc + disp 4 pc relative addressing disp:8 the effective address is the sum of pc value and the value that is obtained by doubling the sign- extended 8-bit displacement (disp). pc 2 + disp (si g n-extended) pc + disp 2 pc + disp 2 disp:12 the effective address is the sum of pc value and the value that is obtained by doubling the sign- extended 12-bit displacement (disp). pc 2 + disp (si g n-extended) pc + disp 2 pc + disp 2 rn the effective address is t he sum of the register pc and rn. pc rn pc + rn + pc + rn 2. cpu rev.4.00 mar. 27, 2008 page 28 of 882 rej09b0108-0400 addressing mode instruction format effective address calculation equation immediate addressing #imm:8 the 8-bit immediate data (imm) for the tst, and, or, and xor instructions is zero-extended. ? #imm:8 the 8-bit immediate data (imm) for the mov, add, and cmp/eq instructions is sign-extended. ? #imm:8 the 8-bit immediate data (imm) for the trapa instruction is zero-extended and then quadrupled. ? 2. cpu rev.4.00 mar. 27, 2008 page 29 of 882 rej09b0108-0400 2.4.3 instruction format the instruction formats and the meaning of source and destination operand are described below. the meaning of the operand depends on the instru ction code. the symbols used are as follows: ? xxxx: instruction code ? mmmm: source register ? nnnn: destination register ? iiii: immediate data ? dddd: displacement table 2.9 instruction formats instruction formats source operand destination operand example 0 format xxxx xxxx xxxx xxxx 15 0 ? ? nop ? nnnn: direct register movt rn control register or system register nnnn: direct register sts mach,rn n format xxxx xxxx xxxx nnnn 15 0 control register or system register nnnn: indirect pre- decrement register stc.l sr,@-rn mmmm: direct register control register or system register ldc rm,sr m format xxxx mmmm xxxx xxxx 15 0 mmmm: indirect post-increment register control register or system register ldc.l @rm+,sr mmmm: indirect register ? jmp @rm mmmm: pc relative using rm ? braf rm 2. cpu rev.4.00 mar. 27, 2008 page 30 of 882 rej09b0108-0400 instruction formats source operand destination operand example mmmm: direct register nnnn: direct register add rm,rn mmmm: direct register nnnn: indirect register mov.l rm,@rn mmmm: indirect post-increment register (multiply- and-accumulate) nnnn * : indirect post-increment register (multiply- and-accumulate) mach, macl mac.w @rm+,@rn+ mmmm: indirect post-increment register nnnn: direct register mov.l @rm+,rn mmmm: direct register nnnn: indirect pre- decrement register mov.l rm,@-rn nm format nnnn xxxx xxxx 15 0 mmmm mmmm: direct register nnnn: indirect indexed register mov.l rm,@(r0,rn) md format xxxx dddd 15 0 mmmm xxxx mmmmdddd: indirect register with displacement r0 (direct register) mov.b @(disp,rn),r0 nd4 format xxxx xxxx dddd 15 0 nnnn r0 (direct register) nnnndddd: indirect register with displacement mov.b r0,@(disp,rn) mmmm: direct register nnnndddd: indirect register with displacement mov.l rm,@(disp,rn) nmd format nnnn xxxx dddd 15 0 mmmm mmmmdddd: indirect register with displacement nnnn: direct register mov.l @(disp,rm),rn 2. cpu rev.4.00 mar. 27, 2008 page 31 of 882 rej09b0108-0400 instruction formats source operand destination operand example dddddddd: indirect gbr with displacement r0 (direct register) mov.l @(disp,gbr),r0 r0 (direct register) dddddddd: indirect gbr with displacement mov.l r0,@(disp,gbr) dddddddd: pc relative with displacement r0 (direct register) mova @(disp,pc),r0 d format dddd xxxx 15 0 xxxx dddd ? dddddddd: pc relative bf label d12 format dddd xxxx 15 0 dddd dddd ? dddddddddddd: pc relative bra label (label = disp + pc) nd8 format dddd nnnn xxxx 15 0 dddd dddddddd: pc relative with displacement nnnn: direct register mov.l @(disp,pc),rn iiiiiiii: immediate indirect indexed gbr and.b #imm,@(r0,gbr) iiiiiiii: immediate r0 (direct register) and #imm,r0 i format xxxx xxxx i i i i 15 0 i i i i iiiiiiii: immediate ? trapa #imm ni format nnnn i i i i xxxx 15 0 i i i i iiiiiiii: immediate nnnn: direct register add #imm,rn note: in multiply-and-accu mulate instructions, nnnn is the source register. 2. cpu rev.4.00 mar. 27, 2008 page 32 of 882 rej09b0108-0400 2.5 instruction set 2.5.1 instruction set by classification table 2.10 lists the instructions according to their classification. table 2.10 classification of instructions classification types operation code function no. of instructions mov data transfer, immediate data transfer, peripheral module data transfer, structure data transfer mova effective address transfer movt t bit transfer swap swap of upper and lower bytes data transfer 5 xtrct extraction of the middl e of registers connected 39 21 add binary addition 33 addc binary addition with carry addv binary addition with overflow check cmp/cond comparison div1 division arithmetic operations div0s initialization of signed division div0u initialization of unsigned division dmuls signed double-length multiplication dmulu unsigned double-length multiplication dt decrement and test exts sign extension extu zero extension mac multiply-and-accumulate, double-length multiply-and-accumulate operation mul double-length multiply operation muls signed multiplication mulu unsigned multiplication neg negation negc negation with borrow sub binary subtraction 2. cpu rev.4.00 mar. 27, 2008 page 33 of 882 rej09b0108-0400 classification types operation code function no. of instructions subc binary subtraction with borrow 33 arithmetic operations subv binary subtraction with underflow 6 and logical and 14 not bit inversion or logical or tas memory test and bit set tst logical and and t bit set logic operations xor exclusive or shift 10 rotl one-bit left rotation 14 rotr one-bit right rotation rotcl one-bit left rotation with t bit rotcr one-bit right rotation with t bit shal one-bit arithmetic left shift shar one-bit arithmetic right shift shll one-bit logical left shift shlln n-bit logical left shift shlr one-bit logical right shift shlrn n-bit logical right shift branch 9 bf conditional bran ch, conditional branch with delay (branch when t = 0) 11 bt conditional branch, conditional branch with delay (branch when t = 1) bra unconditional branch braf unconditional branch bsr branch to subroutine procedure bsrf branch to subroutine procedure jmp unconditional branch jsr branch to subroutine procedure rts return from subroutine procedure 2. cpu rev.4.00 mar. 27, 2008 page 34 of 882 rej09b0108-0400 classification types operation code function no. of instructions 11 clrt t bit clear 31 system control clrmac mac register clear ldc load to control register lds load to system register nop no operation rte return from exception processing sett t bit set sleep transition to power-down mode stc store control register data sts store system register data trapa trap exception handling total: 62 142 2. cpu rev.4.00 mar. 27, 2008 page 35 of 882 rej09b0108-0400 the table below shows the format of instruction c odes, operation, and exec ution states. they are described by using this format according to their classification. ? instruction code format item format explanation instruction described in mnemonic. op.sz src,dest op: operation code sz: size src: source dest: destination rm: source register rn: destination register imm: immediate data disp: displacement * 2 instruction code described in msb ? lsb order mmmm: source register nnnn: destination register 0000: r0 0001: r1 ? ? ? 1111: r15 iiii: immediate data dddd: displacement , direction of transfer (xx) memory operand m/q/t flag bits in the sr & logical and of each bit | logical or of each bit ^ exclusive or of each bit ~ logical not of each bit < 2. cpu rev.4.00 mar. 27, 2008 page 36 of 882 rej09b0108-0400 ? data transfer instructions instruction instruction code operation execution states t bit mov #imm,rn 1110nnnniiiiiiii #imm sign extension rn 1 ? mov.w @(disp,pc),rn 1001nnnndddddddd (disp 2 + pc) sign extension rn 1 ? mov.l @(disp,pc),rn 1101nnnndddddddd (disp 4 + pc) rn 1 ? mov rm,rn 0110nnnnmmmm0011 rm rn 1 ? mov.b rm,@rn 0010nnnnmmmm0000 rm (rn) 1 ? mov.w rm,@rn 0010nnnnmmmm0001 rm (rn) 1 ? mov.l rm,@rn 0010nnnnmmmm0010 rm (rn) 1 ? mov.b @rm,rn 0110nnnnmmmm0000 (rm) sign extension rn 1 ? mov.w @rm,rn 0110nnnnmmmm0001 (rm) sign extension rn 1 ? mov.l @rm,rn 0110nnnnmmmm0010 (rm) rn 1 ? mov.b rm,@?rn 0010nnnnmmmm0100 rn?1 rn, rm (rn) 1 ? mov.w rm,@?rn 0010nnnnmmmm0101 rn?2 rn, rm (rn) 1 ? mov.l rm,@?rn 0010nnnnmmmm0110 rn?4 rn, rm (rn) 1 ? mov.b @rm+,rn 0110nnnnmmmm0100 (rm) sign extension rn,rm + 1 rm 1 ? mov.w @rm+,rn 0110nnnnmmmm0101 (rm) sign extension rn,rm + 2 rm 1 ? mov.l @rm+,rn 0110nnnnmmmm0110 (rm) rn,rm + 4 rm 1 ? mov.b r0,@(disp,rn) 10000000nnnndddd r0 (disp + rn) 1 ? mov.w r0,@(disp,rn) 10000001nnnndddd r0 (disp 2 + rn) 1 ? mov.l rm,@(disp,rn) 0001nnnnmmmmdddd rm (disp 4 + rn) 1 ? mov.b @(disp,rm),r0 10000100mmmmdddd (disp + rm) sign extension r0 1 ? mov.w @(disp,rm),r0 10000101mmmmdddd (disp 2 + rm) sign extension r0 1 ? mov.l @(disp,rm),rn 0101nnnnmmmmdddd (disp 4 + rm) rn 1 ? mov.b rm,@(r0,rn) 0000nnnnmmmm0100 rm (r0 + rn) 1 ? mov.w rm,@(r0,rn) 0000nnnnmmmm0101 rm (r0 + rn) 1 ? mov.l rm,@(r0,rn) 0000nnnnmmmm0110 rm (r0 + rn) 1 ? 2. cpu rev.4.00 mar. 27, 2008 page 37 of 882 rej09b0108-0400 instruction instruction code operation execution states t bit mov.b @(r0,rm),rn 0000nnnnmmmm1100 (r0 + rm) sign extension rn 1 ? mov.w @(r0,rm),rn 0000nnnnmmmm1101 (r0 + rm) sign extension rn 1 ? mov.l @(r0,rm),rn 0000nnnnmmmm1110 (r0 + rm) rn 1 ? mov.b r0,@(disp,gbr) 11000000dddddddd r0 (disp + gbr) 1 ? mov.w r0,@(disp,gbr) 11000001dddddddd r0 (disp 2 + gbr) 1 ? mov.l r0,@(disp,gbr) 11000010dddddddd r0 (disp 4 + gbr) 1 ? mov.b @(disp,gbr),r0 11000100dddddddd (disp + gbr) sign extension r0 1 ? mov.w @(disp,gbr),r0 11000101dddddddd (disp 2 + gbr) sign extension r0 1 ? mov.l @(disp,gbr),r0 11000110dddddddd (disp 4 + gbr) r0 1 ? mova @(disp,pc),r0 11000111dddddddd disp 4 + pc r0 1 ? movt rn 0000nnnn00101001 t rn 1 ? swap.b rm,rn 0110nnnnmmmm1000 rm swap bottom two bytes rn 1 ? swap.w rm,rn 0110nnnnmmmm1001 rm swap two consecutive words rn 1 ? xtrct rm,rn 0010nnnnmmmm1101 rm: middle 32 bits of rn rn 1 ? 2. cpu rev.4.00 mar. 27, 2008 page 38 of 882 rej09b0108-0400 ? arithmetic operation instructions instruction instruction code operation execution states t bit add rm,rn 0011nnnnmmmm1100 rn + rm rn 1 ? add #imm,rn 0111nnnniiiiiiii rn + imm rn 1 ? addc rm,rn 0011nnnnmmmm1110 rn + rm + t rn, carry t 1 carry addv rm,rn 0011nnnnmmmm1111 rn + rm rn, overflow t 1 overflow cmp/eq #imm,r0 10001000iiiiiiii if r0 = imm, 1 t 1 comparison result cmp/eq rm,rn 0011nnnnmmmm0000 if rn = rm, 1 t 1 comparison result cmp/hs rm,rn 0011nnnnmmmm0010 if rn rm with unsigned data, 1 t 1 comparison result cmp/ge rm,rn 0011nnnnmmmm0011 if rn rm with signed data, 1 t 1 comparison result cmp/hi rm,rn 0011nnnnmmmm0110 if rn > rm with unsigned data, 1 t 1 comparison result cmp/gt rm,rn 0011nnnnmmmm0111 if rn > rm with signed data, 1 t 1 comparison result cmp/pl rn 0100nnnn00010101 if rn > 0, 1 t 1 comparison result cmp/pz rn 0100nnnn00010001 if rn 0, 1 t 1 comparison result cmp/str rm,rn 0010nnnnmmmm1100 if rn and rm have an equivalent byte, 1 t 1 comparison result div1 rm,rn 0011nnnnmmmm0100 single-step division (rn rm) 1 calculation result div0s rm,rn 0010nnnnmmmm0111 msb of rn q, msb of rm m, m ^ q t 1 calculation result div0u 0000000000011001 0 m/q/t 1 0 dmuls.l rm,rn 0011nnnnmmmm1101 signed operation of rn rm mach, macl 32 32 64 bits 2 to 4 * ? dmulu.l rm,rn 0011nnnnmmmm0101 unsigned operation of rn rm mach, macl 32 32 64 bits 2 to 4 * ? 2. cpu rev.4.00 mar. 27, 2008 page 39 of 882 rej09b0108-0400 instruction instruction code operation execution states t bit dt rn 0100nnnn00010000 rn ? 1 rn, when rn is 0, 1 t. when rn is nonzero, 0 t 1 comparison result exts.b rm,rn 0110nnnnmmmm1110 byte in rm is sign- extended rn 1 ? exts.w rm,rn 0110nnnnmmmm1111 word in rm is sign- extended rn 1 ? extu.b rm,rn 0110nnnnmmmm1100 byte in rm is zero- extended rn 1 ? extu.w rm,rn 0110nnnnmmmm1101 word in rm is zero- extended rn 1 ? mac.l @rm+,@rn+ 0000nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 32 32 + 64 64 bits 3/(2 to 4) * ? mac.w @rm+,@rn+ 0100nnnnmmmm1111 signed operation of (rn) (rm) + mac mac 16 16 + 64 64 bits 3/(2) * ? mul.l rm,rn 0000nnnnmmmm0111 rn rm macl, 32 32 32 bits 2 to 4 * ? muls.w rm,rn 0010nnnnmmmm1111 signed operation of rn rm macl 16 16 32 bits 1 to 3 * ? mulu.w rm,rn 0010nnnnmmmm1110 unsigned operation of rn rm macl 16 16 32 bits 1 to 3 * ? neg rm,rn 0110nnnnmmmm1011 0 ? rm rn 1 ? negc rm,rn 0110nnnnmmmm1010 0 ? rm ? t rn, borrow t 1 borrow sub rm,rn 0011nnnnmmmm1000 rn ? rm rn 1 ? subc rm,rn 0011nnnnmmmm1010 rn ? rm ? t rn, borrow t 1 borrow subv rm,rn 0011nnnnmmmm1011 rn ? rm rn, underflow t 1 overflow note: * the normal number of execution states is shown. (the number in parentheses is the number of states when there is contention with the precedin g or following instructions.) 2. cpu rev.4.00 mar. 27, 2008 page 40 of 882 rej09b0108-0400 ? logic operation instructions instruction instruction code operation execution states t bit and rm,rn 0010nnnnmmmm1001 rn & rm rn 1 ? and #imm,r0 11001001iiiiiiii r0 & imm r0 1 ? and.b #imm,@(r0,gbr) 11001101iiiiiiii (r0 + gbr) & imm (r0 + gbr) 3 ? not rm,rn 0110nnnnmmmm0111 ~rm rn 1 ? or rm,rn 0010nnnnmmmm1011 rn | rm rn 1 ? or #imm,r0 11001011iiiiiiii r0 | imm r0 1 ? or.b #imm,@(r0,gbr) 11001111iiiiiiii (r0 + gbr) | imm (r0 + gbr) 3 ? tas.b @rn 0100nnnn00011011 if (rn) is 0, 1 t; 1 msb of (rn) 4 test result tst rm,rn 0010nnnnmmmm1000 rn & rm; if the result is 0, 1 t 1 test result tst #imm,r0 11001000iiiiiiii r0 & imm; if the result is 0, 1 t 1 test result tst.b #imm,@(r0,gbr) 11001100iiiiiiii (r0 + gbr) & imm; if the result is 0, 1 t 3 test result xor rm,rn 0010nnnnmmmm1010 rn ^ rm rn 1 ? xor #imm,r0 11001010iiiiiiii r0 ^ imm r0 1 ? xor.b #imm,@(r0,gbr) 11001110iiiiiiii (r0 + gbr) ^ imm (r0 + gbr) 3 ? 2. cpu rev.4.00 mar. 27, 2008 page 41 of 882 rej09b0108-0400 ? shift instructions instruction instruction code operation execution states t bit rotl rn 0100nnnn00000100 t rn msb 1 msb rotr rn 0100nnnn00000101 lsb rn t 1 lsb rotcl rn 0100nnnn00100100 t rn t 1 msb rotcr rn 0100nnnn00100101 t rn t 1 lsb shal rn 0100nnnn00100000 t rn 0 1 msb shar rn 0100nnnn00100001 msb rn t 1 lsb shll rn 0100nnnn00000000 t rn 0 1 msb shlr rn 0100nnnn00000001 0 rn t 1 lsb shll2 rn 0100nnnn00001000 rn<<2 rn 1 ? shlr2 rn 0100nnnn00001001 rn>>2 rn 1 ? shll8 rn 0100nnnn00011000 rn<<8 rn 1 ? shlr8 rn 0100nnnn00011001 rn>>8 rn 1 ? shll16 rn 0100nnnn00101000 rn<<16 rn 1 ? shlr16 rn 0100nnnn00101001 rn>>16 rn 1 ? 2. cpu rev.4.00 mar. 27, 2008 page 42 of 882 rej09b0108-0400 ? branch instructions instruction instruction code operation execution states t bit bf label 10001011dddddddd if t = 0, disp 2 + pc pc; if t = 1, nop 3/1 * ? bf/s label 10001111dddddddd delayed branch, if t = 0, disp 2 + pc pc; if t = 1, nop 2/1 * ? bt label 10001001dddddddd if t = 1, disp 2 + pc pc; if t = 0, nop 3/1 * ? bt/s label 10001101dddddddd delayed branch, if t = 1, disp 2 + pc pc; if t = 0, nop 2/1 * ? bra label 1010dddddddddddd delayed branch, disp 2 + pc pc 2 ? braf rm 0000mmmm00100011 delayed branch, rm + pc pc 2 ? bsr label 1011dddddddddddd delayed branch, pc pr, disp 2 + pc pc 2 ? bsrf rm 0000mmmm00000011 delayed branch, pc pr, rm + pc pc 2 ? jmp @rm 0100mmmm00101011 delayed branch, rm pc 2 ? jsr @rm 0100mmmm00001011 delayed branch, pc pr, rm pc 2 ? rts 0000000000001011 delayed branch, pr pc 2 ? note: * one state when the pr ogram does not branch. 2. cpu rev.4.00 mar. 27, 2008 page 43 of 882 rej09b0108-0400 ? system control instructions instruction instruction code operation execution states t bit clrt 0000000000001000 0 t 1 0 clrmac 0000000000101000 0 mach, macl 1 ? ldc rm,sr 0100mmmm00001110 rm sr 1 lsb ldc rm,gbr 0100mmmm00011110 rm gbr 1 ? ldc rm,vbr 0100mmmm00101110 rm vbr 1 ? ldc.l @rm+,sr 0100mmmm00000111 (rm) sr, rm + 4 rm 3 lsb ldc.l @rm+,gbr 0100mmmm00010111 (rm) gbr, rm + 4 rm 3 ? ldc.l @rm+,vbr 0100mmmm00100111 (rm) vbr, rm + 4 rm 3 ? lds rm,mach 0100mmmm00001010 rm mach 1 ? lds rm,macl 0100mmmm00011010 rm macl 1 ? lds rm,pr 0100mmmm00101010 rm pr 1 ? lds.l @rm+,mach 0100mmmm00000110 (rm) mach, rm + 4 rm 1 ? lds.l @rm+,macl 0100mmmm00010110 (rm) macl, rm + 4 rm 1 ? lds.l @rm+,pr 0100mmmm00100110 (rm) pr, rm + 4 rm 1 ? nop 0000000000001001 no operation 1 ? rte 0000000000101011 delayed branch, stack area pc/sr 4 ? sett 0000000000011000 1 t 1 1 sleep 0000000000011011 sleep 3 * ? stc sr,rn 0000nnnn00000010 sr rn 1 ? stc gbr,rn 0000nnnn00010010 gbr rn 1 ? stc vbr,rn 0000nnnn00100010 vbr rn 1 ? stc.l sr,@?rn 0100nnnn00000011 rn ? 4 rn, sr (rn) 2 ? stc.l gbr,@?rn 0100nnnn00010011 rn ? 4 rn, gbr (rn) 2 ? stc.l vbr,@?rn 0100nnnn00100011 rn ? 4 rn, br (rn) 2 ? sts mach,rn 0000nnnn00001010 mach rn 1 ? sts macl,rn 0000nnnn00011010 macl rn 1 ? sts pr,rn 0000nnnn00101010 pr rn 1 ? sts.l mach,@?rn 0100nnnn00000010 rn ? 4 rn, mach (rn) 1 ? sts.l macl,@?rn 0100nnnn00010010 rn ? 4 rn, macl (rn) 1 ? sts.l pr,@?rn 0100nnnn00100010 rn ? 4 rn, pr (rn) 1 ? 2. cpu rev.4.00 mar. 27, 2008 page 44 of 882 rej09b0108-0400 instruction instruction code operation execution states t bit trapa #imm 11000011iiiiiiii pc/sr stack area, (imm 4 + vbr) pc 8 ? note: * the number of execution st ates before the chip enter s sleep mode: the execution states shown in the table are minimums. the actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) equals to the register used by the next instruction. 2. cpu rev.4.00 mar. 27, 2008 page 45 of 882 rej09b0108-0400 2.6 processing states 2.6.1 state transitions the cpu has five processing states: reset, excep tion processing, bus release, program execution and power-down. figure 2.4 shows the transitions between the states. from any state when res = 0 from any state when res = 1, mres = 0, res = 0 power-on reset state manual reset state pro g ram execution state bus release state sleep mode software standby mode exception processin g state exception processin g source occurs exception processin g ends bus request g enerated bus request cleared ssby bit set for sleep instruction nmi or irq interrupt source occurs power-down state res = 1 res = 1, mres = 1 ssby bit cleared for sleep instruction reset state bus request cleared bus request cleared bus request g enerated bus request g enerated when an internal power-on reset by wdt or internal manual reset by wdt occurs interrupt sources g enerated or dmac/dtc address error occurs * note: * enabled only in masked rom version and rom less version. disabled in f-ztat version and emulator. figure 2.4 transitions between processing states 2. cpu rev.4.00 mar. 27, 2008 page 46 of 882 rej09b0108-0400 reset state: the cpu resets in the reset state. when the res pin level goes low, the power-on reset state is entered. when the res pin is high and the mres pin is low, the manual reset state is entered. exception processing state: the exception processing state is a transient state that occurs when exception processing sour ces such as resets or interrupts al ter the cpu?s processing state flow. for a reset, the initial values of the program counter (pc) (execu tion start address) and stack pointer (sp) are fetched from the exception pro cessing vector table and stored; the cpu then branches to the execution start addres s and execution of the program begins. for an interrupt, the stack pointer (sp) is acc essed and the program counter (pc) and status register (sr) are saved to the stack area. the ex ception service routine st art address is fetched from the exception processing vector table; the cpu then branches to that address and the program starts executing, thereby enteri ng the program execution state. program execution state: in the program execution state, the cpu sequentially executes the program. power-down state: in the power-down state, the cpu operation halts and power consumption declines. the sleep instru ction places the cpu in the sleep mo de or the software standby mode. bus release state: in the bus release state, the cpu releas es bus mastership to the device that has requested them. 3. mcu operating modes rev.4.00 mar. 27, 2008 page 47 of 882 rej09b0108-0400 section 3 mcu operating modes 3.1 selection of operating modes this lsi has four operating modes and four clock modes. the operating mode is determined by the setting of md3 to md0, and fwp pins. do not set these pins in the other way than the combination shown in table 3.1. when power is applied to the system, be sure to conduct power- on reset. table 3.1 selection of operating modes pin setting bus width of cs0, cs4 area mode no. fwp md3 * 1 md2 * 1 md1 md0 mode name on-chip rom sh7144 sh7145 mode 0 1 x x 0 0 mcu extension mode 0 not active 8 bits 16 bits mode 1 1 x x 0 1 mcu extension mode 1 not active 16 bits 32 bits mode 2 1 x x 1 0 mcu extension mode 2 active set by bcr1 of bsc mode 3 1 x x 1 1 single chip mode active ? * 2 0 x x 0 0 set by bcr1 of bsc * 2 0 x x 0 1 boot mode * 2 active ? * 2 0 x x 1 0 set by bcr1 of bsc * 2 0 x x 1 1 user programming mode * 2 active ? [legend] x: don?t care notes: 1. md3 and md2 pins are used to select clock mode. 2. user programming mode for flash memory. supported in only f-ztat version. there are two modes as the mcu operating modes: mcu extension mode and single chip mode. there are two modes to program the flash memory (on-board programming mode): boot mode and user programming mode. 3. mcu operating modes rev.4.00 mar. 27, 2008 page 48 of 882 rej09b0108-0400 the clock mode is selected by the input of md2 and md3 pins. table 3.2 clock mode setting pin setting clock ratio (when input clock is 1) clock mode no. md3 md2 system clock ( ) peripheral clock (p ) system clock output (ck) 0 0 0 1 1 1 1 0 1 2 2 2 2 1 0 4 4 * 4 3 1 1 4 2 4 note: * the maximum clock input frequency is 10mhz because the p is specified as 40mhz or less. 3. mcu operating modes rev.4.00 mar. 27, 2008 page 49 of 882 rej09b0108-0400 3.2 input/output pins table 3.3 describes the configuratio n of operating mode related pin. table 3.3 pin configuration pin name input/output function md0 input designates operating mode through the level applied to this pin md1 input designates operating mode through the level applied to this pin md2 input designates clock mode through the level applied to this pin md3 input designates clock mode through the level applied to this pin fwp input pin for the hardware protec tion against programming/erasing the on-chip flash memory 3. mcu operating modes rev.4.00 mar. 27, 2008 page 50 of 882 rej09b0108-0400 3.3 operating modes 3.3.1 mode 0 (mcu extension mode 0) cs0 space and cs4 space become external memory sp aces with 8-bit bus width in sh7144 or 16- bit bus width in sh7145. 3.3.2 mode 1 (mcu extension mode 1) cs0 space and cs4 space become external memory spaces with 16-bit bus width in sh7144 or 32-bit bus width in sh7145. 3.3.3 mode 2 (mcu extension mode 2) the on-chip rom is active and cs0 space can be used in this mode. 3.3.4 mode 3 (single chip mode) all ports can be used in this mode, however the external address cannot be used. 3.3.5 clock mode the input waveform frequency can be used as is, doubled or quadrupled as system clock frequency in mode 0 to mode 3. 3. mcu operating modes rev.4.00 mar. 27, 2008 page 51 of 882 rej09b0108-0400 3.4 address map the address map for the operating modes are shown in figure 3.1. h'00000000 h'ffff7fff h'ffff8000 h'003fffff h'007fffff h'00400000 h'00800000 h'00bfffff h'00c00000 h'00ffffff h'01000000 h'013fffff h'01400000 h'017fffff h'01800000 h'01bfffff h'01c00000 h'01ffffff h'02000000 h'ffffbfff h'ffffc000 cs4 space * cs5 space * cs6 space * cs7 space * cs4 space * cs5 space * cs6 space * cs7 space * cs4 space to cs7 space are available only in the masked rom version and rom less version. these spaces are reserved in the flash memory version and emulator. h'ffffffff h'ffffdfff h'ffffe000 h'00000000 h'00200000 h'ffff7fff h'ffff8000 h'003fffff h'0003ffff h'007fffff h'00400000 h'00040000 h'00040000 h'00800000 h'00bfffff h'00c00000 h'00ffffff h'01000000 h'011fffff h'01200000 h'013fffff h'01400000 h'017fffff h'01800000 h'01bfffff h'01c00000 h'01ffffff h'02000000 h'ffffbfff h'ffffc000 h'ffffffff h'ffffdfff h'ffffe000 h'ffff7fff h'ffff8000 h'ffffbfff h'ffffc000 h'ffffffff h'ffffdfff h'ffffe000 h'00000000 h'0003ffff on-chip rom (256 kbytes) on-chip rom (256 kbytes) modes 0 and 1 on-chip rom disabled mode mode 2 on-chip rom enabled mode mode 3 sin g le-chip mode on-chip ram (8 kbytes ) on-chip ram (8 kbytes ) on-chip ram (8 kbytes ) reserved area reserved area reserved area reserved area reserved area reserved area reserved area reserved area cs0 space cs0 space cs1 space cs2 space cs3 space cs1 space cs2 space cs3 space on-chip peripheral i/o re g isters on-chip peripheral i/o re g isters on-chip peripheral i/o re g isters note: * figure 3.1 address map for each operating mode 3. mcu operating modes rev.4.00 mar. 27, 2008 page 52 of 882 rej09b0108-0400 3.5 initial state in this lsi in the initial state of this lsi, some of on-chi p modules are set in module standby state for saving power. when operating these mo dules, clear module stan dby state according to the procedure in section 24, power-down modes. 3.6 note on changing operating mode when changing operating mode while power is applie d to this lsi, make sure to do it in the power-on reset state (that is, the low level is applied to the res pin). in addition, when changing clock mode, secure the reset oscillation stabilization time (t osc1 ) after clock mode change. when chan g in g other than clock mode see section 26.3.3, control si g nal timin g . see section 26.3.2, clock timin g . 1. 2. notes: t mds * 1 ck md3 to md0 res t osc1 * 2 when chan g in g clock mode figure 3.2 reset input timing when changing operating mode 4. clock pulse generator cpg0111a_010120030800 rev.4.00 mar. 27, 2008 page 53 of 882 rej09b0108-0400 section 4 clock pulse generator this lsi has an on-chip clock pulse generator (cpg) that generates the system clock ( ) and the peripheral clock (p ), and then makes internal clock ( /2 to /8192 and p /2 to p /1024) out of this generated clock. the cpg consists of an oscillator, pll circuit, and pre-scaler. a block diagram of the clock pulse generator is shown in figure 4.1. the frequency from the oscillator can be modified by the pll circuit. pllcap extal xtal md2 md3 pre-scaler pre-scaler oscillator for internal circuit pll circuit clock divider ( 1/2) clock mode control circuitry /2 to /8192 p /2 to p /1024 ck p figure 4.1 block diagram of clock pulse generator 4. clock pulse generator rev.4.00 mar. 27, 2008 page 54 of 882 rej09b0108-0400 table 4.1 shows the operating clock for each module. table 4.1 operating clock for each module operating clock operating module system clock ( ) cpu ubc dtc bsc dmac wdt aud rom ram peripheral clock (p ) mtu poe sci i 2 c a/d cmt h-udi 4. clock pulse generator rev.4.00 mar. 27, 2008 page 55 of 882 rej09b0108-0400 4.1 oscillator clock pulses can be supplied from a connected crystal resonator or an external clock. 4.1.1 connecting crystal resonator a crystal resonator can be connected as shown in figure 4.2. use the damping resistance (rd) listed in table 4.2. use an crystal resonator that has a resonance frequency of 4 to 12.5 mhz. it is recommended to consult the crystal resonator manu facturer concerning th e compatibility of the crystal resonator and the lsi. extal xtal r d c l2 c l1 c l1 = c l2 = 18?22 pf (recommended value) figure 4.2 connection of crystal resonator (example) table 4.2 damping resistance values (recommended values) frequency (mhz) 4 8 10 12.5 rd ( ) 500 200 0 0 figure 4.3 shows an equivalent circuit of the crystal resonator. use a crystal resonator with the characteristics listed in table 4.3. xtal c l extal c 0 l r s figure 4.3 crystal resonator equivalent circuit 4. clock pulse generator rev.4.00 mar. 27, 2008 page 56 of 882 rej09b0108-0400 table 4.3 crystal resonator characteristics frequency (mhz) 4 8 10 12.5 rs max ( ) 120 80 60 50 c 0 max (pf) 7 7 7 7 4.1.2 external clock input method figure 4.4 shows an example of an external clock input connection. in this case, make the external clock high level to stop it when in software st andby mode. during opera tion, make the external input clock frequency 4 to 12.5 mhz. when leaving the xtal pin open, make sure the parasitic capacitance is less than 10 pf. even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing software standby mode, in order to ensure the pll stabilization time. extal xtal external clock input open state figure 4.4 example of external clock connection 4. clock pulse generator rev.4.00 mar. 27, 2008 page 57 of 882 rej09b0108-0400 4.2 function for detect ing oscillator halt this cpg can detect a clock halt and automati cally cause the timer pins to become high- impedance when any system abnormality causes the oscillator to halt. that is, when a change of extal has not been detected, the high-current 6 pins (pe9/tioc3b/sck3/ trst *, pe11/tioc3d/rxd3/tdo*, pe12/tioc4a/txd3/tck*, pe13/tioc4b/ mres , pe14/tioc4c/dack0, pe15/tioc4d/dack1/ irqout ) can be set to high-impedance regardless of pfc setting. refer to section 17. 1.11, high-current port control register (ppcr), for more details. even in software standby mode, these 6 pins can be set to high-impedance regardless of pfc setting. refer to section 17.1.11, high-current port control register (ppcr), for more details. these pins enter the normal state after software standby mode is released. when abnormalities that halt the oscillator occur except in software standby mode, other lsi operations become undefined. in this case, lsi operations, including these 6 pins, become undefined even when the oscillator operation starts again. in the case of using e10a, the high-impedance function is disabled when an oscillation stop is detected, or when in software standby st ate for the three pins of pe9/tioc3b/sck3/ trst , pe11/tioc3d/rxd3/tdo, and pe12/tioc4a/txd3/tck of the sh7145. note: * only in the sh7145. 4. clock pulse generator rev.4.00 mar. 27, 2008 page 58 of 882 rej09b0108-0400 4.3 usage notes 4.3.1 note on crystal resonator a sufficient evaluation at the user?s site is necessary to use the lsi, by referring the resonator connection examples shown in this section, because various charact eristics related to the crystal resonator are closely linked to the user?s board design. as the oscillator circuit's circuit constant will depend on the resonator and the floating capacitance of the mounting circuit, the value of each external circuit?s component should be determined in consultation with the resonator manufacturer. the design must en sure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 4.3.2 notes on board design measures against radiation noise are taken in this lsi. if further reduction in radiation noise is needed, it is recommended to use a multiple layer board and provide a layer exclusive to the system ground. when using a crystal resonator, place the crystal resonator and its load ca pacitors as close as possible to the xtal and extal pins. do not route any signal lines near the oscillator circuitry as shown in figure 4.5. otherwise, correct oscillation can be interfered by induction. c l2 si g nal a si g nal b this lsi c l1 xtal extal avoid figure 4.5 cautions for oscillator circuit board design 4. clock pulse generator rev.4.00 mar. 27, 2008 page 59 of 882 rej09b0108-0400 a circuitry shown in figure 4.6 is recommended as an external circuitry around the pll. place oscillation stabilization capacitor c1 close to th e pllcap pin, and ensure that no other signal lines cross this line. separate the pll power lin es (pllvcc, pllvss) and the system power lines (vcc, vss) at the board power supply source, and be sure to insert bypass capacitors cb and cpb close to the pins. pllcap pllv cc pllv ss v cc v ss c1: 470 pf cpb = 0.1 f * cb = 0.1 f * (values are recommended values.) note: * cb and cpb are laminated ceramic type. rp=200 r1=3k figure 4.6 recommended ex ternal circuitry around pll in principle, electromagnetic waves are emitted fr om an lsi in operation. this lsi regards the lower of the system clock ( ) and the peripheral clock (p ) as fundamental (for example, if = 40 mhz and p = 40 mhz, then 40 mhz), and the peak of electromagnetic waves is in the high frequency band. when this lsi is used adjacent to apparatuses sensible to electromagnetic waves such as fm/vhf band receivers, it is recommended to use a board with at least four layers and provide a layer exclusive to the system ground. 4. clock pulse generator rev.4.00 mar. 27, 2008 page 60 of 882 rej09b0108-0400 5. exception processing rev.4.00 mar. 27, 2008 page 61 of 882 rej09b0108-0400 section 5 exception processing 5.1 overview 5.1.1 types of exception processing and priority exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. when several exception processing sources occur at once, they are processed according to the priority. table 5.1 types of exception pr ocessing and priority order exception source priority reset power-on reset high manual reset cpu address error or aud address error * 1 address error dmac/dtc address error interrupt nmi user break h-udi irq on-chip peripheral modules: ? direct memory access controller (dmac) ? multifunction timer unit (mtu) ? serial communication interface 0 and 1(sci0 and sci1) ? a/d converter 0 and 1 (a/d0, a/d1) ? data transfer controller (dtc) ? compare match timer 0 and 1 (cmt0, cmt1) ? watchdog timer (wdt) ? input/output port (i/o) (mtu) ? serial communication interface 2 and 3 (sci2 and sci3) ? iic bus interface (iic) instructions trap instruct ion (trapa instruction) general illegal instructions (undefined code) illegal slot instructions (undefined code placed directly after a delayed branch instruction * 2 or instructions that rewrite the pc * 3 ) low notes: 1. only in the f-ztat version. 2. delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, and braf. 5. exception processing rev.4.00 mar. 27, 2008 page 62 of 882 rej09b0108-0400 3. instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, and braf. 5.1.2 exception processing operations the exception processing sources are detected and begin processing according to the timing shown in table 5.2. table 5.2 timing for exception source det ection and start of exception processing exception source timing of source de tection and start of processing power-on reset starts when the res pin changes from low to high or when wdt overflows. reset manual reset starts when the mres pin changes from low to high. address error interrupts detected when instruction is decoded and starts when the execution of the previous instruction is completed. instructions trap instructio n starts from the executio n of a trapa instruction. general illegal instructions starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). illegal slot instructions starts from the decoding of u ndefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the pc. when exception processing starts , the cpu operates as follows: 1. exception processing triggered by reset: the initial values of the program counter (pc) and stack pointer (sp) are fetched from the exception processing vector table (pc and sp are respectively the h'00000000 and h'00000004 addresses for power-on resets and the h'00000008 and h'0000000c addresses for manual resets). see section 5.1.3, exception pr ocessing vector table, for more information. h'00000000 is then written to the vector base register (vbr), and h'f (b'1111) is written to the interrupt mask bits (i3 to i0) of the status register (sr). the program begins running from the pc address fetched from the ex ception processing vector table. 2. exception processing triggered by addr ess errors, interrupts and instructions: sr and pc are saved to the stack indicated by r15. for interrupt exception processing, the interrupt priority level is written to the sr?s in terrupt mask bits (i3 to i0). for address error and instruction exception processing, the i3 to i0 bits are not affected. th e start address is then fetched from the exception processing vector table and the program begins running from that address. 5. exception processing rev.4.00 mar. 27, 2008 page 63 of 882 rej09b0108-0400 5.1.3 exception processing vector table before exception processing begins running, the exception processing vector table must be set in memory. the exception processing vector table st ores the start addresses of exception service routines. (the reset exception processing table holds the initial values of pc and sp.) all exception sources are given different vector numbers and vector tabl e address offsets. the vector table addresses are calculated from these v ector numbers and vector table address offsets. during exception processing, the start addresses of the exception service r outines are fetched from the exception processing vector table that is indicated by this vector table address. table 5.3 shows the vector numbers and vector table address offsets. table 5.4 shows how vector table addresses are calculated. table 5.3 exception processing vector table exception sources vector numbers vector table address offset power-on reset pc 0 h'00000000 to h'00000003 sp 1 h'00000004 to h'00000007 manual reset pc 2 h'00000008 to h'0000000b sp 3 h'0000000c to h'0000000f general illegal instructio n 4 h'00000010 to h'00000013 (reserved by system) 5 h'00000014 to h'00000017 slot illegal instruction 6 h'00000018 to h'0000001b (reserved by system) 7 h'0000001c to h'0000001f 8 h'00000020 to h'00000023 cpu address error or aud address error * 1 9 h'00000024 to h'00000027 dmac/dtc address error 10 h'00000028 to h'0000002b interrupts nmi 11 h'0000002c to h'0000002f user break 12 h'00000030 to h'00000033 (reserved by system) 13 h'00000034 to h'00000037 h-udi 14 h'00000038 to h'0000003b (reserved by system) 15 : 31 h'0000003c to h'0000003f : h'0000007c to h'0000007f 5. exception processing rev.4.00 mar. 27, 2008 page 64 of 882 rej09b0108-0400 exception sources vector numbers vector table address offset trap instruction (user vector) 32 : 63 h'00000080 to h'00000083 : h'000000fc to h'000000ff interrupts irq0 64 h'00000100 to h'00000103 irq1 65 h'00000104 to h'00000107 irq2 66 h'00000108 to h'0000010b irq3 67 h'0000010c to h'0000010f irq4 68 h'00000110 to h'00000113 irq5 69 h'00000114 to h'00000117 irq6 70 h'00000118 to h'0000011b irq7 71 h'0000011c to h'0000011f on-chip peripheral module * 2 72 : 255 h'00000120 to h'00000123 : h'000003fc to h'000003ff notes: 1. only in the f-ztat version. 2. the vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in table 6.2. table 5.4 calculating exception processing vector table addresses exception source vector table address calculation resets vector table address = (vector table address offset) = (vector number) 4 address errors, interrupts, instructions vector table address = vbr + (vector table address offset) = vbr + (vector number) 4 notes: 1. vbr: vector base register 2. vector table address offset: see table 5.3. 3. vector number: see table 5.3. 5. exception processing rev.4.00 mar. 27, 2008 page 65 of 882 rej09b0108-0400 5.2 resets 5.2.1 types of reset resets have the highest priority of any exception source. there are two types of resets: manual resets and power-on resets. as table 5.5 shows, both types of resets initialize the internal status of the cpu. in power-on resets, all registers of th e on-chip peripheral modu les are initialized; in manual resets, they are not. table 5.5 reset status conditions for transition to reset status internal status type res wdt overflow mres cpu/intc on-chip peripheral module poe, pfc, io port low ? ? initialized initialized initialized power-on reset high overflow high initialized initialized not initialized manual reset high ? low initialized not initialized not initialized 5.2.2 power-on reset power-on reset by res pin: when the res pin is driven low, the lsi becomes to be a power- on reset state. to reliably reset the lsi, the res pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in software standby mode (when the clock circuit is halted) or at least 25 t cyc when the clock circuit is running. during power-on reset, cpu internal status and all registers of on-chip pe ripheral modules are initi alized. see appendix a, pin states, for the status of individual pins during the power-on reset status. in the power-on reset status, power-on re set exception processing starts when the res pin is first driven low for a set period of time and then re turned to high. the cpu will then operate as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception processing vector table. 2. the initial value of the stack pointer (sp) is fe tched from the exception pr ocessing vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3 to i0) of the status register (sr) are set to h'f (b'1111). 5. exception processing rev.4.00 mar. 27, 2008 page 66 of 882 rej09b0108-0400 4. the values fetched from the exception processi ng vector table are set in pc and sp, then the program begins executing. be certain to always perform power-on reset processing when turning the system power on. power-on reset by wdt: when a setting is made for a power-on reset to be generated in the wdt?s watchdog timer mode, and the wdt?s tcnt overflows, the lsi becomes to be a power- on reset state. the poe (port output enable) function registers in the mtu, the pin function controller (pfc) registers, and i/o port registers are not initialized by the reset signal generated by the wdt (these registers are only initialized by a power-on reset from outside of the chip). if reset caused by the input signal at the res pin and a reset caused by wdt overflow occur simultaneously, the res pin reset has priority, and the wovf bit in rstcsr is cleared to 0. when wdt-initiated power-on reset processing is started, the cpu operates as follows: 1. the initial value (execution start address) of the program counter (pc) is fetched from the exception processing vector table. 2. the initial value of the stack pointer (sp) is fe tched from the exception pr ocessing vector table. 3. the vector base register (vbr) is cleared to h'00000000 and the interrupt mask bits (i3-i0) of the status register (sr) are set to h'f (b'1111). 4. the values fetched from the exception processi ng vector table are set in the pc and sp, then the program begins executing. 5.2.3 manual reset when the res pin is high and the mres pin is driven low, the lsi becomes to be a manual reset state. to reliably reset the lsi, the mres pin should be kept at low for at least the duration of the oscillation settling time that is set in wdt when in software standby mode (when the clock is halted) or at least 25 t cyc when the clock is operating. during manual reset, the cpu internal status is initialized. registers of on-chip peripheral modules are not initialized. when the lsi enters manual reset status in the middle of a bus cycle, manual reset exception pr ocessing does not start until the bus cycle has ended. thus, manual resets do not abort bus cycles. however, once mres is driven low, hold the low level until the cpu becomes to be a manual reset mode after the bus cycle ends. (keep at low level fo r at least the longest bus cycle) . see appendix a, pin states, for the status of individual pins during manual reset mode. in the manual reset status, manual reset exception processing starts when the mres pin is first kept low for a set period of time and then returned to high. the cpu will th en operate in the same procedures as described for power-on resets. 5. exception processing rev.4.00 mar. 27, 2008 page 67 of 882 rej09b0108-0400 5.3 address errors 5.3.1 cause of add ress error exception address errors occur when instructions are fetched or data read or written, as shown in table 5.6. table 5.6 bus cycles and address errors bus cycle type bus master bus cycl e description address errors cpu instruction fetched from even address none (normal) instruction fetched from odd address address error occurs instruction fetched from other than on-chip peripheral module space * none (normal) instruction fetched from on-chip peripheral module space * address error occurs instruction fetch instruction fetched from external memory space when in single chip mode address error occurs word data accessed from even address none (normal) word data accessed from odd address address error occurs data read/write cpu, dmac, aud, or dtc longword data accessed from a longword boundary none (normal) longword data accessed from other than a long-word boundary address error occurs byte or word data accessed in on-chip peripheral module space * none (normal) longword data accessed in 16-bit on-chip peripheral module space * none (normal) longword data accessed in 8-bit on-chip peripheral module space * address error occurs external memory space accessed when in single chip mode address error occurs note: * see section 9, bus state controller (bsc ), for more information on the on-chip peripheral module space. 5. exception processing rev.4.00 mar. 27, 2008 page 68 of 882 rej09b0108-0400 5.3.2 address error exception processing when an address error occurs, the bus cycle in wh ich the address error occu rred ends, the current instruction finishes, and then address error ex ception processing starts. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the last executed instruction. 3. the start address of the exception service rou tine is fetched from the exception processing vector table that corres ponds to the occurred ad dress error, and the pr ogram starts executing from that address. the jump in this case is not a delayed branch. 5. exception processing rev.4.00 mar. 27, 2008 page 69 of 882 rej09b0108-0400 5.4 interrupts 5.4.1 interrupt sources table 5.7 shows the sources that start the interrupt exception pr ocessing. they are nmi, user breaks, h-udi, irq, and on-chip peripheral modules. table 5.7 interrupt sources type request source number of sources nmi nmi pin (external input) 1 user break user break controller (ubc) 1 h-udi user debugging interface (h-udi) 1 irq irq0 to irq7 pins (external input) 8 on-chip peripheral module direc t memory access controller (dmac) 4 multifunction timer unit (mtu) 23 data transfer controller (dtc) 1 compare match timer (cmt) 2 a/d converter (a/d0 and a/d1) 2 serial communication interface (sci0 ? sci3) 16 watchdog timer (wdt) 1 input/output port 1 iic bus interface (iic) 1 each interrupt source is allocated a different vect or number and vector ta ble offset. see table 6.2 for more information on vector number s and vector table address offsets. 5. exception processing rev.4.00 mar. 27, 2008 page 70 of 882 rej09b0108-0400 5.4.2 interrupt priority level the interrupt priority order is predetermined. when multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (intc) determines their relative priorities and starts the exception processi ng according to the results. the priority order of interrupts is expressed as prio rity levels 0 to 16, with priority 0 the lowest and priority 16 the highest. the nmi interrupt has priority 16 and cannot be masked, so it is always accepted. the priority leve l of user break interrupt and h-udi is 15. irq interrupts and on-chip peripheral module interrupt priority levels can be set freely using the intc?s interrupt priority registers a to j (ipra to iprj) as shown in table 5.8. the priority levels that can be set are 0 to 15. level 16 cannot be set. see section 6. 3.4, interrupt priority re gisters a to j (ipra to iprj), for more information on ipra to iprj. table 5.8 interrupt priority type priority level comment nmi 16 fixed priority level. cannot be masked. user break 15 fixed priority level. h-udi 15 fixed priority level. irq on-chip peripheral module 0 to 15 set with interrupt priority registers a to j (ipra to iprj). 5.4.3 interrupt exce ption processing when an interrupt occurs, the interrupt controlle r (intc) ascertains its priority level. nmi is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (i3 to i0) of the status register (sr). when an interrupt is accepted, ex ception processing begins. in in terrupt exception processing, the cpu saves sr and the program counter (pc) to th e stack. the priority level value of the accepted interrupt is written to sr bits i3 to i0. for nmi, however, the priority level is 16, but the value set in i3 to i0 is h'f (level 15). next, the start addr ess of the exception service routine is fetched from the exception proces sing vector table for the accepted interr upt, that address is jumped to and execution begins. see section 6.6, operation, for more information on the interrupt exception processing. 5. exception processing rev.4.00 mar. 27, 2008 page 71 of 882 rej09b0108-0400 5.5 exceptions triggered by instructions 5.5.1 types of exceptions triggered by instructions exception processing can be triggered by trap in struction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. table 5.9 types of exceptions triggered by instructions type source instruction comment trap instruction trapa ? illegal slot instructions undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that rewrite the pc delayed branch instructions: jmp, jsr, bra, bsr, rts, rte, bf/s, bt/s, bsrf, braf instructions that rewrite the pc: jmp, jsr, bra, bsr, rts, rte, bt, bf, trapa, bf/s, bt/s, bsrf, braf general illegal instructions undefined code anywhere besides in a delay slot ? 5.5.2 trap instructions when a trapa instruction is executed, trap in struction exception processing starts. the cpu operates as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the start address of the instruction to be executed after the trapa instruction. 3. the start address of the exception service rou tine is fetched from the exception processing vector table that corres ponds to the vector numb er specified in the tr apa instruction. that address is jumped to and the pr ogram starts executing. the jump in this case is not a delayed branch. 5. exception processing rev.4.00 mar. 27, 2008 page 72 of 882 rej09b0108-0400 5.5.3 illegal slot instructions an instruction placed imme diately after a delayed branch instru ction is called ?instruction placed in a delay slot?. when the instruction placed in th e delay slot is an unde fined code, illegal slot exception processing starts after the undefined code is decoded. illegal sl ot exception processing also starts when an instruction that rewrites the program counter (p c) is placed in a delay slot and the instruction is decoded. the cpu handles an illegal slot instruction as follows: 1. the status register (sr) is saved to the stack. 2. the program counter (pc) is saved to the stack. the pc value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the pc. 3. the start address of the exception service rou tine is fetched from the exception processing vector table that corres ponds to the exception that occurred. that address is jumped to and the program starts executing. the jump in this case is not a delayed branch. 5.5.4 general illegal instructions when undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general ille gal instruction exception processing starts. the cpu handles the general illegal instructions in the same procedures as in the illegal slot instructions. unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. 5. exception processing rev.4.00 mar. 27, 2008 page 73 of 882 rej09b0108-0400 5.6 cases when exception sources are not accepted when an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction, it is sometimes no t accepted immediately but stored instead, as shown in table 5.10. in this case, it will be ac cepted when an instruction that can accept the exception is decoded. table 5.10 generation of excep tion sources immediately aft er delayed branch instruction or interrupt-disabled instruction exception source point of occurrence address error interrupt immediately after a delayed branch instruction * 1 not accepted not accepted immediately after an interrupt-disabled instruction * 2 accepted not accepted notes: 1. delayed branch instructions: jmp, js r, bra, bsr, rts, rte, bf/s, bt/s, bsrf, and braf 2. interrupt-disabled instructions: ldc, ldc. l, stc, stc.l, lds, lds.l, sts, and sts.l 5.6.1 immediately after de layed branch instruction when an instruction placed immediat ely after a delayed branch instru ction (delay slot) is decoded, neither address errors nor interrupts are accept ed. the delayed branch instruction and the instruction placed immedi ately after it (delay slot) are alwa ys executed consecutively, so no exception processing occurs during this period. 5.6.2 immediately after int errupt-disabled instruction when an instruction placed imme diately after an interrupt-disab led instruction is decoded, interrupts are not accep ted. address errors can be accepted. 5. exception processing rev.4.00 mar. 27, 2008 page 74 of 882 rej09b0108-0400 5.7 stack status after exception processing ends the status of the stack after exception processing ends is shown in table 5.11. table 5.11 stack st atus after exception processing ends types stack status address error 32 bits 32 bits sr address of instruction after executed instruction sp trap instruction 32 bits 32 bits sr address of instruction after trapa instruction sp general illegal instruction 32 bits 32 bits sr address of instruction after g eneral ille g al instruction sp interrupt 32 bits 32 bits sr address of instruction after executed instruction sp illegal slot instruction 32 bits 32 bits sr jump destination address of delay branch instruction sp 5. exception processing rev.4.00 mar. 27, 2008 page 75 of 882 rej09b0108-0400 5.8 usage notes 5.8.1 value of stack pointer (sp) the value of the stack pointer must always be a mu ltiple of four. if it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 value of vector base register (vbr) the value of the vector base regist er must always be a multiple of four. if it is not, an address error will occur when the stack is acce ssed during exception processing. 5.8.3 address errors caused by stacking of address error exception processing when the value of the stack pointer is not a multip le of four, an address error will occur during stacking of the exception processi ng (interrupts, etc.) and addres s error exception processing will start after the first exception proces sing is ended. address errors w ill also occur in the stacking for this address error exception processing. to ensure that address error excep tion processing does not go into an endless loop , no address errors are accepted at that point. this allows program control to be shifted to the service ro utine for address error exception and enables error processing. when an address error occurs during exception pr ocessing stacking, the st acking bus cycle (write) is executed. during stacking of th e status register (sr) and program counter (pc), the value of sp is reduced by 4 for both of sr and pc, therefore the value of sp is still not a multiple of four after the stacking. the address value output during stacki ng is the sp value, so the address itself where the error occurred is output. this means that the write data stacked is undefined. 5. exception processing rev.4.00 mar. 27, 2008 page 76 of 882 rej09b0108-0400 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 77 of 882 rej09b0108-0400 section 6 interrupt controller (intc) the interrupt controller (intc) ascertains the prio rity of interrupt sources and controls interrupt requests to the cpu. 6.1 features ? 16 levels of interrupt priority ? nmi noise canceler function ? occurrence of interrupt can be reported externally (irqout pin) 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 78 of 882 rej09b0108-0400 figure 6.1 shows a block diagram of the intc. irqout nmi irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 ubc dmac h-udi dtc mtu cmt a/d sci wdt iic i/o (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) (interrupt request) input control com- parator interrupt request sr cpu i3 i2 i1 i0 internal bus bus interface ipra to iprj icr1 isr icr2 module bus intc sci: serial communication interface wdt: watchdo g timer iic: iic bus interface i/o: i/o port (port output control unit) icr1, icr2: interrupt control re g ister isr: irq status re g ister ipra to iprj: interrupt priority re g isters a to j sr: status re g ister ipr dter dtc ubc: user break controller dmac: direct memory access controller h-udi: user debu g interface dtc: data transfer controller mtu: multifunction timer unit cmt: compare match timer a/d: a/d converter cpu/dtc request determination priority determination [le g end] figure 6.1 intc block diagram 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 79 of 882 rej09b0108-0400 6.2 input/output pins table 6.1 shows the intc pin configuration. table 6.1 pin configuration name abbreviation i/o function non-maskable interrupt input pin nmi i input of non-maskable interrupt request signal interrupt request input pins irq0 to irq7 i input of maskable interrupt request signals interrupt request output pin irqout o output of notification signal when an interrupt has occurred 6.3 register descriptions the interrupt controller has the following registers. for details on register addresses and register states during each processing, refer to section 25, list of registers. ? interrupt control register 1 (icr1) ? interrupt control register 2 (icr2) ? irq status register (isr) ? interrupt priority register a (ipra) ? interrupt priority register b (iprb) ? interrupt priority register c (iprc) ? interrupt priority register d (iprd) ? interrupt priority register e (ipre) ? interrupt priority register f (iprf) ? interrupt priority register g (iprg) ? interrupt priority register h (iprh) ? interrupt priority register i (ipri) ? interrupt priority register j (iprj) 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 80 of 882 rej09b0108-0400 6.3.1 interrupt contro l register 1 (icr1) icr1 is a 16-bit register that sets the input signal detection mode of the external interrupt input pins nmi and irq0 to irq7 and indicates the input signal level at the nmi pin. bit bit name initial value r/w description 15 nmil 1/0 r nmi input level sets the level of the signal input to the nmi pin. this bit can be read to determine the nmi pin level. this bit cannot be modified. 0: nmi input level is low 1: nmi input level is high 14 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 8 nmie 0 r/w nmi edge select 0: interrupt request is detected on falling edge of nmi input 1: interrupt request is detected on rising edge of nmi input 7 irq0s 0 r/w irq0 sense select this bit sets the irq0 interrupt request detection mode. 0: interrupt request is detected on low level of irq0 input 1: interrupt request is detected on edge of irq0 input (edge direction is selected by icr2) 6 irq1s 0 r/w irq1 sense select this bit sets the irq1 interrupt request detection mode. 0: interrupt request is detected on low level of irq1 input 1: interrupt request is detected on edge of irq1 input (edge direction is selected by icr2) 5 irq2s 0 r/w irq2 sense select this bit sets the irq2 interrupt request detection mode. 0: interrupt request is detected on low level of irq2 input 1: interrupt request is detected on edge of irq2 input (edge direction is selected by icr2) 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 81 of 882 rej09b0108-0400 bit bit name initial value r/w description 4 irq3s 0 r/w irq3 sense select this bit sets the irq3 interrupt request detection mode. 0: interrupt request is detected on low level of irq3 input 1: interrupt request is detected on edge of irq3 input (edge direction is selected by icr2) 3 irq4s 0 r/w irq4 sense select this bit sets the irq4 interrupt request detection mode. 0: interrupt request is detected on low level of irq4 input 1: interrupt request is detected on edge of irq4 input (edge direction is selected by icr2) 2 irq5s 0 r/w irq5 sense select this bit sets the irq5 interrupt request detection mode. 0: interrupt request is detected on low level of irq5 input 1: interrupt request is detected on edge of irq5 input (edge direction is selected by icr2) 1 irq6s 0 r/w irq6 sense select this bit sets the irq6 interrupt request detection mode. 0: interrupt request is detected on low level of irq6 input 1: interrupt request is detected on edge of irq6 input (edge direction is selected by icr2) 0 irq7s 0 r/w irq7 sense select this bit sets the irq7 interrupt request detection mode. 0: interrupt request is detected on low level of irq7 input 1: interrupt request is detected on edge of irq7 input (edge direction is selected by icr2) 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 82 of 882 rej09b0108-0400 6.3.2 interrupt contro l register 2 (icr2) icr2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins irq0 to irq7 . icr2 is, however, valid only when irq interrupt request detection mode is set to the edge detection mode by the sense select bits of irq0 to irq 7 in interrupt control register 1 (icr1). if the irq interrupt request detection mode has been set to low level detection mode, the setting of icr2 is ignored. bit bit name initial value r/w description 15 14 irq0es1 irq0es0 0 0 r/w r/w this bit sets the irq0 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq0 input 01: interrupt request is detected on rising edge of irq0 input 10: interrupt request is det ected on both of falling and rising edge of irq0 input 11: cannot be set 13 12 irq1es1 irq1es0 0 0 r/w r/w this bit sets the irq1 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq1 input 01: interrupt request is detected on rising edge of irq1 input 10: interrupt request is det ected on both of falling and rising edge of irq1 input 11: cannot be set 11 10 irq2es1 irq2es0 0 0 r/w r/w this bit sets the irq2 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq2 input 01: interrupt request is detected on rising edge of irq2 input 10: interrupt request is det ected on both of falling and rising edge of irq2 input 11: cannot be set 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 83 of 882 rej09b0108-0400 bit bit name initial value r/w description 9 8 irq3es1 irq3es0 0 0 r/w r/w this bit sets the irq3 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq3 input 01: interrupt request is detected on rising edge of irq3 input 10: interrupt request is det ected on both of falling and rising edge of irq3 input 11: cannot be set 7 6 irq4es1 irq4es0 0 0 r/w r/w this bit sets the irq4 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq4 input 01: interrupt request is detected on rising edge of irq4 input 10: interrupt request is det ected on both of falling and rising edge of irq4 input 11: cannot be set 5 4 irq5es1 irq5es0 0 0 r/w r/w this bit sets the irq5 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq5 input 01: interrupt request is detected on rising edge of irq5 input 10: interrupt request is det ected on both of falling and rising edge of irq5 input 11: cannot be set 3 2 irq6es1 irq6es0 0 0 r/w r/w this bit sets the irq6 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq6 input 01: interrupt request is detected on rising edge of irq6 input 10: interrupt request is det ected on both of falling and rising edge of irq6 input 11: cannot be set 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 84 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 0 irq7es1 irq7es0 0 0 r/w r/w this bit sets the irq7 interrupt request edge detection mode. 00: interrupt request is detected on falling edge of irq7 input 01: interrupt request is detected on rising edge of irq7 input 10: interrupt request is det ected on both of falling and rising edge of irq7 input 11: cannot be set 6.3.3 irq status register (isr ) isr is a 16-bit register that indicates the interrupt request status of the external interrupt input pins irq0 to irq7 . when irq interrupts are set to edge detection, held interrupt requests can be cleared by writing 0 to irqnf after reading irqnf = 1. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 5 4 3 2 1 0 irq0f irq1f irq2f irq3f irq4f irq5f irq6f irq7f 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w irq0 to irq7 flags these bits display the irq0 to irq7 interrupt request status. [setting condition] ? when interrupt source that is selected by icr 1 and icr2 has occurred. [clearing conditions] ? when 0 is written after reading irqnf = 1 ? when interrupt exception processing has been executed at high level of irqn input under the low level detection mode. ? when irqn interrupt exception processing has been executed under the edge detection mode of falling edge, rising edge or both of falling and rising edge. ? when the disel bit of dtmr of dtc is 0, after dtc has been started by irqn interrupt. 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 85 of 882 rej09b0108-0400 6.3.4 interrupt prio rity registers a to j (ipra to iprj) interrupt priority registers are ten 16-bit readable/w ritable registers that set priority levels from 0 to 15 for interrupts except nmi. for the corr espondence between interr upt request sources and ipr, refer to table 6.2. each of the corresponding interrupt priority ranks are established by setting a value from h'0 to h'f in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. reserved bits that are not assigned should be set h'0 (b'0000.) bit bit name initial value r/w description 15 14 13 12 ipr15 ipr14 ipr13 ipr12 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) 11 10 9 8 ipr11 ipr10 ipr9 ipr8 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 86 of 882 rej09b0108-0400 bit bit name initial value r/w description 7 6 5 4 ipr7 ipr6 ipr5 ipr4 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) 3 2 1 0 ipr3 ipr2 ipr1 ipr0 0 0 0 0 r/w r/w r/w r/w these bits set priority levels for the corresponding interrupt source. 0000: priority level 0 (lowest) 0001: priority level 1 0010: priority level 2 0011: priority level 3 0100: priority level 4 0101: priority level 5 0110: priority level 6 0111: priority level 7 1000: priority level 8 1001: priority level 9 1010: priority level 10 1011: priority level 11 1100: priority level 12 1101: priority level 13 1110: priority level 14 1111: priority level 15 (highest) note: name in the tables above is represented by a general name. name in the list of register is, on the other hand, represent ed by a module name. 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 87 of 882 rej09b0108-0400 6.4 interrupt sources there are five types of interrupt sources: nmi, us er breaks, h-udi, irq, and on-chip peripheral modules. each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). giving an interrupt a priority level of 0 masks it. 6.4.1 external interrupts nmi interrupts: the nmi interrupt has priority 16 and is always accepted. input at the nmi pin is detected by edge. use the nmi edge select bit (nmie) in the interrupt control register 1 (icr1) to select either the rising or falling edge. nmi interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to level 15. irq interrupts: irq interrupts are requested by input from pins irq0 to irq7 . set the irq sense select bits (irq0s to irq7s) of the interrupt control register 1 (icr1) and irq edge select bit (irq0es[1:0] to irq7es[1:0]) of the interrupt control register 2 (icr2) to select low level detection, falling edge detection, or rising edge detection for each pin. the priority level can be set from 0 to 15 for each pin using the interrupt priority registers a and b (ipra and iprb). when irq interrupts are set to low level detection, an interrupt request signal is sent to the intc during the period the irq pin is low level. interrupt request si gnals are not sent to the intc when the irq pin becomes high level. interrupt request levels can be confirmed by reading the irq flags (irq0f to irq7f) of th e irq status register (isr). when irq interrupts are set to falling edge detec tion, interrupt request signals are sent to the intc upon detecting a change on the irq pin from high to low level. the results of detection for irq interrupt request are maintained until the in terrupt request is accepted. it is possible to confirm that irq interrupt requests have been detected by reading the irq flags (irq0f to irq7f) of the irq status register (isr), and by writing a 0 after reading a 1, irq interrupt request detection results can be cleared in irq interrupt exception processing, the interrupt ma sk bits (i3 to i0) of the status register (sr) are set to the priority level value of the acce pted irq interrupt. figur e 6.2 shows the block diagram of this irq7 to irq0 interrupts. 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 88 of 882 rej09b0108-0400 irqns irqnes isr.irqnf irq pins resirqn level detection ed g e detection sq r selection determination cpu interrupt request dtc dtc startin g request (acceptance of irqn interrupt/dtc transfer end/ writin g 0 after readin g irqnf = 1) figure 6.2 block diagram of irq7 to irq0 interrupts control 6.4.2 on-chip peripheral module interrupts on-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. as a different interrupt vector is assigned to each interrupt source, the exception service routine does not have to decide which interrupt has occurred. priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers a to j (ipra to iprj). on-chip peripheral module interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.4.3 user break interrupt a user break interrupt has a priority of level 15, and occurs when the break condition set in the user break controller (ubc) is satisfied. user break interrupt requests are detected by edge and are held until accepted. user br eak interrupt exception processing sets the interrupt mask level bits (i3 to i0) in the status register (sr) to level 15. for more details on the user break interrupt, see section 7, user break controller (ubc). 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 89 of 882 rej09b0108-0400 6.4.4 h-udi interrupt the user debugging interface (h-udi) interrupt has a priority level of 15, and occurs when an h- udi interrupt instruction is serially input. h-udi interrupt requests are detected by edge and are held until accepted. h-udi exception processing sets the interrupt mask leve l bits (i3-i0) in the status register (sr) to level 15. for more deta ils on the h-udi interrupt, see section 22, user debugging interface (h-udi). 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 90 of 882 rej09b0108-0400 6.5 interrupt exception processing vectors table table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. each interrupt source is allocated a different vector number and vect or table address offset. vector table addresses are calculated from the vector numb ers and address offsets. in interrupt exception processing, the exception service ro utine start address is fetched from the vector table indicated by the vector table address. for the details of calculation of vector table address, see table 5.4. irq interrupts and on-chip periph eral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priori ty registers a to j (ipr a to iprj). however, the smaller vector number has interrupt source, th e higher priority ranking is assigned among two or more interrupt sources specified by the same ipr, and the priority ranking cannot be changed. a power-on reset assigns priority level 0 to irq interrupts and on-chip peripheral module interrupts. if the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order indicated in table 6.2. table 6.2 interrupt exception pro cessing vectors and priorities interrupt source name vector no . vector table starting address ipr default priority external pin nmi 11 h'0000002c ? high user break 12 h'00000030 ? h-udi 14 h'00000038 ? ? reserved by system 15 h'0000003c ? interrupts irq0 64 h'00000100 ipra15 to ipra12 irq1 65 h'00000104 ipra11 to ipra8 irq2 66 h'00000108 ipra7 to ipra4 irq3 67 h'0000010c ipra3 to ipra0 irq4 68 h'00000110 iprb15 to iprb12 irq5 69 h'00000114 iprb11 to iprb8 irq6 70 h'00000118 iprb7 to iprb4 irq7 71 h'0000011c iprb3 to iprb0 low 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 91 of 882 rej09b0108-0400 interrupt source name vector no . vector table starting address ipr default priority dei0 72 h'00000120 iprc15 to iprc12 high dei1 76 h'00000130 iprc11 to iprc8 dei2 80 h'00000140 iprc7 to iprc4 dmac dei3 84 h'00000150 iprc3 to iprc0 tgia_0 88 h'00000160 iprd15 to iprd12 tgib_0 89 h'00000164 tgic_0 90 h'00000168 tgid_0 91 h'0000016c mtu channel 0 tciv_0 92 h'00000170 iprd11 to iprd8 tgia_1 96 h'00000180 iprd7 to iprd4 tgib_1 97 h'00000184 tciv_1 100 h'00000190 iprd3 to iprd0 mtu channel 1 tciu_1 101 h'00000194 mtu channel 2 tgia_2 104 h'000001a0 ipre15 to ipre12 tgib_2 105 h'000001a4 tciv_2 108 h'000001b0 ipre11 to ipre8 tciu_2 109 h'000001b4 mtu channel 3 tgia_3 112 h'000001c0 ipre7 to ipre4 tgib_3 113 h'000001c4 tgic_3 114 h'000001c8 tgid_3 115 h'000001cc tciv_3 116 h'000001d0 ipre3 to ipre0 mtu channel 4 tgia_4 120 h' 000001e0 iprf15 to iprf12 tgib_4 121 h'000001e4 tgic_4 122 h'000001e8 tgid_4 123 h'000001ec tciv_4 124 h'000001f0 iprf11 to iprf8 sci channel 0 eri_0 128 h'00000200 iprf7 to iprf4 rxi_0 129 h'00000204 txi_0 130 h'00000208 tei_0 131 h'0000020c low 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 92 of 882 rej09b0108-0400 interrupt source name vector no . vector table starting address ipr default priority sci channel 1 eri_1 132 h'00000210 iprf3 to iprf0 high rxi_1 133 h'00000214 txi_1 134 h'00000218 tei_1 135 h'0000021c a/d adi0 136 h'00000220 iprg15 to iprg12 adi1 137 h'00000224 dtc swdtend 140 h'000002 30 iprg11 to iprg8 cmt cmi0 144 h'00000240 iprg7 to iprg4 cmi1 148 h'00000250 iprg3 to iprg0 watchdog timer iti 152 h'00000260 iprh15 to iprh12 ? reserved by system 153 h'00000264 ? i/o (mtu) mtuoei 156 h'00000270 iprh11 to iprh8 ? reserved by system 160 to 167 h'00000290 to h'0000029c ? sci channel 2 eri_2 168 h'000002a0 ipri15 to ipri12 rxi_2 169 h'000002a4 txi_2 170 h'000002a8 tei_2 171 h'000002ac sci channel 3 eri_3 172 h'000002b0 ipri11 to ipri8 rxi_3 173 h'000002b4 txi_3 174 h'000002b8 tei_3 175 h'000002bc ? reserved by system 176 to 188 h'000002c0 to h'000002fc ? iic ici 192 h'00000300 iprj7 to iprj4 ? reserved by system 196 to 247 h'00000304 to h'000003dc low 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 93 of 882 rej09b0108-0400 6.6 operation 6.6.1 interrupt sequence the sequence of interrupt operations is explained below. figure 6.3 is a flowchart of the operations. 1. the interrupt request sources send interrupt request signals to the interrupt controller. 2. the interrupt controller selects the highest priority interrupt in the interrupt requests sent, according to the priority levels se t in interrupt priority level se tting registers a to j (ipra to iprj). interrupts that have lower-priority than that of the selected interrupt are ignored.* if interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest pr iority is selected acco rding to the default priority order indicated in table 6.2. 3. the interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (i3 to i0) in the cpu?s status register (sr). if the request priority level is equal to or less than the level set in i3 to i0, th e request is ignored. if the request priority level is higher than the level in bits i3 to i0, th e interrupt controller accept s the interrupt and sends an interrupt request signal to the cpu. 4. when the interrupt controller accepts an interrupt, a low level is output from the irqout pin. 5. the cpu detects the interrupt request sent fro m the interrupt controller when cpu decodes the instruction to be executed. in stead of executing the decoded instruction, the cpu starts interrupt exception processing (figure 6.5). 6. sr and pc are saved onto the stack. 7. the priority level of the accepted interrupt is copi ed to the interrupt mask level bits (i3 to i0) in the status register (sr). 8. when the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the irqout pin. when the accepted interrupt is sensed by edge, a high level is output from the irqout pin at the moment when the cpu starts interrupt exception processing instead of instruction execution as noted in (5) above. however, if the interrupt controller accepts an interrupt with a higher prior ity than the interrupt ju st to be accepting, the irqout pin holds low level. 9. the cpu reads the start address of the excep tion service routine from the exception vector table for the accepted interrupt, jumps to that ad dress, and starts executing the program. this jump is not a delay branch. note: * interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. irq interrupt s, however, can be cancelled by accessing 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 94 of 882 rej09b0108-0400 the irq status register (isr). interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. pro g ram execution state interrupt? nmi? user break? i3 to i0 level 14? level 14 interrupt? level 1 interrupt? i3 to i0 level 13? i3 to i0 = level 0? no yes no no no no no no no no yes yes yes yes yes yes yes yes irqout = low * 1 save sr to stack save pc to stack copy accept-interrupt level to i3 to i0 irqout = hi g h read exception vector table branch to exception service routine * 2 h-udi interrupt? no yes level 15 interrupt? notes: i3 to i0 are interrupt mask bits of status re g ister (sr) in the cpu 1. irqout is the same si g nal as interrupt request si g nal to the cpu (see fi g ure 6.1). therefore, irqout is output when the request priority level is hi g her than the level in bits i3?i0 of sr. 2. when the accepted interrupt is sensed by ed g e, a hi g h level is output from the irqout pin at the moment when the cpu starts interrupt exception processin g instead of instruction execution (namely, before savin g sr to stack). however, if the interrupt controller accepts an interrupt with a hi g her priority than the interrupt just to be accepted and has output an interrupt request to the cpu, the irqout pin holds low level. figure 6.3 interrupt sequence flowchart 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 95 of 882 rej09b0108-0400 6.6.2 stack after interrupt exception processing figure 6.4 shows the stack afte r interrupt exception processing. 32 bits 32 bits pc * 1 sr address 4n?8 4n?4 4n sp * 2 notes: 1. pc: start address of the next instruction (return destination instruction) after the executin g instruction 2. always make sure that sp is a multiple of 4 figure 6.4 stack after inte rrupt exception processing 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 96 of 882 rej09b0108-0400 6.7 interrupt response time table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. figure 6.5 shows an example of the pipeline operation when an irq interrupt is accepted. table 6.3 interrupt response time number of states item nmi, peripheral module irq remarks dmac/dtc active judgment 0 or 1 1 1 state required for interrupt signals for which dmac/dtc activation is possible interrupt priority judgment and comparison with sr mask bits 2 3 wait for completion of sequence currently being executed by cpu x ( 0) x ( 0) the longest sequence is for interrupt or address-error exception processing (x = 4 + m1 + m2 + m3 + m4). if an interrupt-masking instruction follows, however, the time may be even longer. time from start of interrupt exception processing until fetch of first instruction of exception service routine starts 5 + m1 + m2 + m3 5 + m1 + m2 + m3 performs the saving pc and sr, and vector address fetch. total: (7 or 8) + m1 + m2 + m3+x 9 + m1 + m2 + m3 + x interrupt response time minimum: 10 12 0.20 to 0.24 s at 50 mhz maximum: 12 + 2 (m1 + m2 + m3) + m4 13 + 2 (m1 + m2 + m3) + m4 0.38 to 0.40 s at 50 mhz * note: m1 to m4 are the number of states needed for the following memory accesses. m1: sr save (longword write) m2: pc save (longword write) m3: vector address read (longword read) m4: fetch first instruction of interrupt service routine * 0.38 to 0.40 s at 50 mhz is the value in the case that m1 = m2 = m3 = m4 = 1. 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 97 of 882 rej09b0108-0400 fde mee mme ee fd f 3 1 3 interrupt acceptance irq m1 m2 1 m3 1 5 + m1 + m2 + m3 instruction (instruction replaced by interrupt exception processin g ) overrun fetch interrupt service routine start instruction f: instruction fetch (instruction fetched from memory where pro g ram is stored). d: instruction decodin g (fetched instruction is decoded). e: instruction execution (data operation and address calculation is performed accordin g to the results of decodin g ). m: memory access (data in memory is accessed). figure 6.5 example of pipeline opera tion when irq interrupt is accepted 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 98 of 882 rej09b0108-0400 6.8 data transfer with interrupt request signals the following data transfers can be done using interrupt request signals: ? activate dmac only, cpu interrupts do not occur ? activate dtc only, cpu interrupts according to dtc settings interrupt sources that are activ ated by dmac are masked with out being input to intc. mask condition is as follows: mask condition = dme ? (de0 ? interrupt source select 0 + de1 ? interrupt source select 1 + de2 ? interrupt source select 2 + de3 ? interrupt source select 3) the intc masks cpu interrupts when the corresp onding dte bit is 1. the conditions for clearing dte and interrupt source flag are listed below. dte clear condition = dtc transfer end ? dteclr interrupt source flag clear condition = dtc transfer end ? dteclr +dmac transfer end where: dteclr = disel + counter 0. figure 6.6 shows a control block diagram. interrupt source fla g clear (by dtc) cpu interrupt request dtc activation request dteclr transfer end dter dmac dte clear interrupt source interrupt source (not desi g nated as dmac activation source) interrupt source fla g clear (by dmac) figure 6.6 interrupt control block diagram 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 99 of 882 rej09b0108-0400 6.8.1 handling interrupt reque st signals as sources fo r dtc activating and cpu interrupt, but not dmac activating 1. do not select dmac activating so urces or clear the dte bit to 0. 2. for dtc, set the corresponding dte bits and disel bits to 1. 3. activating sources are applied to the dtc when interrupts occur. 4. when the dtc performs a data transfer, it clears the dte bit to 0 and sends an interrupt request to the cpu. the activ ating source is not cleared. 5. the cpu clears interrupt sources in the interrupt processing r outine then confirms the transfer counter value. when the transfer counter value is not 0, the cpu sets the dte bit to 1 and allows the next data transfer . if the transfer counter valu e = 0, the cpu performs the necessary end processing in the interrupt processing routine. 6.8.2 handling interrupt reque st signals as sources for activating dmac, but not cpu interrupt and dtc activating 1. select dmac activating sources and set the dme bit to 1. then, cpu interrupt and dtc activating sources are masked regardless of the settin gs of the interrupt priority register and the dtc register. 2. activating sources are applied to the dmac when in terrupts occur. 3. the dmac clears the interrupt sources when st arting transfer. 6.8.3 handling interrupt reque st signals as source for dt c activating, but not cpu interrupt and dm ac activating 1. do not select dmac activating so urces or clear the dme bit to 0. 2. for dtc, set the corresponding dte bits to 1 and clear the disel bits to 0. 3. activating sources are applied to the dtc when interrupts occur. 4. when the dtc performs a data transfer, it clears the activating source. an interrupt request is not sent to the cpu, because the dte bit is hold to 1. 5. however, when the transfer counter value = 0 the dte bit is cleared to 0 and an interrupt request is sent to the cpu. 6. the cpu performs the necessa ry end processing in the in terrupt processing routine. 6. interrupt controller (intc) rev.4.00 mar. 27, 2008 page 100 of 882 rej09b0108-0400 6.8.4 handling interrupt reque st signals as source for cp u interrupt but not dmac and dtc activating 1 do not select dmac activating so urces or clear the dme bit to 0. 2. for dtc, clear the corr esponding dte bits to 0. 3. when interrupts occur, interrupt requests are sent to the cpu. 4. the cpu clears the interrupt source and perfor ms the necessary proce ssing in the interrupt processing routine. 7. user break controller (ubc) ubc0001a_000020010800 rev.4.00 mar. 27, 2008 page 101 of 882 rej09b0108-0400 section 7 user break controller (ubc) the user break controller (ubc) provides functions that make program debugging easier. by setting break conditions in the ubc, a user break in terrupt is generated according to the contents of the bus cycle generated by the cpu or dmac/dtc. this function makes it easy to design an effective self-monitoring debugger, and customers of the chip can easily debug their programs without using a large in-circuit emulator. 7.1 features ? there are 5 types of break co mpare conditions as follows: ? address ? cpu cycle or dmac/dtc cycle ? instruction fetch or data access ? read or write ? operand size: longword/word/byte ? user break interrupt generated upon satisfying break conditions ? user break interrupt generated before an instruction is executed by selecting break in the cpu instruction fetch. ? module standby mode can be set 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 102 of 882 rej09b0108-0400 figure 7.1 shows a block diagram of the ubc. module bus ubbr ubamrh ubamrl ubarh ubarl break condition comparator user break interrupt g eneratin g circuit bus interface internal bus interrupt request interrupt controller [le g end] ubarh, ubarl: user break address re g isters h, l ubamrh, ubamrl: user break address mask re g isters h, l ubbr: user break bus cycle re g ister ubcr: user break control re g ister ubcr ubc figure 7.1 user break controller block diagram 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 103 of 882 rej09b0108-0400 7.2 register descriptions the ubc has the following registers. for details on register addresses and register states during each processing, refer to sec tion 25, list of registers. ? user break address register h (ubarh) ? user break address register l (ubarl) ? user break address mask register h (ubamrh) ? user break address mask register l (ubamrl) ? user break bus cycle register (ubbr) ? user break control register (ubcr) 7.2.1 user break address register (ubar) the user break address register (ubar) consists of two registers: user break address register h (ubarh) and user break address register l (ubarl ). both are 16-bit readable/writable registers. ubarh specifies the upper bits (bits 31 to 16 ) of the address for th e break condition, while ubarl specifies the lower bits (bits 15 to 0). the initial value of ubar is h'00000000. ? ubarh bits 15 to 0: specifies user break address 31 to 16 (uba31 to uba16) ? ubarl bits 15 to 0: specifies user break address 15 to 0 (uba15 to uba0) 7.2.2 user break address mask register (ubamr) the user break address mask register (ubamr) consists of two registers: user break address mask register h (ubamrh) and user break address mask register l (ubamrl). both are 16-bit readable/writable registers. ubam rh specifies whether to mask any of the break address bits set in ubarh, and ubamrl specifies whether to mask any of the break address bits set in ubarl. ? ubamrh bits 15 to 0: specifies user break address mask 31 to 16 (ubm31 to ubm16) ? ubamrl bits 15 to 0: specifies user br eak address mask 15 to 0 (ubm15 to ubm0) 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 104 of 882 rej09b0108-0400 bit bit name initial value r/w description ubamrh15 to ubamrh0 ubm31 to ubm16 all 0 r/w user break address mask 31 to 16 0: corresponding uba bit is included in the break conditions 1: corresponding uba bit is not included in the break conditions ubamrl15 to ubamrl0 ubm15 to ubm0 all 0 r/w user break address mask 15 to 0 0: corresponding uba bit is included in the break conditions 1: corresponding uba bit is not included in the break conditions 7.2.3 user break bus cycle register (ubbr) the user break bus cycle register (ubbr) is a 16-b it readable/writable register that sets the four break conditions. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 6 cp1 cp0 0 0 r/w r/w cpu cycle/dmac, dtc cycle select 1 and 0 these bits specify break conditions for cpu cycles or dmac/dtc cycles. 00: no user break interrupt occurs 01: break on cpu cycles 10: break on dtc or dmac cycles 11: break on both cpu and dmac or dtc cycles 5 4 id1 id0 0 0 r/w r/w instruction fetch/data access select1 and 0 these bits select whether to break on instruction fetch and/or data access cycles. 00: no user break interrupt occurs 01: break on instruction fetch cycles 10: break on data access cycles 11: break on both instruction fetch and data access cycles 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 105 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 2 rw1 rw0 0 0 r/w r/w read/write select 1 and 0 these bits select whether to break on read and/or write cycles 00: no user break interrupt occurs 01: break on read cycles 10: break on write cycles 11: break on both read and write cycles 1 0 sz1 sz0 0 0 r/w r/w operand size select 1 and 0 * these bits select operand size as a break condition. 00: operand size is not a break condition 01: break on byte access 10: break on word access 11: break on longword access note: * when breaking on an instruction fetch, clear the sz0 bit to 0. all instructions are considered to be accessed in word-size (eve n when there are instructions in on-chip memory and two instruction fetches are pe rformed simultaneously in one bus cycle). operand size is word for instructions or determined by the operand size specified for the cpu/dtc, dmac data access. it is not determined by the bus width of the space being accessed. 7.2.4 user break control register (ubcr) the user break control register (ubcr) is a 16-b it readable/writable register that enables or disables user break interrupts. bit bit name initial value r/w description 15 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 ubid 0 r/w user break disable enables or disables user break interrupt request generation in the event of a user break condition match. 0: user break interrupt request is enabled 1: user break interrupt request is disabled 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 106 of 882 rej09b0108-0400 7.3 operation 7.3.1 flow of user break operation the flow from setting of break conditions to user break interrupt exception processing is described below: 1. the user break addresses are set in the user break address register (ubar), the desired masked bits in the addresses are set in the user brea k address mask register (ubamr) and the breaking bus cycle type is set in the user break bus cy cle register (ubbr). if even one of the three groups of the ubbr?s cpu cycle/dmac, dtc cycle select bits (cp1, cp0), instruction fetch/data access select bits (id1, id0), and read/write select bits (rw1, rw0) is set to 00 (no user break generated), no user break interrupt w ill be generated even if all other conditions are satisfied. when using user break interrupts, always be certain to establish bit conditions for all of these three groups. 2. the ubc uses the method shown in figure 7.2 to determine whether set conditions have been satisfied or not. when the set conditions are sa tisfied, the ubc sends a user break interrupt request signal to the interrupt controller (intc). 3. the interrupt controller checks the accepted user break interrupt request signal?s priority level. the user break interrupt has prio rity level 15, so it is accepted only if the interrupt mask level in bits i3 to i0 in the status register (sr) is 14 or lower. when the i3 to i0 bit level is 15, the user break interrupt cannot be accepted but it is held pending until user break interrupt exception processing can be carried out. cons equently, user break interrupts within nmi exception service routines cannot be accepted, since the i3 to i0 b it level is 15. however, if the i3 to i0 bit level is changed to 14 or lower at the start of the nmi exception service routine, user break interrupts become acceptable thereafter. see section 6, interr upt controller (intc), for the details on the handling of priority levels. 4. the intc sends the user break interrupt request signal to the cpu, which begins user break interrupt exception pro cessing upon receipt. see section 6. 6, operation, for the details on interrupt exception processing. 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 107 of 882 rej09b0108-0400 ubarh/ubarl ubamrh/ubamrl internal address bits 31?0 cpu cycle dmac/dtc cycle instruction fetch data access read cycle write cycle byte size word size lon g word size 32 32 32 32 32 cp1 cp0 id1 id0 rw1 rw0 sz1 sz0 user break interrupt ubid figure 7.2 break condition determination method 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 108 of 882 rej09b0108-0400 7.3.2 break on on-chip memo ry instruction fetch cycle data in on-chip memory (on-chip rom and/or ra m) is always accessed as 32-bits data in one bus cycle. therefore, two instructions can be retr ieved in one bus cycle when fetching instructions from on-chip memory. at such times, only one bus cycle is generated, but it is possible to cause independent breaks by setting the start addresses of both instructions in the user break address register (ubar). in other words, when wanting to effect a break using the latter of two addresses retrieved in one bus cycle, set the start address of that instruction in ubar. the break will occur after execution of the former instruction. 7.3.3 program counter (pc) values saved break on instruction fetch: the program counter (pc) value sa ved to the stack in user break interrupt exception processing is the address that matches the break condition. the user break interrupt is generated before the fetched instruction is executed. if a break condition is set in an instruction fetch cycle placed immedi ately after a delayed branch instru ction (delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user break interrupt is not accepted immediately, but the break condition establis hing instruction is ex ecuted. the user break interrupt is accepted after execution of the instruc tion that has accepted the in terrupt. in this case, the pc value saved is the start address of the inst ruction that will be executed after the instruction that has accepted the interrupt. break on data acce ss (cpu/dtc, dmac): the program counter (pc) value is the top address of the next instruction after the last instruction executed before the user break exception processing started. when data access (cpu/dtc, dmac) is set as a break condition, the place where the break will occur cannot be specified exactly. the break will occur at the instruction fetched close to where the data access th at is to receive the break occurs. 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 109 of 882 rej09b0108-0400 7.4 examples of use break on cpu instruction fetch cycle 1. register settings: ubarh = h'0000 ubarl = h'0404 ubbr = h'0054 ubcr = h'0000 conditions set: address: h'00000404 bus cycle: cpu, inst ruction fetch, read (operand size is not included in conditions) interrupt requests enabled a user break interrupt will occur before the instruction at address h'00000404. if it is possible for the instruction at h'00000402 to accept an interrupt, the user break exception processing will be executed after execution of that instruction. the instruction at h'00000404 is not executed. the pc value saved is h'00000404. 2. register settings: ubarh = h'0015 ubarl = h'389c ubbr = h'0058 ubcr = h'0000 conditions set: address: h'0015389c bus cycle: cpu, instruction fetch, write (operand size is not included in conditions) interrupt requests enabled a user break interrupt does not occur because the instruction fetch cycle is not a write cycle. 3. register settings: ubarh = h'0003 ubarl = h'0147 ubbr = h'0054 ubcr = h'0000 conditions set: address: h'00030147 bus cycle: cpu, inst ruction fetch, read (operand size is not included in conditions) interrupt requests enabled a user break interrupt does not occur because the instruction fetch was performed for an even address. however, if the first instruction fetch ad dress after the branch is an odd address set by these conditions, user break interrupt exception processing will be carried out after address error excepti on processing. 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 110 of 882 rej09b0108-0400 break on cpu data access cycle 1. register settings: ubarh = h'0012 ubarl = h'3456 ubbr = h'006a ubcr = h'0000 conditions set: address: h'00123456 bus cycle: cpu, data access, write, word interrupt requests enabled a user break interrupt occurs when word data is written into address h'00123456. 2. register settings: ubarh = h'00a8 ubarl = h'0391 ubbr = h'0066 ubcr = h'0000 conditions set: address: h'00a80391 bus cycle: cpu, data access, read, word interrupt requests enabled a user break interrupt does not occur because the word access was performed on an even address. break on dmac/dtc cycle 1. register settings: ubarh = h'0076 ubarl = h'bcdc ubbr = h'00a7 ubcr = h'0000 conditions set: address: h'0076bcdc bus cycle: dmac/dtc, data access, read, longword interrupt requests enabled a user break interrupt occurs when longword data is read from address h'0076bcdc. 2. register settings: ubarh = h'0023 ubarl = h'45c8 ubbr = h'0094 ubcr = h'0000 conditions set: address: h'002345c8 bus cycle: dmac/dtc, instruction fetch, read (operand size is not included in conditions) interrupt requests enabled a user break interrupt does not occur because no instruction fetch is performed in the dmac/dtc cycle. 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 111 of 882 rej09b0108-0400 7.5 usage notes 7.5.1 simultaneous fetching of two instructions two instructions may be simultaneously fetched in instruction fetch operation. once a break condition is set on the latter of these two instructions, a user break interrupt will occur before the latter instruction, even though the contents of th e ubc registers are modifi ed to change the break conditions immediately after the fetching of the former instruction. 7.5.2 instruction fetches at branches when a conditional branch instruction or trapa instruction causes a branch, the order of instruction fetching and execution is as follows: 1. when branching with a conditional branch instruction: bt and bf instructions when branching with a trapa instruction: trapa instruction a. instruction fetch order branch instruction fetch next instruction overrun fetch overrun fetch of instruction after the next branch destination instruction fetch b. instruction execution order branch instruction execution branch destination instruction execution 2. when branching with a delayed conditional bran ch instruction: bt/s and bf/s instructions a. instruction fetch order branch instruction fetch next instruction fetch (delay slot) overrun fetch of instruction after the next branch destination instruction fetch b. instruction execution order branch instruction execution delay slot instruction execution branch destination instruction execution thus, when a conditional branch instruction or trapa instruction causes a branch, the branch destination instruction will be fetched after an overrun fetch of the next instruction or the instruction after the next. however, as the instruct ion that is the object of the break does not break until fetching and execution of the instruction have been confirmed, the overrun fetches described above do not become objects of a break. if data accesses are also included in break conditi ons besides instruction fetch, a break will occur because the instruction overrun fe tch is also regarded as satisfying the data break condition. 7. user break controller (ubc) rev.4.00 mar. 27, 2008 page 112 of 882 rej09b0108-0400 7.5.3 contention between user break and exception processing if a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user break is in contention and is accepted in the decode stage for that instruction (or the next instruction), user break exception processing may not be performed after completion of the higher-priority exception service routine (on return by rte). thus, if a user break condition is specified to the branch destination instruction fetch after a branch (bra, braf, bt, bf, bt/s, bf/s, bsr, bsrf, jmp, jsr, rts, rte, exception processing), and that branch instruction accepts an exception processing with higher priority than a user break interrupt, user break exception processing is not performed after completion of the exception serv ice routine. therefore, a user break condition should not be set for the fetch of the branch destination instruction after a branch. 7.5.4 break at non-delay branch instruction jump destination when a branch instruction without delay slot (including exception processing) jumps to the destination instruction by executing the branch, a user break will not be ge nerated even if a user break condition has been set for the first jump destination instruction fetch. 7.5.5 module standby mode setting the ubc can set the module disable/enable by using the module standby control register 2 (mstcr2). by releasing the module standby mo de, register access becomes to be enabled. by setting the mstp0 bit of mstcr2 to 1, the ubc is in the module standby mode in which the clock supply is halted. see section 24, power-down modes, for further details. 8. data transfer controller (dtc) dtcsh21a_010020020700 rev.4.00 mar. 27, 2008 page 113 of 882 rej09b0108-0400 section 8 data transfer controller (dtc) this lsi includes a data transfer controller (dtc ). the dtc can be activated by an interrupt or software, to transfer data. figure 8.1 shows a block diagram of the dtc. the dtc?s register information is stored in the on-chip ram. when the dtc is used, the rame bit in syscr must be set to 1. 8.1 features ? transfer possible over any number of channels ? three transfer modes normal, repeat, and block transfer modes available ? one activation source can trigger a number of data transfer s (chain transfer) ? direct specification of 32 -bit address space possible ? activation by software is possible ? transfer can be set in byte, word, or longword units ? the interrupt that activated the dtc can be requested to the cpu ? module standby mode can be set 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 114 of 882 rej09b0108-0400 on-chip rom on-chip ram external memory external device (memory- mapped) on-chip peripheral module cpu interrupt request source clear control re g ister control dtmr dtcr dtsar dtdar dtiar dter dtcsr dtbr dtc dtc module bus activation control internal bus peripheral bus external bus request priority control interrupt request bus interface bus controller [le g end] dtmr: dtc mode re g ister dtcr: dtc transfer count re g ister dtsar: dtc source address re g ister dtdar: dtc destination address re g ister dtiar: dtc initial address re g ister dter: dtc enable re g ister dtcsr: dtc control/status re g ister dtbr: dtc information base re g ister figure 8.1 block diagram of dtc 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 115 of 882 rej09b0108-0400 8.2 register descriptions the dtc has the following registers. ? dtc mode register (dtmr) ? dtc source address register (dtsar) ? dtc destination address register (dtdar) ? dtc initial address register (dtiar) ? dtc transfer count register a (dtcra) ? dtc transfer count register b (dtcrb) these six registers cannot be di rectly accessed from the cpu. when activated, the dtc transfer desired set of register information that is stored in an on-chip ram to the corresponding dtc registers. after the data transfer, it writes a set of updated register information back to the ram. ? dtc enable register a (dtea) ? dtc enable register b (dteb) ? dtc enable register c (dtec) ? dtc enable register d (dted) ? dtc enable register e (dtee) ? dtc enable register g (dteg) ? dtc control/status register (dtcsr) ? dtc information base register (dtbr) for details on register addresses and register states during each processing, refer to section 25, list of registers. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 116 of 882 rej09b0108-0400 8.2.1 dtc mode register (dtmr) dtmr is a 16-bit register that selects the dtc operating mode. bit bit name initial value r/w description 15 14 sm1 sm0 undefined undefined ? ? source address mode 1 and 0 these bits specify a dtsar operation after a data transfer. 0x: dtsar is fixed 10: dtsar is incremented after a transfer (by +1 when sz 1 and 0 = 00; by +2 when sz 1 and 0 = 01; by +4 when sz 1 and 0 = 10) 11: dtsar is decremented after a transfer (by ?1 when sz 1 and 0 = 00; by ?2 when sz 1 and 0 = 01; by ?4 when sz 1 and 0 = 10) 13 12 dm1 dm0 undefined undefined ? ? destination address mode 1 and 0 these bits specify a dtdar operation after a data transfer. 0x: dtdar is fixed 10: dtdar is incremented after a transfer (by +1 when sz 1 and 0 = 00; by +2 when sz 1 and 0 = 01; by +4 when sz 1 and 0 = 10) 11: dtdar is decremented after a transfer (by ?1 when sz 1 and 0 = 00; by ?2 when sz 1 and 0 = 01; by ?4 when sz 1 and 0 = 10) 11 10 md1 md0 undefined undefined ? ? dtc mode 1 and 0 these bits specify the dtc transfer mode. 00: normal mode 01: repeat mode 10: block transfer mode 11: setting prohibited 9 8 sz1 sz0 undefined undefined ? ? dtc data transfer size 1 and 0 specify the size of data to be transferred. 00: byte-size transfer 01: word-size transfer 10: longword-size transfer 11: setting prohibited 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 117 of 882 rej09b0108-0400 bit bit name initial value r/w description 7 dts undefined ? dtc transfer mode select specifies whether the source or the destination is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: destination is repeat area or block area 1: source is repeat area or block area 6 chne undefined ? dtc chain transfer enable when this bit is set to 1, a chain transfer will be performed. 0: chain transfer is canceled 1: chain transfer is set in data transfer with chne set to 1, determination of the end of the specified num ber of transfers, clearing of the activation source flag, and clearing of dter is not performed. 5 disel undefined ? dtc interrupt select when this bit is set to 1, a cpu interrupt request is generated every time a data transfer ends. when this bit is set to 0, a cpu interrupt request is generated at the time when the specified number of data transfer ends. 4 nmim undefined ? dtc nmi mode this bit designates whether to terminate transfers when an nmi is input during dtc transfers. 0: terminate dtc transfer upon an nmi 1: continue dtc transfer unt il end of transfer being executed 3 to 0 ? undefined ? reserved these bits have no effect on dtc operation. the write value should always be 0. [legend] x: don?t care 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 118 of 882 rej09b0108-0400 8.2.2 dtc source address register (dtsar) the dtc source address register (dtsar) is a 32-bit register th at specifies the dtc transfer source address. for the wo rd size transfer, specify an even so urce address. for the longword size transfer, specify a multip le-of-four address. the initial value of dtsar is undefined. 8.2.3 dtc destination address register (dtdar) the dtc destination address register (dtdar) is a 32-bit register that sp ecifies the dtc transfer destination address. for the word size transfer, specify an even source address. for the longword size transfer, specify a multiple-of-four address. the initial value of dtdar is undefined. 8.2.4 dtc initial address register (dtiar) the dtc initial address register (dtiar) is a 32-b it register that specifies the initial transfer source/transfer destination address in repeat mode. in repeat mode, when the dts bit is set to 1, specify the initial transfer source ad dress in the repeat area, and when the dts bit is cleared to 0, specify the initial transfer destina tion address in the repeat area. the initial value of dtiar is undefined. 8.2.5 dtc transfer count register a (dtcra) dtcra is a 16-bit register that de signates the number of times data is to be transferred by the dtc. in normal mode, the dtcra functions as a 16-bit tr ansfer counter (1 to 65536). it is decremented by 1 every time data is transferred, and transfer ends when the count r eaches h'0000. the number of transfers is 1 when the set value is h'0001, 65535 when it is h'ffff, and 65536 when it is h'0000. in repeat mode, upper 8-bit dtcrah maintain s the transfer count value and lower 8-bit dtcral functions as an 8-bit transfer counter. the number of transfers is 1 when the set value is dtcrah = dtcral = h'01, 255 when they are h'ff, and 256 when it is h'00. in block transfer mode, the dtcra functions as a 16-bit transfer counter. the number of transfers is 1 when the set value is h'0001, 65535 when it is h'ffff, and 65536 when it is h'0000. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 119 of 882 rej09b0108-0400 the initial value of dtcra is undefined. 8.2.6 dtc transfer count register b (dtcrb) the dtcrb is a 16-bit register that designates th e block length in block transfer mode. the block length is 1 when the set value is h'0001, 65535 when it is h'ffff , and 65536 when it is h'0000. the initial value of dtcrb is undefined. 8.2.7 dtc enable registers (dter) dter which is comprised of six registers, dtea to dtee, dteg, is a register that specifies dtc activation interrupt sources. the corresponden ce between interrupt sour ces and dte bits is shown in table 8.1. bit bit name initial value r/w description 7 6 5 4 3 2 1 0 dte * 7 dte * 6 dte * 5 dte * 4 dte * 3 dte * 2 dte * 1 dte * 0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w dtc activation enable setting this bit to 1 specifies the corresponding interrupt source to a dtc activation source. [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended ? 0 is written to the bit to be cleared after 1 has been read from the bit these bits are not cleared when the disel bit is 0 and the specified number of transfers have not ended. [setting condition] 1 is written to the bit to be set after a 0 has been read from the bit note: * the last character of the dtc enable register?s name comes here. example: dteb3 in dteb, etc. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 120 of 882 rej09b0108-0400 8.2.8 dtc control/status register (dtcsr) dtcsr is a 16-bit readable /writable register that is used to disable/enable dtc activation by software and to set the dtc vector addresses for software activation. it also indicates the dtc transfer status. bit bit name initial value r/w description 15 to 11 ? all 0 r reserved these bits have no effect on dtc operation. the write value should always be 0. 10 nmif 0 r/(w) * 1 nmi flag bit this bit indicates that an nmi interrupt has occurred. 0: no nmi interrupts [clearing condition] ? write 0 after reading the nmif bit 1: nmi interrupt has been generated when the nmif bit is set, dtc transfers are not allowed even if the dter bit is set to 1. if, however, a transfer has already started with the nmim bit of the dtmr set to 1, execut ion will continue until that transfer ends. 9 ae 0 r/(w) * 1 address error flag this bit indicates that an address error by the dtc has occurred. 0: no address error by the dtc [clearing condition] ? write 0 after reading the ae bit 1: an address error by the dtc occurred when the ae bit is set, dtc transfers are not allowed even if the dter bit is set to 1. 8 swdte 0 r/w * 2 dtc software activation enable setting this bit to 1 activates dtc. 0: dtc activation by software disabled 1: dtc activation by software enabled 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 121 of 882 rej09b0108-0400 bit bit name initial value r/w description 7 6 5 4 3 2 1 0 dtvec7 dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w r/w dtc software activation vectors 7 to 0 these bits specify the lower eight bits of the vector addresses for dtc activation by software. a vector address is calculated as h'0400 + dtvec (7:0). always specify 0 for dtvec0. for example, when dtvec7 to dtvec0 = h'10, the vector address is h'0410. when the bit swdte is 0, these bits can be written to. notes: 1. for the nmif and ae bits, only a 0 write after a 1 read is possible. 2. for the swdte bit, a 1 write is always possi ble, but a 0 write is possible only after a 1 is read. 8.2.9 dtc information base register (dtbr) the dtbr is a 16-bit readable/writable register th at specifies the upper 16 bits of the memory address containing dtc transf er information. always access the dtbr in word or longword units. if it is accessed in byte units the register contents will become undefined at the time of a write, and undefined values will be read out upon reads. the initial value of dtbr is undefined. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 122 of 882 rej09b0108-0400 8.3 operation 8.3.1 activation sources the dtc operates when activated by an interrupt or by a write to dtcsr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dter bit. at the end of a data transfer (or the last co nsecutive transfer in the cas e of chain transfer), the activation source interrupt flag or corresponding dter bit is cleared. the activation source flag, in the case of rxi_2, for exampl e, is the rdrf flag of sci2. when a dtc is activated by an interrupt, existing cpu mask level and interrupt controller priorities have no effect. if th ere is more than one activation source at the same time, the dtc operates in accordance with the default priorities. figure 8.2 shows a block diagram of activation source control. for details see section 6, interrupt controller (intc). irq on-chip peripheral interrupt requests cpu interrupt requests (those not desi g nated as dtc activatin g sources) interrupt requests (those not desi g nated as dmac activatin g sources) source fla g clear source fla g clear dter intc dtc dtc control clear dtc activation request dmac figure 8.2 activating so urce control block diagram 8.3.2 location of register information and dtc vector table figure 8.3 shows the allocation of register information in memory space. the register information start addresses are designated by dtbr for the upper 16 bits, and the dtc vector table for the lower 16 bits. the allocation in order from the register information start addr ess in normal mode is dtmr, dtcra, 4 bytes empty (no effect on dtc operation), dtsar, then dtdar. in repeat mode it is dtmr, dtcra, dtiar, dtsar, and dtdar. in block transfer mode, it is dtmr, dtcra, 2 bytes empty (no effect on dtc oper ation), dtcrb, dtsar, then dtdar. fundamentally, certain ram areas are designated for addresses storing register information. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 123 of 882 rej09b0108-0400 memory space normal mode dtmr dtcra dtsar dtdar memory space repeat mode dtmr dtcra dtsar dtdar memory space block transfer mode re g ister information dtmr dtcra dtcrb dtiar dtsar dtdar re g ister information start address figure 8.3 dtc register informat ion allocation in memory space figure 8.4 shows the correspondence between dtc vector addresses and register information allocation. for each dtc activatin g source there are 2 bytes in the dtc vector table, which contain the register info rmation start address. table 8.1 shows the correspondence between ac tivating sources and vector addresses. when activating with software, the vector addre ss is calculated as h'0400 + dtvec[7:0]. through dtc activation, a register information star t address is read from the vector table, then register information placed in memory space is read from that register information start address. always designate register information start addresses in multiples of four. dtbr dtc vector table dtc vector address transfer information start address (upper 16 bits) re g ister information memory space re g ister information start address (lower 16 bits) figure 8.4 correspondence between dtc vector address and transfer information 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 124 of 882 rej09b0108-0400 table 8.1 interrupt sources , dtc vector addresses, and corresponding dtes activating source generator activating source dtc vector address dte bit transfer source transfer destination priority mtu (ch4) tgia_4 h'00000400 dtea7 arbitrary * arbitrary * high tgib_4 h'00000402 dtea6 arbitrary * arbitrary * tgic_4 h'00000404 dtea5 arbitrary * arbitrary * tgid_4 h'00000406 dtea4 arbitrary * arbitrary * tciv_4 h'00000408 dtea3 arbitrary * arbitrary * mtu (ch3) tgia_3 h'0000040a dtea2 arbitrary * arbitrary * tgib_3 h'0000040c dtea1 arbitrary * arbitrary * tgic_3 h'0000040e dtea0 arbitrary * arbitrary * tgid_3 h'00000410 dteb7 arbitrary * arbitrary * mtu (ch2) tgia_2 h'00000412 dteb6 arbitrary * arbitrary * tgib_2 h'00000414 dteb5 arbitrary * arbitrary * mtu (ch1) tgia_1 h'00000416 dteb4 arbitrary * arbitrary * tgib_1 h'00000418 dteb3 arbitrary * arbitrary * mtu (ch0) tgia_0 h'0000041a dteb2 arbitrary * arbitrary * tgib_0 h'0000041c dteb1 arbitrary * arbitrary * tgic_0 h'0000041e dteb0 arbitrary * arbitrary * tgid_0 h'00000420 dtec7 arbitrary * arbitrary * a/d converter (ch0) adi0 h'00000422 dtec6 addr0 arbitrary * external pin irq0 h'00000424 dtec5 arbitrary * arbitrary * irq1 h'00000426 dtec4 arbitrary * arbitrary * irq2 h'00000428 dtec3 arbitrary * arbitrary * irq3 h'0000042a dtec2 arbitrary * arbitrary * irq4 h'0000042c dtec1 arbitrary * arbitrary * irq5 h'0000042e dtec0 arbitrary * arbitrary * irq6 h'00000430 dted7 arbitrary * arbitrary * irq7 h'00000432 dted6 arbitrary * arbitrary * cmt (ch0) cmi0 h'00000434 dted5 arbitrary * arbitrary * cmt (ch1) cmi1 h'00000436 dted4 arbitrary * arbitrary * low 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 125 of 882 rej09b0108-0400 activating source generator activating source dtc vector address dte bit transfer source transfer destination priority rxi_0 h'00000438 dted3 rdr_0 arbitrary * high sci0 txi_0 h'0000043a dted2 arbitrary * tdr_0 rxi_1 h'0000043c dted1 rdr_1 arbitrary * sci1 txi_1 h'0000043e dted0 arbitrary * tdr_1 reserved ? h'00000440 to h'00000443 ? ? ? a/d converter (ch1) adi1 h'00000444 dtee5 addr1 arbitrary * reserved ? h'00000446 ? ? ? sci2 rxi_2 h'00000448 dtee3 rdr_2 arbitrary * txi_2 h'0000044a dtee2 arbitrary * tdr_2 sci3 rxi_3 h'0000044c dtee1 rdr_3 arbitrary * txi_3 h'0000044e dtee0 arbitrary * tdr_3 reserved ? h'00000450 to h'0000045f ? ? ? iic ici h'00000460 dteg7 icdr (receive) arbitrary * (receive) arbitrary * (transmit) icdr (transmit) reserved ? h'00000462 to h'0000049f ? ? ? software write to dtcsr h'0400+ dtvec[7:0] ? arbitrary * arbitrary * low note: * external memory, memory-mapped external devices, on-chip memory, on-chip peripheral modules (excluding dmac and dtc) 8.3.3 dtc operation register information is stored in an on-chip ram. when activated, the dtc reads register information in an on-chip ram and transfers da ta. after the data tran sfer, it writes updated register information back to the ram. pre-storage of register informati on in the ram makes it possible to transfer data over any required number of channels. the transfer mode can be specified as normal, rep eat, and block transfer mode. setting the chne bit to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 126 of 882 rej09b0108-0400 the 32-bit dtsar designates the dtc transfer source address and the 32-bit dtdar designates the transfer destination addr ess. after each transfer, dtsa r and dtdar are independently incremented, decremented, or left fixed depending on its register information. yes no yes yes yes yes no no no no start initial settin g s dtmr, dtcr, dtiar, dtsar, dtdar transfer request g enerated? nmif = ae = 0? dtc vector read transfer information read dtcra = dtcra ? 1 (normal/block transfer mode) dtcral = dtcral ? 1 (repeat mode) dtsar, dtdar update dtcrb = dtcrb ? 1 (block transfer mode) transfer (1 transfer unit) block transfer mode and dtcrb 0? transfer information write nmi or address error end transfer information write chne = 0? nmif ? nmim + ae = 1? when disel = 1 or dtcra = 0 (normal/block transfer mode) when disel = 1 (repeat transfer mode) cpu interrupt request figure 8.5 dtc operation flowchart 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 127 of 882 rej09b0108-0400 normal mode: performs the transfer of one byte, one wo rd, or one longword for each activation. the total transfer count is 1 to 65536. once the specified number of transfers have ended, a cpu interrupt can be requested. table 8.2 lists the register functions in normal mode. figure 8.6 shows a memory map in normal mode. table 8.2 normal mode register functions values written back upon transfer information write register function when dtcra is other than 1 when dtcra is 1 dtmr operation mode control dtmr dtmr dtcra transfer count dtcra ? 1 dtcra ? 1 (= h'0000) dtsar transfer source address increment/decrement/fixed increment/decrement/fixed dtdar transfer destination address increment/decrement/fixed increment/decrement/fixed transfer dtsar dtdar figure 8.6 memory mapping in normal mode repeat mode: performs the transfer of one byte, one word, or one longword for each activation. either the transfer source or transfer destination is designated as the repeat area. table 8.3 lists the register functions in repeat mode. from 1 to 25 6 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. figure 8.7 shows a memory map in repeat mode. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 128 of 882 rej09b0108-0400 table 8.3 repeat mode register functions values written back upon transfer information write register function when dtcra is other than 1 when dtcra is 1 dtmr operation mode control dtmr dtmr dtcrah transfer count save dtcrah dtcrah dtcral transfer count dtcral ? 1 dtcrah dtiar initial address (not wri tten back) (not written back) dtsar transfer source address increment/decrement/fixed (dts = 0) increment/ decrement/fixed (dts = 1) dtiar dtdar transfer destination address increment/decrement/fixed (dts = 0) dtiar (dts = 1) increment/ decrement/fixed transfer dtsar or dtdar dtdar or dtsar repeat area figure 8.7 memory mapping in repeat mode 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 129 of 882 rej09b0108-0400 block transfer mode: performs the transfer of one block for each one activation. either the transfer source or transfer destination is designated as the block area. the block length is specified between 1 and 65536. when the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. the other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified numb er of transfers have ended, a cpu interrupt is requested. table 8.4 lists the register functions in block transfer mode. figure 8.8 shows a memory map in block transfer mode. table 8.4 block transfer mode register functions register function values written back upon transfer information write dtmr operation mode control dtmr dtcra transfer count dtcra ? 1 dtcrb block length (not written back) dtsar transfer source address (dts = 0) increment/ decrement/ fixed (dts = 1) dtsar initial value dtdar transfer destination address (dts = 0) dtdar initial value (dts = 1) increment/ decrement/ fixed 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 130 of 882 rej09b0108-0400 transfer dtsar or dtdar dtdar or dtsar block area ? ? ? first block nth block figure 8.8 memory mapping in block transfer mode chain transfer: setting the chne bit to 1 enables a numb er of data transfers to be performed consecutively in a single activation source. dtsar, dtdar, dtmr, dtcra, and dtcrb can be set independently. figure 8.9 shows the chain transfer. when activated, the dtc reads the register informa tion start address stored at the vector address, and then reads the first re gister information at that start addre ss. after the data transfer, the chne bit will be tested. when it has been set to 1, dt c reads next register in formation located in a consecutive area and performs the data transfer. these sequences are repeated until the chne bit is cleared to 0. in the case of transfer with chne set to 1, an in terrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the di sel bit to 1, and the interrupt source flag for the activatio n source is not affected. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 131 of 882 rej09b0108-0400 dtc vector address source destination source destination re g ister information chne = 1 re g ister information chne = 0 re g ister information start address figure 8.9 chain transfer 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 132 of 882 rej09b0108-0400 8.3.4 interrupt source an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt cont roller priority level control. in the case of activation by software, a software activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine should clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during da ta transfer even if the swdte bit is set to 1. note: when the dtcr contains a value equal to or greater than 2, the swdte bit is automatically cleared to 0. when the dtcr is set to 1, the swdte bit is again set to 1. 8.3.5 operation timing when register information is located in on-chip ram, each mode requires 4 cycles for transfer information reads, and 3 cycles for writes. activatin g source address vector read transfer information read data transfer rw transfer information write dtc request figure 8.10 dtc operation timing example (normal mode) 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 133 of 882 rej09b0108-0400 8.3.6 dtc execution state counts table 8.5 shows the execution state for one dtc da ta transfer. furthermor e, table 8.6 shows the state counts needed for execution state. table 8.5 execution state of dtc mode vector read i register information read/write j data read k data write l internal operation m normal 1 7 1 1 1 repeat 1 7 1 1 1 block transfer 1 7 n n 1 n: block size (default set values of dtcrb) table 8.6 state counts n eeded for execution state access objective on-chip ram on-chip rom internal i/o register external device bus width 32 32 8 or 16 8 16 32 access state 1 1 2 * 1 3 * 2 2 2 2 vector read s i ? 1 ? ? 4 2 2 register information read/write s j 1 1 ? ? 8 4 2 execution state byte data read s k 1 1 2 3 2 2 2 word data read s k 1 1 2 3 4 2 2 long word data read s k 1 1 4 6 8 4 2 byte data write s l 1 1 2 3 2 2 2 word data write s l 1 1 2 3 4 2 2 longword data write s l 1 1 4 6 8 4 2 internal operation s m 1 notes: 1. two state access modul e: port, int, cmt, sci, etc. 2. three state access module: wdt, ubc, etc. the execution state count is calcul ated using the following formula. indicates the number of transfers by one ac tivating source (count + 1 when chne bit is set to 1). execution state count = i s i + (j s j + k s k + l s l ) + m s m 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 134 of 882 rej09b0108-0400 8.4 procedures for using dtc 8.4.1 activation by interrupt the procedure for using the dtc with interrupt activation is as follows: 1. set the dtmr, dtcra, dtsar, dtdar, dt crb, and dtiar register information in memory space. 2. specify the register info rmation start address with dt br and the dtc vector table. 3. set the corresponding dter bit to 1. 4. the dtc is activated when an interrupt source occurs. 5. when interrupt requests are not made to the cp u, the interrupt source is cleared, but the dter is not. when interrupts are requested, the inte rrupt source is not cleared, but the dter is. 6. interrupt sources are cleared within the cpu interrupt routine. when doing continuous dtc data transfers, set the dter to 1 after reading dter = 0. 8.4.2 activation by software the procedure for using the dtc with software activation is as follows: 1. set the dtmr, dtcra, dtsar, dtdar, dt crb, and dtiar register information in memory space. 2. set the start address of the register information in the dtbr register and the dtc vector address. 3. check that the swdte bit is 0. 4. write 1 to swdte bit and the vector number to dtvec. 5. check the vector number written to dtvec. 6. after the end of one data transfer, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the speci fied number of data transfers have ended, the swdte bit is held at 1 and a cpu interrupt is requested. 7. the swdte bit is cleared to 0 within the cpu interrupt routine. for continuous dtc data transfer, set the swdte bit to 1 after confirming that its current value is 0. then write the vector number to dtvec fo r continuous dtc transfer. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 135 of 882 rej09b0108-0400 8.4.3 dtc use example the following is a dtc use example of a 128-byte data reception by the sci: 1. the settings are: dtmr source address fixed (sm1 = sm0 = 0), destination address incremented (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), byte size (sz1 = sz0 = 0), one transfer per activating source (chne = 0), and a cpu interrupt request after the designated number of data transfers (disel = 0). dts bit can be set to any value. 128 (h'0080) is set in dtcra, the rdr address of th e sci is set in dtsar, and the start address of the ram storing the receive data is se t in dtdar. dtcrb can be set to any value. 2. set the register information start addr ess with dtbr and the dtc vector table. 3. set the corresponding dter bit to 1. 4. set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error duri ng the sci reception operation will disable subsequent reception, th e cpu should be enabled to accept receive error interrupts. 5. each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activ ated. the receive data is transferred from rdr to ram by the dtc. dtdar is incremented an d dtcra is decremented. the rdrf flag is automatically cleared to 0. 6. when dtcra is 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the corresponding bit in dter is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine should perform completion processing. 8. data transfer controller (dtc) rev.4.00 mar. 27, 2008 page 136 of 882 rej09b0108-0400 8.5 usage notes 8.5.1 prohibition against dmac/ dtc register access by dtc dmac and dtc register access by the dmac is prohibited. 8.5.2 module standby mode setting dtc operation can be disabled or enabled using the module standby control register. the initial setting is for dtc operation to be halted. regi ster access is enabled by clearing module standby mode. when the mstp24 and mstp25 bits in mstcr1 are set to 1, the dtc clock is halted and the dtc enters module standby mode. the mstp24 and mstp25 bit cannot be set to 1 during activation of the dtc. in addition, when the module standby mode is entered, clear all the dter bits to 0. for details, refer to section 24, power-down modes. 8.5.3 on-chip ram the dtmr, dtsar, dtdar, dtcra,dtcrb and dtia r registers are all located in on-chip ram. when the dtc is used, the rame b it in syscr must not be cleared to 0. 9. bus state controller (bsc) bsc1001a_020020030800 rev.4.00 mar. 27, 2008 page 137 of 882 rej09b0108-0400 section 9 bus state controller (bsc) the bus state controller (bsc) divides up the address spaces and outputs control signals for various types of memory. this enables memories like sram and rom to be connected directly to the chip without external circuitry. 9.1 features the bsc has the following features: ? address space is divided into four spaces ? a maximum linear 2 mbytes for on-chip rom enabled mode, and a maximum 4 mbytes for on-chip rom disabl ed mode, for address spaces cs0 and cs4 ? a maximum linear 4 mbytes for addres s space cs1 to cs3 and cs5 to cs7 ? bus width (8, 16, or 32 bits) can be selected for each space ? wait states can be inserted by software for each space ? wait state insertion with wait pin in external memory space access ? outputs control signals for each space accor ding to the type of memory connected ? on-chip rom and ram interfaces ? on-chip rom and ram access of 32 bits in 1 state 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 138 of 882 rej09b0108-0400 figure 9.1 shows the bsc block diagram. ramer wcr1 bcr1 bcr2 wcr2 internal bus module bus bus interface on-chip memory control unit memory control unit wait control unit area control unit w rhh , wrhl wrh , wrl cs0 to cs7 rd wait bsc wcr1: wait control re g ister 1 wcr2: bcr1: bus control re g ister 1 bcr2: bus control re g ister 2 ramer: ram emulation re g ister wait control re g ister 2 refer to section 19, flash memory (f-ztat version), for ramer. pins cs4 to cs7 are available only for the masked rom version and romless version. note: figure 9.1 bsc block diagram 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 139 of 882 rej09b0108-0400 9.2 input/output pins table 9.1 shows the bus state controller pin configuration. table 9.1 pin configuration name abbr. i/o description address bus a21 to a0 output address output (address bus a21 to a18 pins are disabled and i/o port function is enabled after power-on-reset.) data bus d31 to d0 i/o 32-bit data bus chip select cs0 to cs7 * output chip select signal indicating the area being accessed read rd output strobe that in dicates the read cycle wrhh output strobe that indicates a write cycle to the first byte (d31 to d24) wrhl output strobe that indicates a write cycle to the second byte (d23 to d16) wrh output strobe that indicates a write cycle to the third byte (d15 to d8) write wrl output strobe that indicates a wr ite cycle to the fourth byte (d7 to d0) wait wait input wait state request signal bus request breq input bus request input bus acknowledge back output bus use enable output note: * pins cs4 to cs7 are available only for the masked rom version and romless version. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 140 of 882 rej09b0108-0400 9.3 register configuration the bsc has five registers. for details on these register addresses and register states in each processing states, refer to s ection 25, list of registers. these registers are used to control wait states, bus width, and interfaces with memories like rom and sram. all registers are 16 bits. ? bus control register 1 (bcr1) ? bus control register 2 (bcr2) ? wait control register 1 (wcr1) ? wait control register 2 (wcr2) ? ram emulation register (ramer) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 141 of 882 rej09b0108-0400 9.4 address map figure 9.2 shows the address format used by this lsi. output address: output from the address pins cs space selection: decoded, outputs cs0 to cs7 when a31 to a24 = 00000000 or 00000001 space selection: not output externally; used to select the type of space on-chip rom space or cs space when 00000000 or 00000001 (h'00 or h'01) reserved (do not access) when 00000010 to 11111110 (h'02 to h'fe) on-chip peripheral module space or on-chip ram space when 11111111 (h'ff) a31 to a24 a23, a22 a21 a0 figure 9.2 address format this chip uses 32-bit addresses: ? bits a31 to a24 are used to select the t ype of space and are not output externally. ? bits a23 and a22 are decoded and output as chip select signals ( cs0 to cs7 ) for the corresponding areas when bits a31 to a24 are 00000000 or 00000001. ? bits a21 to a0 are output externally. table 9.2 shows the address map. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 142 of 882 rej09b0108-0400 table 9.2 address map ? on-chip rom enabled mode address space memory size bus width h'00000000 to h'0003ffff on-chip rom on-chip rom 256 kbytes 32 bits h'00040000 to h'001fffff reserved reserved h'00200000 to h'003fffff cs0 space external space 2 mbytes 8/16/32 bits * 1 h'00400000 to h'007fffff cs1 space external space 4 mbytes 8/16/32 bits * 1 h'00800000 to h'00bfffff cs2 space external space 4 mbytes 8/16/32 bits * 1 h'00c00000 to h'00ffffff cs3 space external space 4 mbytes 8/16/32 bits * 1 h'01000000 to h'011fffff reserved reserved h'01200000 to h'013fffff cs4 space * 3 external space 2 mbytes 8/16/32 bits * 1 h'01400000 to h'017fffff cs5 space * 3 external space 4 mbytes 8/16/32 bits * 1 h'01800000 to h'01bfffff cs6 space * 3 external space 4 mbytes 8/16/32 bits * 1 h'01c00000 to h'01ffffff cs7 space * 3 external space 4 mbytes 8/16/32 bits * 1 h'02000000 to h'ffff7fff reserved reserved h'ffff8000 to h'ffffbfff on-chip peripheral module on-chip peripheral module 16 kbytes 8/16 bits h'ffffc000 to h'ffffdfff reserved reserved h'ffffe000 to h'ffffffff on-chip ram on-chip ram 8 kbytes 32 bits 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 143 of 882 rej09b0108-0400 ? on-chip rom disabled mode address space memory size bus width h'00000000 to h'003fffff cs0 space external space 4 mbytes 8/16/32 bits * 2 h'00400000 to h'007fffff cs1 space external space 4 mbytes 8/16/32 bits * 1 h'00800000 to h'00bfffff cs2 space external space 4 mbytes 8/16/32 bits * 1 h'00c00000 to h'00ffffff cs3 space external space 4 mbytes 8/16/32 bits * 1 h'01000000 to h'013fffff cs4 space * 3 external space 4 mbytes 8/16/32 bits * 2 h'01400000 to h'017fffff cs5 space * 3 external space 4 mbytes 8/16/32 bits * 1 h'01800000 to h'01bfffff cs6 space * 3 external space 4 mbytes 8/16/32 bits * 1 h'01c00000 to h'01ffffff cs7 space * 3 external space 4 mbytes 8/16/32 bits * 1 h'02000000 to h'ffff7fff reserved reserved h'ffff8000 to h'ffffbfff on-chip peripheral module on-chip peripheral module 16 kbytes 8/16 bits h'ffffc000 to h'ffffdfff reserved reserved h'ffffe000 to h'ffffffff on-chip ram on-chip ram 8 kbytes 32 bits notes: do not access reserved spaces. operati on cannot be guaranteed if they are accessed. spaces other than on-chip rom, on-chip ra m, and on-chip peripheral modules cannot be used in single-chip mode. 1. selected by setting the on-chip register. 2. selected by the mode pin: 8 or 16 bits in sh7144 (112 pins) 16 or 32 bits in sh7145 (144 pins) 3. spaces cs4 to cs7 are available only for the masked rom version and romless version. these spaces are reserved for the flash memory version and emulator. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 144 of 882 rej09b0108-0400 9.5 register descriptions 9.5.1 bus control register 1 (bcr1) bcr1 is a 16-bit readable/writable register that enables access to the mtu control registers and specifies the bus size of each cs space. when usin g the sh7144, specify the bus size as word (16- bit) or smaller size. write bits 7 to 0 of bcr1 during the initialization stage after a power-on reset, and do not change the values thereafter. in on-chip rom enabled mode, do not access any of each cs space until completion of register initialization. in on-c hip rom disabled mode, do not access cs spaces other than cs0 and cs4 until completion of register initialization. bit bit name initial value r/w description 15 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 13 mturwe 1 r/w mtu read/write enable this bit enables mtu control register access. for details, refer to section 11, multi-function timer pulse unit (mtu). 0: mtu control register access is disabled 1: mtu control register access is enabled 12 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 a3lg 0 r/w cs3 and cs7 space longword this bit specifies the cs3 and cs7 space bus size. this bit is valid only for the sh7145. this bit is reserved in sh7144. this bit is always read as 0 and should always be written with 0. 0: depends on the value set with the a3sz bit in this register. 1: longword (32 bits) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 145 of 882 rej09b0108-0400 bit bit name initial value r/w description 6 a2lg 0 r/w cs2 and cs6 space longword this bit specifies the cs2 and cs6 space bus size. this bit is valid only for the sh7145. this bit is reserved in sh7144. this bit is always read as 0 and should always be written with 0. 0: depends on the value set with the a2sz bit in this register. 1: longword (32 bits) 5 a1lg 0 r/w cs1 and cs5 space longword this bit specifies the cs1 and cs5 space bus size. this bit is valid only for the sh7145. this bit is reserved in sh7144. this bit is always read as 0 and should always be written with 0. 0: depends on the value set with the a1sz bit in this register. 1: longword (32 bits) 4 a0lg 0 r/w cs0 and cs4 space longword this bit specifies the cs0 and cs4 space bus size. this bit is valid only for the sh7145. this bit is reserved in sh7144. this bit is always read as 0 and should always be written with 0. 0: depends on the value set with the a0sz bit in this register. 1: longword (32 bits) note: a0lg is valid only in on-chip rom enabled mode. the cs0 and cs4 space bus size is specified with the mode pin in on-chip rom disabled mode. 3 a3sz 1 r/w cs3 and cs7 space size this bit specifies the cs3 and cs7 space bus size in a3lg = 0. 0: byte (8 bits) 1: word (16 bits) note: in a3lg = 1, this bit is ignored and the cs3 and cs7 space bus size is longword (32 bits). 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 146 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 a2sz 1 r/w cs2 and cs6 space size this bit specifies the cs2 and cs6 space bus size in a2lg = 0. 0: byte (8 bits) 1: word (16 bits) note: in a2lg = 1, this bit is ignored and the cs2 and cs6 space bus size is longword (32 bits). 1 a1sz 1 r/w cs1 and cs5 space size this bit specifies the cs1 and cs5 space bus size in a1lg = 0. 0: byte (8 bits) 1: word (16 bits) note: in a1lg = 1, this bit is ignored and the cs1 and cs5 space bus size is longword (32 bits). 0 a0sz 1 r/w cs0 and cs4 space size this bit specifies the cs0 and cs4 space bus size in a0lg = 0. 0: byte (8 bits) 1: word (16 bits) note: this bit is valid only in on-chip rom enabled mode. the cs0 and cs4 space bus size is specified with the mode pin in on-chip rom disabled mode. even in on-chip rom enabled mode, this bit is ignored in a0lg = 1, and the cs0 and cs4 space bus size is longword (32 bits). 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 147 of 882 rej09b0108-0400 9.5.2 bus control register 2 (bcr2) bcr2 is a 16-bit readable/writable register that specifies the number of idle cycles and cs signal assert extension of each cs space. bit bit name initial value r/w description 15 14 iw31 iw30 1 1 r/w r/w idle cycles in cs3 and cs7 space cycles after read access to the cs3 and cs7 spaces, these bits insert idle cycles (1) when the write cycle to the cs3 space continues, (2) when the write cycle to the cs7 space continues, or (3) when continuous access is made to cs spaces except for the cs3 and cs7 spaces. 00: no idle cycle inserted after access to the cs3 and cs7 spaces 01: one idle cycle inserted after access to the cs3 and cs7 spaces 10: two idle cycles inserted after access to the cs3 and cs7 spaces 11: three idle cycles insert ed after access to the cs3 and cs7 spaces 13 12 iw21 iw20 1 1 r/w r/w idle cycles in cs2 and cs6 space cycles after read access to the cs2 and cs6 spaces, these bits insert idle cycles (1) when the write cycle to the cs2 space continues, (2) when the write cycle to the cs6 space continues, or (3) when continuous access is made to cs spaces except for the cs2 and cs6 spaces. 00: no idle cycle inserted after access to the cs2 and cs6 spaces 01: one idle cycle inserted after access to the cs2 and cs6 spaces 10: two idle cycles inserted after access to the cs2 and cs6 spaces 11: three idle cycles insert ed after access to the cs2 and cs6 spaces 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 148 of 882 rej09b0108-0400 bit bit name initial value r/w description 11 10 iw11 iw10 1 1 r/w r/w idle cycles in cs1 and cs5 space cycles after read access to the cs1 and cs5 spaces, these bits insert idle cycles (1) when the write cycle to the cs1 space continues, (2) when the write cycle to the cs5 space continues, or (3) when continuous access is made to cs spaces except for the cs1 and cs5 spaces. 00: no idle cycle inserted after access to the cs1 and cs5 spaces 01: one idle cycle inserted after access to the cs1 and cs5 spaces 10: two idle cycles inserted after access to the cs1 and cs5 spaces 11: three idle cycles insert ed after access to the cs1 and cs5 spaces 9 8 iw01 iw00 1 1 r/w r/w idle cycles in cs0 and cs4 space cycles after read access to the cs0 and cs4 spaces, these bits insert idle cycles (1) when the write cycle to the cs0 space continues, (2) when the write cycle to the cs4 space continues, or (3) when continuous access is made to cs spaces except for the cs0 and cs4 spaces. 00: no idle cycle inserted after access to the cs0 and cs4 spaces 01: one idle cycle inserted after access to the cs0 and cs4 spaces 10: two idle cycles inserted after access to the cs0 and cs4 spaces 11: three idle cycles insert ed after access to the cs0 and cs4 spaces 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 149 of 882 rej09b0108-0400 bit bit name initial value r/w description 7 cw3 1 r/w idle cycles at contin uous access to cs3 and cs7 spaces this bit inserts an idle cycle and negates the cs3 signal to make the bus cycle end obvious when accessing the cs3 space continuously. an idle cycl e set by this bit is also inserted when access is made to the cs7 space after access to the cs3 space. in addition, an idle cycle set by this bit is inserted when continuous access is made to the cs7 space, and when access is made to the cs3 space after access to the cs7 space. 0: no idle cycle inserted at co ntinuous access to the cs3 and cs7 spaces. 1: one idle cycle inserted at continuous access to the cs3 and cs7 spaces. when the write cycle follows the read cycle, the larger of the value specified with iw an d that specified with cw is used as the idle cycles to be inserted. 6 cw2 1 r/w idle cycles at contin uous access to cs2 and cs6 spaces this bit inserts an idle cycle and negates the cs2 signal to make the bus cycle end obvious when accessing the cs2 space continuously. an idle cycl e set by this bit is also inserted when access is made to the cs6 space after access to the cs2 space. in addition, an idle cycle set by this bit is inserted when continuous access is made to the cs6 space, and when access is made to the cs2 space after access to the cs6 space. 0: no idle cycle inserted at co ntinuous access to the cs2 and cs6 spaces. 1: one idle cycle inserted at continuous access to the cs2 and cs6 spaces. when the write cycle follows the read cycle, the larger of the value specified with iw an d that specified with cw is used as the idle cycles to be inserted. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 150 of 882 rej09b0108-0400 bit bit name initial value r/w description 5 cw1 1 r/w idle cycles at contin uous access to cs1 and cs5 spaces this bit inserts an idle cycle and negates the cs1 signal to make the bus cycle end obvious when accessing the cs1 space continuously. an idle cycl e set by this bit is also inserted when access is made to the cs5 space after access to the cs1 space. in addition, an idle cycle set by this bit is inserted when continuous access is made to the cs5 space, and when access is made to the cs1 space after access to the cs5 space. 0: no idle cycle inserted at co ntinuous access to the cs1 and cs5 spaces. 1: one idle cycle inserted at continuous access to the cs1 and cs5 spaces. when the write cycle follows the read cycle, the larger of the value specified with iw an d that specified with cw is used as the idle cycles to be inserted. 4 cw0 1 r/w idle cycles at contin uous access to cs0 and cs4 spaces this bit inserts an idle cycle and negates the cs0 signal to make the bus cycle end obvious when accessing the cs0 space continuously. an idle cycl e set by this bit is also inserted when access is made to the cs4 space after access to the cs0 space. in addition, an idle cycle set by this bit is inserted when continuous access is made to the cs4 space, and when access is made to the cs0 space after access to the cs4 space. 0: no idle cycle inserted at co ntinuous access to the cs0 and cs4 spaces. 1: one idle cycle inserted at continuous access to the cs0 and cs4 spaces. when the write cycle follows the read cycle, the larger of the value specified with iw an d that specified with cw is used as the idle cycles to be inserted. 3 sw3 1 r/w cs assert period extension for cs3 and cs7 spaces this bit inserts a cycle to pr event the assert period of rd and wrx from extending the assert period of cs3 and cs7 . 0: no cycle inserted for cs assert period for cs3 and cs7 spaces. 1: cs assert extension for cs3 and cs7 spaces. (each one cycle inserted before and after the bus cycle) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 151 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 sw2 1 r/w cs assert period extension for cs2 and cs6 spaces this bit inserts a cycle to pr event the assert period of rd and wrx from extending the assert period of cs2 and cs6 . 0: no cycle inserted for cs assert period for cs2 and cs6 spaces. 1: cs assert extension for cs2 and cs6 spaces. (each one cycle inserted before and after the bus cycle) 1 sw1 1 r/w cs assert period extension for cs1 and cs5 spaces this bit inserts a cycle to pr event the assert period of rd and wrx from extending the assert period of cs1 and cs5 . 0: no cycle inserted for cs assert period for cs1 and cs5 spaces. 1: cs assert extension for cs1 and cs5 spaces. (each one cycle inserted before and after the bus cycle) 0 sw0 1 r/w cs assert period extension for cs0 and cs4 spaces this bit inserts a cycle to pr event the assert period of rd and wrx from extending the assert period of cs0 and cs4 . 0: no cycle inserted for cs assert period for cs0 and cs4 spaces. 1: cs assert extension for cs0 and cs4 spaces. (each one cycle inserted before and after the bus cycle) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 152 of 882 rej09b0108-0400 9.5.3 wait control register 1 (wcr1) wcr1 is a 16-bit readable/writable register that sp ecifies the number of wait cycles (0 to 15) for each cs space. bit bit name initial value r/w description 15 14 13 12 w33 w32 w31 w30 1 1 1 1 r/w r/w r/w r/w cs3 and cs7 space wait specification these bits specify the number of waits for cs3 and cs7 space access. 0000: no wait (external wait input disabled) 0001: one wait (external wait input enabled) . . . 1111: 15 waits (external wait input enabled) 11 10 9 8 w23 w22 w21 w20 1 1 1 1 r/w r/w r/w r/w cs2 and cs6 space wait specification these bits specify the number of waits for cs2 and cs6 space access. 0000: no wait (external wait input disabled) 0001: one wait (external wait input enabled) . . . 1111: 15 waits (external wait input enabled) 7 6 5 4 w13 w12 w11 w10 1 1 1 1 r/w r/w r/w r/w cs1 and cs5 space wait specification these bits specify the number of waits for cs1 and cs5 space access. 0000: no wait (external wait input disabled) 0001: one wait (external wait input enabled) . . . 1111: 15 waits (external wait input enabled) 3 2 1 0 w03 w02 w01 w00 1 1 1 1 r/w r/w r/w r/w cs0 and cs4 space wait specification these bits specify the number of waits for cs0 and cs4 space access. 0000: no wait (external wait input disabled) 0001: one wait (external wait input enabled) . . . 1111: 15 waits (external wait input enabled) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 153 of 882 rej09b0108-0400 9.5.4 wait control register 2 (wcr2) wcr2 is a 16-bit readable/writable register that specifies the number of access cycles to the cs space in dma single address mode transfer. do not perform dma single address transfer before setting wcr2. bit bit name initial value r/w description 15 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 1 0 dsw3 dsw2 dsw1 dsw0 1 1 1 1 r/w r/w r/w r/w number of wait cycles for access to cs space in dma single address mode these bits specify the number of wait cycles (0 to 15) for access to the cs space in dma single address mode. these bits are independent of the w bit in wcr1. 0000: no wait (external wait insertion disabled) 0001: one wait (external wait insertion enabled) : 1111: 15 waits (external waits insertion enabled) 9.5.5 ram emulation register (ramer) ramer is a 16-bit readable/writable register th at selects the ram area to be used when emulating realtime programming of flash memory. for details, refer to section 19.5.5, ram emulation register (ramer). 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 154 of 882 rej09b0108-0400 9.6 accessing external space a strobe signal is output in external space accesse s to provide primarily for sram or rom direct connections. 9.6.1 basic timing external access bus cycles are perfor med in 2 states. figure 9.3 show s the basic timing of external space access. write data dack wrxx data rd csn address ck read t1 t2 figure 9.3 basic timing of external space access during a read, irrespective of operand size, a ll bits in the data bus width for the access space (address) accessed by rd signal are fetched by the lsi. during a write, the wrhh (bits 31 to 24), the wrhl (bits 23 to 16), the wrh (bits 15 to 8), and the wrl (bits 7 to 0) signal indicate the byte location to be written. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 155 of 882 rej09b0108-0400 9.6.2 wait state control the number of wait states insert ed into external space access states can be controlled using the wcr settings. the specified number of tw cycles are inserted as software cycles at the timing shown in figure 9.4. write data dack wrxx data rd csn address ck read t1 tw t2 figure 9.4 wait state timing of ext ernal space access (s oftware wait only) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 156 of 882 rej09b0108-0400 when the wait is specified by software using wcr, the wait input wait signal from outside is sampled. figure 9.5 shows the wait signal sampling. the wait signal is sampled at the clock rise one cycle before the clock rise when the tw state shifts to the t2 state. write data wrxx wait data dack rd csn address ck read t1 tw tw two t2 figure 9.5 wait state timi ng of external space access (two software wait states + wait signal wait state) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 157 of 882 rej09b0108-0400 9.6.3 cs assert period extension idle cycles can be inserted to prevent extension of the rd or wrxx signal assert period beyond the length of the csn signal assert period by setting the sw3 to sw0 bits of bcr2. this allows for flexible interfaces with external circuitry. the timing is shown in figure 9.6. th and tf cycles are added respectively before and after the normal cycle. only csn is asserted in these cycles; rd and wrxx signals are not. further, data is extended up to the tf cycl e, which is effective for gate arrays and the like, which have slower write operations. write data wrxx data rd csn address dack ck read th t1 t2 tf figure 9.6 cs assert period extension function 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 158 of 882 rej09b0108-0400 9.7 waits between access cycles when a read from a slow device is completed, data buffers may not go off in time, causing conflict with the next access data. if there is a data conflict during memory acces s, the problem can be solved by inserting a wait in the access cycle. to enable detection of bus cycle starts, waits can be inserted between access cycles during continuous accesses of the sa me cs space by negating the csn signal once. 9.7.1 prevention of data bus conflicts wait cycles are inserted in the fo llowing cases so that the number of idle cycles specified with the iw31 to iw00 bits are inserted: ? the write cycle to the same cs sp ace continues after the cycle read ? the continuous access is made to the di fferent cs space after the read access if there are idle cycles between the access cycles, th e number of wait cycles is inserted that is obtained by subtracting the existing idle cycles from the number of id le cycles specified. figure 9.7 shows the example of idle cycle insertion. in this example, when one idle cycle insertion is specified between csn space cycles, the specified one idle cycle is inserted when the write access is performed to the csm space immedi ately after the read cycle of the csn space. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 159 of 882 rej09b0108-0400 t1 t2 t1 t2 ck address csn csm rd wrxx data csn space read idle cycles csm space write tidle figure 9.7 example of idle cycle insertion bits iw31 and iw30 in bcr2 specify the number of idle cycles inserted in the case of a write cycle to cs3 and cs7 spaces or a read access to different space after cs3 and cs7 space read. bits iw21 and iw20 specify the number of idle cycles insert ed for cs2 and cs6 spaces, bits iw11 and iw10 specify for cs1 and cs5 spaces, and bits iw01 and iw00 specify for cs0 and cs4 spaces, respectively. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 160 of 882 rej09b0108-0400 9.7.2 simplification of bus cycle start detection for consecutive accesses to the same cs space, wait s are inserted to provid e the number of idle cycles designated by bits cw3 to cw0 in bcr2 . however, in the case of a write cycle after a read, the number of idle cycles inserted will be the larger of the two values designated by the iw and cw bits. when idle cycles already exist between access cycles, waits are not inserted. figure 9.8 shows an example. a continuous access idle is specifi ed for csn space, and csn space is consecutively write-accessed. data csn space access idle cycle csn space access wrxx rd csn address ck t1 t2 tidle t1 t2 figure 9.8 example of idle cycle inse rtion at same space consecutive access 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 161 of 882 rej09b0108-0400 9.8 bus arbitration this lsi has a bus arbitration function that, wh en a bus release request is received from an external device, releases the bus to that device. it also has four internal bus masters, the cpu, dmac, dtc, and aud. the priority for arbitrate the bus mastership betw een these bus masters is: bus request from external device > aud > dtc > dmac > cpu aud does not acquire the bus mastership during dtc or dmac burst transfer; it acquires the bus mastership after dtc or dmac bu rst transfer. aud has the prior ity for the bus mastership to dtc and dmac if the cpu has the bus mastership. dmac, continues operating even if dtc requests the bus mastership during the read or the write period in dmac dual address mode, during burst transfer, or during operation in indirect address transfer mode. a bus request by an external device should be input to the breq pin. when the breq pin is asserted, this lsi releases the bus immediately after executing th e current bus cycle. the signal indicating that the bus has been released is output from the back pin. however, the bus arbitration is not performed at the timing betwee n the read cycle and the write cycle of tas instruction. in addition, bus arbitration is not performed during bus cycle if the access size is greater than the data-bus size, for example, when a long-word access is made for an 8-bit size memory. when an interrupt is generated and the cpu must process this interrupt, the lsi must take back the bus mastership. for this purpose, this lsi has the irqout pin used for the bus mastership request signal. before the lsi takes back the bus mastership, the irqout signal is asserted. when the irqout signal is asserted, the device that a sserted the external bus release request negates the breq signal to release the bus mastership. this allows the bus master ship to return to the cpu, and the lsi processes the interrupt. the irqout pin is asserted when a cause of interrupt is generated and the interrupt request level is higher than the interrupt mask bits (i3 to i0) of the status register (sr). figure 9.9 shows a bus mastership release procedure. 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 162 of 882 rej09b0108-0400 this lsi breq accepted bus mastership release response strobe pin: hi g h-level output external device bus mastership request bus mastership acquisition back confirmation bus mastership release status breq = low back = low address, data, strobe pin: hi g h impedance figure 9.9 bus mastership release procedure 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 163 of 882 rej09b0108-0400 9.9 memory connection example since a21 to a18 function as input ports at power-on reset, take the procedure such as pulling down as required. this lsi csn rd a0 to a14 d0 to d7 ce oe a0 to a14 i/o0 to i/o7 32k 8-bit rom figure 9.10 example of 8-bi t data bus width rom connection 256k 16-bit rom ce oe a0 to 17 i/o0 to 15 csn rd a0 a1 to 18 d0 to 15 this lsi figure 9.11 example of 16-bi t data bus width rom connection 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 164 of 882 rej09b0108-0400 256k 16-bit rom this lsi csn rd a0 a1 a2 to19 d16 to 31 d0 to 15 ce oe a0 to 17 i/o0 to 15 ce oe a0 to 17 i/o0 to 15 figure 9.12 example of 32-bit data bu s width rom connection (only for sh7145) 128k 8-bit sram this lsi ce oe a0 to 16 we i/o0 to 7 csn rd a0 to 16 wrl d0 to 7 figure 9.13 example of 8-bit data bus width sram connection 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 165 of 882 rej09b0108-0400 128k 8-bit sram this lsi csn rd a0 a1 to 17 wrh d8 to 15 wrl d0 to 7 cs oe a0 to16 we i/o0 to 7 cs oe a0 to 16 we i/o0 to 7 figure 9.14 example of 16-bit data bus width sram connection 128k 8-bit sram this lsi csn rd a0 a1 a2 to 18 wrhh d24 to 31 wrhl d16 to 23 wrh d8 to 15 wrl d0 to 7 cs oe a0 to 16 we i/o0 to 7 cs oe a0 to 16 we i/o0 to 7 cs oe a0 to 16 we i/o0 to 7 cs oe a0 to 16 we i/o0 to 7 figure 9.15 example of 32-bit data bu s width sram connection (only for sh7145) 9. bus state controller (bsc) rev.4.00 mar. 27, 2008 page 166 of 882 rej09b0108-0400 9.10 access to on-chip peripheral i/o registers on-chip peripheral i/o re gisters are accessed from the bus state controller as shown in table 9.3. refer to section 25, list of registers, for more details. table 9.3 access to on-chip peripheral i/o registers on-chip peripheral module sci mtu, poe intc pfc, port cmt a/d ubc wdt dmac dtc iic h-udi connection bus width 8 bits 16 bits 16 bits 16 bits 16 bits 8 bits 16 bits 16 bits 16 bits 16 bits 8 bits 16 bits number of access cycles 2 cyc 2 cyc 2 cyc 2 cyc 2 cyc 3 cyc 3 cyc 3 cyc 3 cyc 3 cyc 2 cyc 2 cyc 9.11 cycles of no-bus mastership release the bus mastership is not released during one bus cycle. for example, when the longword read (or write) access is performed to the 8-bit normal space, four memory accesses to the 8-bit normal space are regarded as one bus cycle. in this bus cycle, the bus mast ership is not released. in this case, assuming that one memory access takes two stat es, the bus mastership is not released in eight states. 8 bits 8 bits 8 bits 8 bits cycle in which the bus mastership is not released figure 9.16 one bus cycle 9.12 cpu operation when program is located in external memory in this lsi, two words (two instructions) are fetche d in one instruction fetch. this also applies to the cases where program is located in external memory or the bus width of that external memory is 8 or 16 bits. also, if the program counter value is the odd word (2n+1) address or the program counter value before branch is the even word (2n) address, 32 bits (two instructions) including each word instruction are always fetched. 10. direct memory access controller (dmac) dmash20a_010020020700 rev.4.00 mar. 27, 2008 page 167 of 882 rej09b0108-0400 section 10 direct memory access controller (dmac) this lsi includes an on-chip four-channel dir ect memory access controller (dmac). the dmac can be used in place of the cpu to perform high -speed data transfers among external devices equipped with dack (transfer request acknowledge signal), external memories, memory-mapped external devices, and on-chip peripheral modules (except for the dmac, dtc, bsc, and ubc). using the dmac reduces the burden on the cpu an d increases operating efficiency of the lsi as a whole. 10.1 features ? four channels ? four gbytes of address space in the architecture ? byte, word, or longword selectable data transfer unit ? 16,777,216 transfers, maximum ? address mode ? dual address mode or single address mode can be selected. ? direct access or indirect access can be selected in dual address mode. ? channel function: transfer modes that ca n be set are different for each channel. ? channel 0: single or dual address mode. external requests are accepted. ? channel 1: single or dual address mode. external requests are accepted. ? channel 2: dual address mode only. source address reload function is available. ? channel 3: dual address mode only. direct addres s transfer mode and indirect address transfer mode selectable. ? transfer requests: there are three dmac transf er activation requests, as indicated below. ? external request: from two dreq pins. dreq can be detected either by falling edge or by low level. ? requests from on-chip peripheral modules: transfer requests from on-chip modules such as sci (request made to sci_0 and sci_1) or a/d (request made to a/d 1). ? auto-request: the transfer request is generated automatically within the dmac. ? selectable bus modes: cycle- steal mode or burst mode ? two types of dmac channel priority ranking: fixed priority mode or round robin mode ? cpu can be interrupted when the specified number of data tran sfers are complete. ? module standby mode can be set. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 168 of 882 rej09b0108-0400 figure 10.1 is a block diagram of the dmac. on-chip rom peripheral bus internal bus on-chip ram dreq0 , dreq1 transfer count control sarn dmac module re g ister control activation control request priority control bus interface bus state controller on-chip peripheral module darn dmatcrn chcrn dmaor mtu sci0, sci1 a/d 1 dein external rom external ram external i/o (memory mapped) external i/o (with acknowled g e) dack0, dack1 drak0, drak1 sarn: darn: dmatcrn: chcrn: dmaor: n: dmac source address re g ister dmac destination address re g ister dmac transfer count re g ister dmac channel control re g ister dmac operation re g ister 0, 1, 2, 3 figure 10.1 dmac block diagram 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 169 of 882 rej09b0108-0400 10.2 input/output pins table 10.1 shows the dmac pin configuration. table 10.1 dmac pin configuration channel name sy mbol i/o function 0 dma transfer request dreq0 i dma transfer request input from external device to channel 0 dma transfer request acknowledge dack0 o dma transfer strobe output from channel 0 to external device dreq0 acceptance confirmation drak0 o sampling receive acknowledge output for dma transfer request input from external source 1 dma transfer request dreq1 i dma transfer request input from external device to channel 1 dma transfer request acknowledge dack1 o dma transfer strobe output from channel 1 to external device dreq1 acceptance confirmation drak1 o sampling receive acknowledge output for dma transfer request input from external source 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 170 of 882 rej09b0108-0400 10.3 register descriptions the dmac has the following registers. the dmac has a total of 17 registers. each channel has four control registers. one other control register is shared by all channels. for register address and their states in each opera ting mode, refer to section 25, list of registers. ? dma source address register_0 (sar_0) ? dma destination address register_0 (dar_0) ? dma transfer count re gister_0 (dmatcr_0) ? dma channel control register_0 (chcr_0) ? dma source address register_1 (sar_1) ? dma destination address register_1 (dar_1) ? dma transfer count re gister_1 (dmatcr_1) ? dma channel control register_1 (chcr_1) ? dma source address register_2 (sar_2) ? dma destination address register_2 (dar_2) ? dma transfer count re gister_2 (dmatcr_2) ? dma channel control register_2 (chcr_2) ? dma source address register_3 (sar_3) ? dma destination address register_3 (dar_3) ? dma transfer count re gister_3 (dmatcr_3) ? dma channel control register_3 (chcr_3) ? dma operation register (dmaor) 10.3.1 dma source address regist ers_0 to 3 (sar _0 to sar_3) dma source address registers_0 to 3 (sar_0 to sar_3) are 32-bit readab le/writable registers that specify the source address of a dma transfer. these registers have a count function, and during a dma transfer, they indicate the next so urce address. in single-address mode, sar values are ignored when a device with dack has b een specified as th e transfer source. specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. operation cannot be guaranteed on any other addresses. when this register is accessed in 16 bits, the va lue of another 16 bits that are not accessed is retained. the initial value of sar is undefined. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 171 of 882 rej09b0108-0400 10.3.2 dma destination address registers_0 to 3 (dar_0 to dar_3) dma destination address registers_0 to 3 (dar _0 to dar_3) are 32-bit readable/writable registers that specify the destin ation address of a dma transfer . these registers have a count function, and during a dma transf er, they indicate the next destin ation address. in single-address mode, dar values are ignored when a device with dack has been specified as the transfer destination. specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. operation cannot be guaranteed on any other address. when th is register is accessed in 16 bits, the value of another 16 bits that are not accessed is retained. the initial value of dar is undefined. 10.3.3 dma transfer count registers_0 to 3 (dmatcr_0 to dmatcr_3) dma transfer count regi sters_0 to 3 (dmatcr_0 to dmatcr_ 3) are 32-bit readable/writable registers that specify th e transfer count for each channel (byt e count, word count, or longword count) with lower 24 bits. specifying a h'000001 gives a transfer count of 1, while h'000000 gives the maximum setting, 16,777,2 16 transfers. while dmac is in operation, the number of transfers to be perf ormed is indicated. upper eight bits of this register are read as 0 and the write value should always be 0. when this register is accessed in 16 bits, the value of anot her 16 bits that are no t accessed is retained. the initial value of dmatcr is undefined. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 172 of 882 rej09b0108-0400 10.3.4 dma channel control registers_0 to 3 (chcr_0 to chcr_3) dma channel control registers_0 to 3 (chcr_0 to chcr_3) are 32-bit readable/writable registers where the operation and transmission of each channel is designated. bit bit name initial value r/w description 31 to 21 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 20 di 0 (r/w) * 2 direct/indirect specifies either direct address mode operation or indirect address mode operation for channel 3 source address. this bit is valid only in chcr_3. for chcr_0 to chcr_2, this bit is always read as 0 and the write value should always be 0. 0: direct access mode operation for channel 3 1: indirect access mode operation for channel 3 19 ro 0 (r/w) * 2 source address reload selects whether to reload the source address initial value during channel 2 transfer. this bit is valid only for chcr_2. for chcr_0, chcr_1, and chcr_3, this bit is always read as 0 and the write value should always be 0. 0: does not reload source address 1: reloads source address 18 rl 0 (r/w) * 2 request check level selects whether to output drak notifying external device of dreq received, with active high or active low. this bit is valid only for chcr_0 and chcr_1. for chcr_2 and chcr_3, this bit is always read as 0 and the write value should always be 0. 0: output drak with active high 1: output drak with active low 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 173 of 882 rej09b0108-0400 bit bit name initial value r/w description 17 am 0 (r/w) * 2 acknowledge mode in dual address mode, selects whether to output dack in the data write cycle or data read cycle. in single address mode, dack is always output irrespective of the setting of this bit. this bit is valid only for chcr_0 and chcr_1. for chcr_2 and chcr_3, this bit is always read as 0 and the write value should always be 0. 0: outputs dack during read cycle 1: outputs dack during write cycle 16 al 0 (r/w) * 2 acknowledge level specifies whether to set dack (acknowledge) signal output to active high or active low. this bit is valid only with chcr_0 and chcr_1. for chcr_2 and chcr_3, this bit is always read as 0 and the write value should always be 0. 0: active high output 1: active low output 15 14 dm1 dm0 0 0 r/w r/w destination address mode 1, 0 these bits specify increm ent/decrement of the dma transfer destination address. these bit specifications are ignored when transferring data from an external device to address space in single address mode. 00: destination address fixed 01: destination address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32- bit transfer) 10: destination address decremented (?1 during 8-bit transfer, ?2 during 16-bit transfer, ?4 during 32-bit transfer) 11: setting prohibited 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 174 of 882 rej09b0108-0400 bit bit name initial value r/w description 13 12 sm1 sm0 0 0 r/w r/w source address mode 1, 0 these bits specify increm ent/decrement of the dma transfer source address. thes e bit specifications are ignored when transferring data from an external device to address space in single address mode. 00: source address fixed 01: source address incremented (+1 during 8-bit transfer, +2 during 16-bit transfer, +4 during 32-bit transfer) 10: source address decremented (?1 during 8-bit transfer, ?2 during 16-bit transfer, ?4 during 32- bit transfer) 11: setting prohibited when the transfer source is specified at an indirect address, specify in source address register 3 (sar_3) the actual storage address of the data you want to transfer as the data storage address (indirect address). during indirect address mode, sar_3 obeys the sm1/sm0 setting for increment/decrement. in this case, sar_3?s increment/decrement is fixed at +4/?4 or 0, irrespective of the transfer data size specified by ts1 and ts0. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 175 of 882 rej09b0108-0400 bit bit name initial value r/w description 11 10 9 8 rs3 rs2 rs1 rs0 0 0 0 0 r/w r/w r/w r/w resource select 3, 2, 1, 0 these bits specify the transfer request source. 0000: external request, dual address mode 0001: prohibited 0010: external request, single address mode. external address space external device. 0011: external request, single address mode. external device external address space. 0100: auto-request 0101: prohibited 0110: mtu tgia_0 0111: mtu tgia_1 1000: mtu tgia_2 1001: mtu tgia_3 1010: mtu tgia_4 1011: a/d1 adi1 1100: sci0 txi_0 1101: sci0 rxi_0 1110: sci1 txi_1 1111: sci1 rxi_1 note: external request designations are valid only for channels 0 and 1. no transfer request sources can be set for channels 2 or 3. 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 176 of 882 rej09b0108-0400 bit bit name initial value r/w description 6 ds 0 (r/w) * 2 dreq select sets the sampling method for the dreq pin in external request mode to either low-level detection or falling-edge detection. this bit is valid only with chcr_0 and chcr_1. for chcr_2 and chcr_3, this bit is always read as 0 and the write value should always be 0. even with channels 0 and 1, when specifying an on- chip peripheral module or auto-request as the transfer request source, this bit setting is ignored. the sampling method is fixed at falling-edge detection in cases other than auto-request. 0: low-level detection 1: falling-edge detection 5 tm 0 r/w transfer mode specifies the bus mode for data transfer. 0: cycle steal mode 1: burst mode 4 3 ts1 ts0 0 0 r/w r/w transfer size 1, 0 specify size of data for transfer. 00: specifies byte size (8 bits) 01: specifies word size (16 bits) 10: specifies longword size (32 bits) 11: prohibited 2 ie 0 r/w interrupt enable when this bit is set to 1, interrupt requests are generated after the number of data transfers specified in the dmatcr (when te = 1). 0: interrupt request not generated after dmatcr- specified transfer count 1: interrupt request enabled on completion of dmatcr specified number of transfers 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 177 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 te 0 r/(w) * 1 transfer end flag this bit is set to 1 after the number of data transfers specified by the dmatcr. at th is time, if the ie bit is set to 1, an interrupt request is generated. if data transfer ends before te is set to 1 (for example, due to an nmi or address error, or clearing of the de bit or dme bit of the dmaor) the te is not set to 1. with this bit set to 1, data transfer is disabled even if the de bit is set to 1. 0: dmatcr-specified tran sfer count not ended [clearing condition] 0 write after te = 1 read, power-on reset, software standby mode 1: dmatcr specified number of transfers completed 0 de 0 r/w dmac enable de enables operation in the corresponding channel. 0: operation of the corresponding channel disabled 1: operation of the corresponding channel enabled transfer mode is entered if this bit is set to 1 when auto-request is specified (rs3 to rs0 settings). with an external request or on-chip module request, when a transfer request occurs after this bit is set to 1, transfer is enabled. if this bit is cleared during a data transfer, transfer is suspended. if the de bit has been set, but te = 1, then if the dme bit of the dmaor is 0, and the nmi or ae bit of the dmaor is 1, transfer enable mode is not entered. notes: 1. te bit: allows only 0 write after reading 1. 2. the di, ro, rl, am, al, or ds bit may be absent, depending on the channel. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 178 of 882 rej09b0108-0400 10.3.5 dmac operation register (dmaor) the dmaor is a 16-bit readable/wr itable register that specifies th e transfer mode of the dmac bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 8 pr1 pr0 0 0 r/w r/w priority mode 1 and 0 these bits determine the priority level of channels for execution when transfer requests are made for several channels simultaneously. 00: ch0 > ch1 > ch2 > ch3 01: ch0 > ch2 > ch3 > ch1 10: ch2 > ch0 > ch1 > ch3 11: round robin mode 7 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 ae 0 r/(w) * address error flag indicates that an address error has occurred during dma transfer. if this bit is set during a data transfer, transfers on all channels are suspended. the cpu cannot write a 1 to the ae bit. clearing is effected by 0 write after 1 read. 0: no address error, dma transfer enabled [clearing condition] write ae = 0 after reading ae = 1 1: address error, dma transfer disabled [setting condition] address error due to dmac 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 179 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 nmif 0 r/(w) * nmi flag indicates input of an nmi. this bit is set irrespective of whether the dmac is operating or suspended. if this bit is set during a data transfer, transfers on all channels are suspended. the cpu is unable to write a 1 to the nmif. clearing is effected by a 0 write after 1 read. 0: no nmi interrupt, dma transfer enabled [clearing condition] write nmif = 0 after reading nmif = 1 1: nmi has occurred, dma transfer prohibited [setting condition] nmi interrupt occurrence 0 dme 0 r/w dmac master enable this bit enables activation of the entire dmac. when the dme bit and de bit of the chcr for the corresponding channel are set to 1, that channel is transfer-enabled. if this bit is cleared during a data transfer, transfers on all channels are suspended. 0: disable operation on all channels 1: enable operation on all channels even when the dme bit is set, when the te bit of the chcr is 1, or its de bit is 0, transfer is disabled when nmi of the dmaor = 1 or when ae = 1. note: * only 0 can be written to clear the flag. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 180 of 882 rej09b0108-0400 10.4 operation when there is a dma transfer request, the dmac starts the transfer according to the predetermined channel priority order; when the tr ansfer end conditions are satisfied, it ends the transfer. transfer s can be requested in three modes: auto-request, external request, and on-chip peripheral module request. transfer can be in eith er the single address mo de or the dual address mode, and dual address mode can be either direct or indirect address transfer mode. the bus mode can be either burst or cycle steal. 10.4.1 dma transfer flow after the dma source address registers (sar), dma destination address registers (dar), dma transfer count register (dmatcr), dma channel control registers (chcr), and dma operation register (dmaor) are set to the desired transfer conditions, the dmac transfers data according to the following procedure: 1. the dmac checks to see if transfer is enab led (de = 1, dme = 1, te = 0, nmif = 0, ae = 0). 2. when a transfer request comes and transfer has been enabled, the dmac transfers 1 transfer unit of data (determined by ts0 and ts1 setting). for an auto-request, the transfer begins automatically when the de bit and dme bit are set to 1. the dmatcr value will be decremented by 1 upon each transf er. the actual transfer flows vary by address mode and bus mode. 3. when the specified number of transfers have been completed (when dmatcr reaches 0), the transfer ends normally. if the ie bit of the chcr is set to 1 at this time, a dei interrupt is sent to the cpu. 4. when an address error occurs in the dmac or an nmi interrupt is generated, the transfer is aborted. transfers are also aborted when th e de bit of the chcr or the dme bit of the dmaor are changed to 0. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 181 of 882 rej09b0108-0400 figure 10.2 is a flowchart of this procedure. normal end does nmif = 1, ae = 1, de = 0, or dme = 0? bus mode, transfer request mode, dreq detection selection system initial settin g s (sar, dar, dmatcr, chcr, dmaor) transfer (1 transfer unit); dmatcr ? 1 dmatcr, sar and dar updated dei interrupt request (when ie = 1) no yes no yes no yes yes no yes no * 3 * 2 start transfer aborted notes: 1. 2. 3. in auto-request mode, transfer be g ins when nmif, ae, and te are all 0, and the de and dme bits are set to 1. dreq = level detection in burst mode (external request) or cycle-steal mode. dreq = ed g e detection in burst mode (external request), or auto-request mode in burst mode. dmatcr = 0? transfer request occurs? * 1 de, dme = 1 and nmif, ae, te = 0? does nmif = 1, ae = 1, de = 0, or dme = 0? transfer ends figure 10.2 dmac transfer flowchart 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 182 of 882 rej09b0108-0400 10.4.2 dma transfer requests dma transfer requests are usually generated in either the data tran sfer source or destination, but they can also be generated by devices and on-chip peripheral modules that are neither the source nor the destination. transfers can be requested in three modes: auto-request, external request, and on-chip peripheral module request. the request mode is selected in the rs3 to rs0 bits of the dma channel control registers_0 to 3 (chcr_0 to chcr_3). auto-request mode: when there is no transfer request sign al from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the dmac to automatically generate a transfer request signal internally. when the de bits of chcr_0 to chcr_3 and the dme bit of the dmaor are set to 1, the transfer begins (s o long as the te bits of chcr_0 to chcr_3 and the nmif and ae bits of dmaor are all 0). external request mode: in this mode a transfer is pe rformed at the request signal ( dreq ) of an external device. choose one of the modes shown in table 10.2 according to the application system. when this mode is selected, if the dma transfer is enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), a transfer is performed upon a request at the dreq input. choose to detect dreq by either the falling edge or low level of the signal input with the ds bit of chcr_0 to chcr_3 (ds = 0 is level detection, ds = 1 is edge detection). the source of the transfer request does not have to be the data transfer source or destination. table 10.2 selecting external request modes with rs bits rs3 rs2 rs1 rs0 address mode source destination 0 0 0 0 dual address mode any * any * 0 0 1 0 single address mode external memory or memory-mapped external device external device with dack 0 0 1 1 single address mode external device with dack external memory or memory-mapped external device note: * external memory, memory-mapped external device, on-chip memory, and on-chip peripheral module (excluding dmac, dtc, bsc, ubc). 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 183 of 882 rej09b0108-0400 on-chip peripheral module request mode: in this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. as indicated in table 10.3, there are ten transfer request signals: five from the multifunction timer pulse unit (mtu), which are compare match or input capture interrupts; the receive data full interrupts (rxi) and transmit data empty interrupts (t xi) of the two serial communi cation interfaces (sci); and the a/d conversion end interrupt (adi1) of the a/d converter. when dma transfers are enabled (de = 1, dme = 1, te = 0, nmif = 0, ae = 0), a transfer is performed upon the input of a transfer request signal. the transfer request source need not be the data transfer source or transfer destination. however, when the transfer request is set by rxi (transfe r request because sci?s receive data is full), the transfer source must be the sci?s receive data regi ster (rdr). when the transfer request is set by txi (transfer request because sci?s transmit data is empty), the transfer destination must be the sci?s transmit data register (tdr). also, if the tr ansfer request is set to the a/d converter, the data transfer destination must be the a/d converter register. table 10.3 selecting on-chip peripheral module request modes with rs bits rs3 rs2 rs1 rs0 dmac transfer request source dma transfer request signal source desti- nation bus mode 0 1 1 0 mtu tgia_0 any * any * burst/cycle steal 0 1 1 1 mtu tgia_1 any * any * burst/cycle steal 1 0 0 0 mtu tgia_2 any * any * burst/cycle steal 1 0 0 1 mtu tgia_3 any * any * burst/cycle steal 1 0 1 0 mtu tgia_4 any * any * burst/cycle steal 1 0 1 1 a/d1 adi1 addr1 any * burst/cycle steal 1 1 0 0 sci0 transmit block txi_0 any * tdr0 burst/cycle steal 1 1 0 1 sci0 receiver block rxi_0 rdr0 any * burst/cycle steal 1 1 1 0 sci1 transmit block txi_1 any * tdr1 burst/cycle steal 1 1 1 1 sci1 receiver block rxi_1 rdr1 any * burst/cycle steal notes: mtu: multifunction timer pulse unit. sci0, sci1: serial communications interface channels 0 and 1. addr1: a/d converter?s a/d register. tdr_0, tdr_1: sci_0 and sci _1 transmit data registers. rdr_0, rdr_1: sci_0 and sci_1 receive data registers. * external memory, memory-mapped external device, on-chip memory, and on-chip peripheral module (excluding dmac, dtc, bsc, and ubc). 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 184 of 882 rej09b0108-0400 in order to output a transfer request from an on-chip peripheral module, set the relevant interrupt enable bit for each module, and output an interrupt signal. when an on-chip peripheral module?s interrupt request signal is used as a dma transfer request signal, interrupts for the cpu are not generated. when a dma transfer is conducted corresponding with one of the transfer request signals in table 10.3, it is automatically discontinued. in cycle steal mode this occurs in the first transfer, and in burst mode in the last transfer. 10.4.3 channel priority when the dmac receives simultaneous transfer requ ests on two or more channels, it selects a channel according to a predetermined priority order, either in a fixed mode or in round robin mode. these modes are selected by priority bits pr1 and pr0 in the dma operation register (dmaor). fixed mode: in this mode, the priority levels among the channels remain fixed. the following priority orders are available for fixed mode: ? ch0 > ch1 > ch2 > ch3 ? ch0 > ch2 > ch3 > ch1 ? ch2 > ch0 > ch1 > ch3 these are selected by settings of the pr1 and pr0 bits of the dma operation register (dmaor). round robin mode: in round robin mode, each time the transfer of one transfer un it (byte, word or long word) ends on a given ch annel, that channel receives the lo west priority level (figure 10.3 (1)). the priority level in round robin mode immediately after a reset is ch0 > ch1 > ch2 > ch3. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 185 of 882 rej09b0108-0400 ch1 > ch2 > ch3 > ch0 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch2 > ch3 > ch0 > ch1 ch0 > ch1 > ch2 > ch3 ch0 > ch1 > ch2 > ch3 ch3 > ch0 > ch1 > ch2 ch0 > ch1 > ch2 > ch3 transfer on c hannel 0 initial priority settin g initial priority settin g initial priority settin g initial priority settin g no chan g e in priority. when channel 2 receives the lowest priority, the priorities of channel 0 and 1, which were above channel 2, are also shifted simultaneously. immedi- ately thereafter, if there is a transfer request for channel 1 only, channel 1 is g iven the lowest priority, and the priorities of channels 3 and 0 are simultaneously shifted down. when channel 1 is g iven the lowest priority, the priority of channel 0, which was above channel 1, is also shifted simultaneously. channel 0 is g iven the lowest priority. priority after transfer priority after transfer priority after transfer priority after transfer priority after transfer due to issue of a transfer request for channel 1 only. transfer on c hannel 1 transfer on c hannel 2 transfer on c hannel 3 figure 10.3 (1) round robin mode 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 186 of 882 rej09b0108-0400 figure 10.3 (2) shows the changes in priority levels when transfer requests are issued simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on channel 0. the dmac operates in the fo llowing manner under these circumstances: 1. transfer requests are issued si multaneously for channels 0 and 3. 2. since channel 0 has a higher priority level than channel 3, the channel 0 transfer is conducted first (channel 3 is on transfer standby). 3. a transfer request is issued for channel 1 during a transfer on channel 0 (channels 1 and 3 are on transfer standby). 4. at the end of the channel 0 transfer, channel 0 shifts to the lowest priority level. 5. at this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer comes first (channel 3 is on transfer standby). 6. when the channel 1 transfer ends, channe l 1 shifts to the lowest priority level. 7. channel 3 transfer begins. 8. when the channel 3 transfer ends, channel 3 and channel 2 priority levels are lowered, giving channel 3 the lowest priority. transfer request channel waiting dmac operation channel priority issued for channels 0 and 3 issued for channel 1 0 > 1 > 2 > 3 channel 0 transfer be g ins 1 > 2 > 3 > 0 channel 0 transfer ends channel 1 transfer be g ins channel 3 transfer be g ins 2 > 3 > 0 > 1 channel 1 transfer ends 0 > 1 > 2 > 3 channel 3 transfer ends chan g e of priority chan g e of priority chan g e of priority none 3 3 1,3 figure 10.3 (2) example of change s in priority in round robin mode 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 187 of 882 rej09b0108-0400 10.4.4 dma transfer types the dmac supports the transfers shown in table 10.4. it can operate in the single address mode, in which either the tran sfer source or destination is accessed using an acknowledge signal, or dual access mode, in which both the transfer source an d destination addresses are output. the dual access mode consists of a direct address mode, in wh ich the output address value is the object of a direct data transfer, and an indi rect address mode, in which the output address value is not the object of the data transfer, but th e value stored at the output ad dress becomes the transfer object address. the actual tran sfer operation timing varies with the bus mode. the dmac has two bus modes: cycle-steal mode and burst mode. table 10.4 supported dma transfers destination source external device with dack external memory memory- mapped external device on-chip memory on-chip peripheral module external device with dack not available single single not available not available external memory single dual dual dual dual memory-mapped external device single dual dual dual dual on-chip memory not available dual dual dual dual on-chip peripheral module not available dual dual dual dual note: dual address mode includes both direct address mode and indirect address mode. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 188 of 882 rej09b0108-0400 address modes: ? single address mode in the single address mode, both the transfer source and destination are external; one is accessed by a dack signal while the other is acce ssed by an address. in this mode, the dmac performs the dma transfer in 1 bus cycle by simultaneously outputting a transfer request acknowledge dack signal to one external device to access it while outputting an address to the other end of the tr ansfer. figure 10.4 shows an ex ample of a transfer between an external memory and an external device with da ck in which the external device outputs data to the data bus while that data is written in external memory in the same bus cycle. dmac dack dreq external memory external device with dack this lsi external address bus : data flow external data bus figure 10.4 data flow in single address mode 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 189 of 882 rej09b0108-0400 two types of transfers are possible in the sing le address mode: (a) transfers between external devices with dack and memory-mapped external devices, and (b) transfers between external devices with dack and external memory. the only transfer requests for ei ther of these is the external request ( dreq ). figure 10.5 shows the dma transf er timing for the single address mode. ck a21?a0 csn d15?d0 dack wrh wrl address output to external memory space data that is output from the external device with dack dack si g nal to external devices with dack (active low) wr si g nal to external memory space a. external device with dack to external memory space ck a21?a0 csn d15?d0 rd address output to external memory space data that is output from external memory space rd si g nal to external memory space dack si g nal to external device with dack (active low) dack b. external memory space to external device with dack figure 10.5 example of dma transf er timing in single address mode 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 190 of 882 rej09b0108-0400 dual address mode: dual address mode is used for access of both th e transfer source and de stination by address. transfer source and destination can be accessed eith er internally or externally. dual address mode is subdivided into two other modes: direct address transfer mode and indirect address transfer mode. ? direct address transfer mode data is read from the transfer source during th e data read cycle, and written to the transfer destination during the write cycle, so transfer is conducted in tw o bus cycles. at this time, the transfer data is temporarily st ored in the dmac. with the kind of external memory transfer shown in figure 10.6, data is read from one of the memories by the dmac during a read cycle, then written to the other external memory dur ing the subsequent write cycle. figure 10.7 shows the timing for this operation. data buffer address bus data bus address bus data bus memory transfer source module transfer destination module memory transfer source module transfer destination module sar dar data buffer sar dar the sar value is taken as the address, and data is read from the transfer source module and stored temporarily in the dmac. 1st bus cycle 2nd bus cycle the dar value is taken as the address, and data stored in the dmac's data buffer is written to the transfer destination module. dmac dmac figure 10.6 direct address oper ation during dual address mode 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 191 of 882 rej09b0108-0400 data read cycle data write cycle transfer destination address transfer source address ck (1st cycle) (2nd cycle) a21?a0 csn d15?d0 rd wrh , wrl dack note: transfer between external memories with dack are output durin g read cycle. figure 10.7 example of direct address transfer timing in dual address mode ? indirect address transfer mode in this mode the memory address storing the data you actually want to transfer is specified in dmac internal transfer source ad dress register (sar3). therefore, in indirect address transfer mode, the dmac internal transfer source address register value is read first. this value is stored once in the dmac. next, the read value is output as the address, and the value stored at that address is again stored in the dmac. finally, the subsequent read value is written to the address specified by th e transfer destination address register, ending one cycle of dma transfer. in indirect address mode (figure 10.8), transf er destination, transfer source, and indirect address storage destination are all 16-bit external memory locations, and transfer in this example is conducted in 16-bit or 8-bit units. ti ming for this transfer example is shown in figure 10.9. in indirect address mode, one nop cycle (figure 10.9) is required until the data read as the indirect address is output to the address bus. when transfer data is 32-bit, the third and fourth bus cycles each need to be doubled, giving a required total of six bus cycles and one nop cycle for the whole operation. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 192 of 882 rej09b0108-0400 sar3 dar3 data buffer address bus data bus memory transfer source module transfer destination module temporary buffer the sar3 value is taken as the address, memory data is read, and the value is stored in the temporary buffer. since the value read at this time is used as the address, it must be 32 bits. when external connection data bus is 16 bits, two bus cycles are required. dmac sar3 dar3 data buffer address bus data bus memory transfer source module transfer destination module temporary buffer the value in the temporary buffer is taken as the address, and data is read from the transfer source module to the data buffer. sar3 dar3 data buffer address bus data bus memory transfer source module transfer destination module temporary buffer the dar3 value is taken as the address, and the value in the data buffer is written to the transfer destination module. note: memory, transfer source, and transfer destination modules are shown here. in practice, connection can be made anywhere if there is address space. dmac dmac 1st, 2nd bus cycles 3rd bus cycle 4th bus cycle figure 10.8 dual address mode and indirect address operation (when external memory space is 16 bits) 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 193 of 882 rej09b0108-0400 transfer source address (h) transfer source address (l) indirect address nop transfer destination address indirect address (h) indirect address (l) transfer data transfer data transfer data transfer data transfer data transfer source address ? 1 indirect address ? 2 indirect address nop indirect address address read cycle (1st) (2nd) (3rd) nop cycle data read cycle (4th) data write cycle ck a21?a0 csn d15?d0 internal address bus internal data bus dmac indirect address buffer dmac data buffer rd wrh , wrl notes: 1. 2. the internal address bus is controlled by the port and does not chan g e. dmac does not fetch value until 32-bit data is read from the internal data bus. figure 10.9 dual address mode and i ndirect address transfer timing example (external memory space to external memory space, 16-bit width) 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 194 of 882 rej09b0108-0400 figure 10.10 shows an example of timing in indi rect address mode when transfer source and indirect address storage locations are in internal memory, the tran sfer destination is an on-chip peripheral module with 2-cycle access sp ace, and transfer data is 8-bit. since the indirect address storag e destination and the transfer so urce are in in ternal memory, these can be accessed in one cycle. the transfer destination is 2-cycle access space, so two data write cycles are required. one no p cycle is required until the data read as the indirect address is output to the address bus. internal address bus internal data bus dmac indirect address buffer dmac data buffer ck transfer source address nop nop indirect address transfer destination address indirect address indirect address transfer data transfer data transfer data address read cycle nop cycle data read cycle data write cycle (4th) (1st) (2nd) (3rd) figure 10.10 dual address mode and indirect address transfer timing example (on-chip memory space to on-chip memory space) 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 195 of 882 rej09b0108-0400 bus modes: select the appropriate bus mode in the tm bits of chcr_0 to chcr_3. there are two bus modes: cycle steal and burst. ? cycle-steal mode in the cycle steal mode, the bus mastership is given to another bus master after each one- transfer-unit (byte, word, or longword) dmac tr ansfer. when the next tr ansfer request occurs, the bus mastership are ob tained from the other bus master and a transfer is performed for one transfer unit. when that transf er ends, the bus mastership is passed to the other bus master. this is repeated until the transfer end conditions are satisfied. the cycle steal mode can be used with all categories of transfer de stination, transfer source and transfer request. figure 10.11 shows an exampl e of dma transfer timi ng in the cycle steal mode. transfer conditions are dual address mode and dreq level detection. cpu cpu cpu dmac dmac cpu dmac dmac cpu cpu dreq bus cycle bus control returned to cpu read write write read figure 10.11 dma transfer example in cycle-steal mode ? burst mode once the bus mastership is obtained, the transfer is performed continuously until the transfer end condition is satisfied. in the external re quest mode with low level detection of the dreq pin, however, when the dreq pin is driven high, the bus passes to the other bus master after the bus cycle of the dmac that currently has an acknowledged request ends, even if the transfer end conditions have not been satisfied. figure 10.12 shows an example of dma transfer timing in the burst mode. transfer conditions are single address mode and dreq level detection. cpu cpu cpu dmac dmac dmac dmac dmac dreq bus cycle dmac cpu figure 10.12 dma transfer example in burst mode 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 196 of 882 rej09b0108-0400 relationship between request modes and bus modes by dma transfer category: table 10.5 shows the relationship between request modes and bus modes by dma transfer category. table 10.5 relationship of request mode s and bus modes by dma transfer category address mode transfer category request mode bus mode transfer size (bits) usable channels single external device with dack and external memory external b/c 8/16/32 0, 1 external device with dack and memory-mapped external device external b/c 8/16/32 0, 1 dual external memory and external memory any * 1 b/c 8/16/32 0 to 3 * 5 external memory and memory-mapped external device any * 1 b/c 8/16/32 0 to 3 * 5 memory-mapped external device and memory-mapped external device any * 1 b/c 8/16/32 0 to 3 * 5 external memory and on-chip memory any * 1 b/c 8/16/32 0 to 3 * 5 external memory and on-chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0 to 3 * 5 memory-mapped external device and on-chip memory any * 1 b/c 8/16/32 0 to 3 * 5 memory-mapped external device and on- chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0 to 3 * 5 on-chip memory and on-chip memory any * 1 b/c 8/16/32 0 to 3 * 5 on-chip memory and on-chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0 to 3 * 5 on-chip peripheral module and on- chip peripheral module any * 2 b/c * 3 8/16/32 * 4 0 to 3 * 5 b: burst c: cycle steal notes: 1. external request, auto-request or on- chip peripheral module request enabled. however, in the case of on-chip peripheral module requ est, it is not possible to specify the sci or a/d converter for the transfer request source. 2. external request, auto-request or on-chip peripheral module request possible. however, if transfer request source is also the sci or a/d converter, the transfer source or transfer destination must be the sci or a/d converter. 3. when the transfer request source is the sci, only cycle steal mode is possible. 4. access size permitted by register of on- chip peripheral module that is the transfer source or transfer destination. 5. when the transfer request is an external request, channels 0 and 1 only can be used. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 197 of 882 rej09b0108-0400 bus mode and channel priority: when a given channel is transferring in burst mode , and a transfer request is issued to channel 0, which has a higher priority ranking, transfer on channel 0 begins immediately. if the priority level setting is fixed mode (ch0 > ch1), channel 1 transfer is continued after transfer on channel 0 are completely ended, whether the channel 0 setting is cycle steal mode or burst mode. when the priority level setting is for round robin mo de, transfer on channel 1 begins after transfer of one transfer unit on channel 0, whether channel 0 is set to cycle steal mode or burst mode. thereafter, bus master ship alternates in the order: channel 1 channel 0 channel 1 channel 0. whether the priority level setting is for fixed mode or round robin mode, since channel 1 is set to burst mode, the bus mastership is not given to the cpu. an example of round robin mode is shown in figure 10.13. cpu dmac ch1 dmac ch1 dmac ch0 dmac ch1 dmac ch0 dmac ch1 dmac ch1 cpu ch0 ch1 ch0 dmac ch0 and ch1 round-robin mode dmac ch1 burst mode cpu cpu priority: round-robin mode ch0: cycle-steal mode ch1: burst mode dmac ch1 burst mode figure 10.13 bus handling when multiple channels are operating 10.4.5 number of bus cycle states and dreq pin sample timing number of states in bus cycle: the number of states in the bus cycle when the dmac is the bus master is controlled by the bus state controlle r (bsc) just as it is when the cpu is the bus master. for details, see section 9, bus state controller (bsc). dreq pin sampling timing and drak signal: in external request mode, the dreq pin is sampled by either falling edge or low-level detection. when a dreq input is detected, a dmac bus cycle is issued and dma transfer effected, at the earliest, after three states. however, in burst mode when single address operation is specified, a dummy cycle is inserted for the first bus cycle. in this case, the actual data transfer starts from the second bus cycle. data is transferred continuously from the second bus cycle. the dummy cycle is not counted in the number of transfer cycles, so th ere is no need to recognize the du mmy cycle when setting the tcr. dreq sampling from the second time begins from the start of the transfer one bus cycle prior to the dmac transfer generated by the previous sampling. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 198 of 882 rej09b0108-0400 drak is output once for the first dreq sampling, irrespective of transfer mode or dreq detection method. in burst mode, using edge detection, dreq is sampled for the first cycle only, so drak is also output for the first cycle only. therefore, the dreq signal negate timing can be ascertained, and this facilitates handshake opera tions of transfer requests with the dmac. cycle steal mode operations: in cycle steal mode, dreq sampling timing is the same irrespective of dual or single address mode, or whether edge or low-level dreq detection is used. for example, dmac transfer begins (figure 10.1 4), at the earliest, thr ee cycles from the first sampling timing. the second sampling begins at the start of the tran sfer one bus cycle prior to the start of the dmac transf er initiated by the first sampling (i.e., from the start of the cpu(3) transfer). at this point, if dreq detection has not occurred, sampling is executed every cycle thereafter. as in figure 10.15, whatever cy cle the cpu transfer cycle is, th e next sampling begins from the start of the transfer on e bus cycle before the dmac transfer begins. figure 10.14 shows an example of output during dack read and figure 10.15 an example of output during dack write. figures 10.16 and 10.17 show cycle steal mode an d single address mode. in this case, transfer begins at earliest three cycles after the first dreq sampling. the second sampling begins from the start of the transfer one bus cycle before the start of the firs t dmac transfer. in single address mode, the dack signal is output during the dmac transfer period. burst mode, dual addres s, and level detection: figures 10.18 and 10.19 show the dreq sampling timing in burst mode with dual address and level detection. dreq sampling timing in this mode is virtually the same as that of cycle steal mode. for example, dmac transfer begins (figure 10.18), at the earliest, three cycles after the timing of the first sampling. the second sampling also begins from the start of the transfer one bus cycle before the start of the first dmac transfer. in burst mode, as long as transfer requests are issued, dmac transfer continues. theref ore, the ?transfer one bus cycle before the start of the dmac transfer? may be a dmac transfer. in burst mode, the dack output period is the same as that of cycle steal mode. burst mode, single address, and level detection: dreq sampling timing in burst mode with single address and level detection is shown in figures 10.20 and 10.21. in burst mode with single address and level detecti on, a dummy cycle is inse rted as one bus cycle, at the earliest, three cycles after timing of the first sampling. data during this period is undefined, 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 199 of 882 rej09b0108-0400 and the dack signal is not output. nor is th e number of dmac tran sfers counted. the actual dmac transfer begins after one dummy bus cycle output. the dummy cycle is not counted e ither at the start of the second sampling (transfer one bus cycle before the start of the first dmac transfer). therefore, the second sampling is not conducted from the bus cycle starting th e dummy cycle, but from the star t of the cpu(3) bus cycle. thereafter, as long the dreq is continuously sampled, no dummy cycle is inserted. dreq sampling timing during this period begins from the start of the transfer one bus cycle before the start of dmac transfer, in the sa me way as with cycle steal mode. as with the fourth sampling in figure 10.20, onc e dmac transfer is interrupted, a dummy cycle is again inserted at the start as soon as dmac transfer is resumed. the dack output period in burst mode is the same as in cycle steal mode. burst mode, dual addres s, and edge detection: in burst mode with dual address and edge detection, dreq sampling is conducted only on the first cycle. in figure 10.22, dmac transfer begins, at the ear liest, three cycles after the timing of the first sampling. thereafter, dmac transf er continues until the end of the data transfer count set in the dmatcr. dreq sampling is not conducted during this period. therefore, drak is output on the first cycle only. when dmac transfer is resumed after being halted by an nmi or address error, be sure to reinput an edge request. the remaining transfer restarts after the first drak output. the dack output period in burst mode is the same as in cycle steal mode. burst mode, single address, and edge detection: in burst mode with single address and edge detection, dreq sampling is conducted only on the first cycle. in figure 10.23, a dummy cycle is inserted, at the earliest, three cycles after the timing for the first sampling. during this period, data is undefined, and dack is not output. nor is the number of dmac transfers counted. thereafter, dmac transfer continues until the data tran sfer count set in the dmatcr has ended. dreq sampling is not conducted during this period. therefore, drak is output on the first cycle only. when dmac transfer is resumed after being halted by an nmi or address error, be sure to reinput an edge request. drak is output once, and the remaining transfer restarts after output of one dummy cycle. the dack output period in burst mode is the same as in cycle steal mode. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 200 of 882 rej09b0108-0400 ck dreq drak bus cycle dack cpu(3) cpu(4) cpu(5) cpu(2) cpu(1) 1st samplin g 2nd samplin g dmac(r) dmac(r) dmac(w) dmac(w) dmac(w) dmac(r) figure 10.14 cycle steal, dual address and level detection (fastest operation) ck dreq drak bus cycle dack cpu cpu cpu cpu dmac(r) dmac (r) dmac(w) 1st samplin g 2nd samplin g figure 10.15 cycle steal, dual address and level detection (normal operation) note: with cycle-steal and dual address operation, sampling timing is the same regardless of whether dreq detection is by level or by edge. ck dreq drak bus cycle dack cpu cpu cpu cpu cpu dmac dmac dmac figure 10.16 cycle steal, single addre ss and level detection (fastest operation) ck dreq drak bus cycle dack cpu cpu dmac cpu dmac cpu cpu figure 10.17 cycle steal, single addr ess and level detection (normal operation) 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 201 of 882 rej09b0108-0400 note: with cycle steal and single address operation, sampling tim ing is the same regardless of whether dreq detection is by level or by edge. ck dreq drak bus cycle dack cpu cpu cpu cpu dmac(r) dmac(w) dmac(r) dmac(r) dmac(w) dmac(r) dmac(w) figure 10.18 burst mode, dual address and level detection (fastest operation) ck dreq drak bus cycle dack cpu cpu dmac(r) dmac(r) dmac(r) cpu dmac(w) dmac(w) figure 10.19 burst mode, dual addres s and level detection (normal operation) ck d req drak bus cycle dack cpu(4) cpu(1) cpu(2) cpu(3) dummy dmac dummy 2nd samplin g 1st samplin g 3rd samplin g 4th samplin g dmac dmac figure 10.20 burst mode, si ngle address and level det ection (fastest operation) 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 202 of 882 rej09b0108-0400 ck dreq drak bus cycle dack cpu cpu dummy dmac cpu dmac dmac figure 10.21 burst mode, single address and level de tection (normal operation) ck dreq drak bus cycle dack cpu cpu cpu dmac(r) dmac(r) dmac(r) dmac(r) dmac(w) dmac(w) dmac(w) dmac(w) figure 10.22 burst mode, dual address and edge detection ck dreq drak bus cycle dack cpu dmac dmac dmac dmac cpu cpu dummy figure 10.23 burst mode, sing le address and edge detection 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 203 of 882 rej09b0108-0400 10.4.6 source address reload function channel 2 has a source address reload function. th is returns to the first value set in the source address register (sar_2) every fo ur transfers by setting the ro bit of chcr_2 to 1. figure 10.24 illustrates this operation. figure 10.25 is a timing chart for reload on mode, with burst mode, autorequest, 16-bit transfer data size, sar_2 increment, and dar_2 fixed mode. sar_2 (initial value) dmac transfer request dmac control block reload control 4th count chcr_2 dmatcr_2 sar_2 ro bit = 1 count si g nal reload si g nal reload si g nal address bus figure 10.24 source address reload function ck internal address bus internal data bus sar2 dar2 dar2 dar2 dar2 sar2+2 sar2+4 sar2+6 sar2 dar2 sar2 data sar2+2 data sar2+4 data sar2+6 data sar2 data 1st channel 2 transfer 2nd channel 2 transfer 3rd channel 2 transfer 4th channel 2 transfer 5th channel 2 transfer sar2 output dar2 output sar2+2 output dar2 output sar2+4 output dar2 output sar2+6 output dar2 output sar2 output dar2 output after sar2+6 output, sar2 is reloaded bus mastership is returned one time in four figure 10.25 source address reload function timing chart 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 204 of 882 rej09b0108-0400 the reload function can be executed whether the transfer data size is 8, 16, or 32 bits. dmatcr_2, which specifies the numb er of transfers, is decremen ted by 1 at the end of every single-transfer-unit transfer, regardless of whether the reload function is on or off. therefore, when using the reload function in the on state, a multiple of 4 must be specified in dmatcr_2. operation will not be guaranteed if any other value is set. also, the counter which counts the occurrence of four transf ers for address reloading is reset by clearing of the dme bit in dmaor or the de bit in chcr_2, setting of the transfer end flag (the te bit in chcr_2), nmi input, and setting of the ae flag (address error generation in dmac transfer), as we ll as by a reset and in software standby mode, but sar_2, dar_2, dmatcr_2, and other registers are not reset. consequently, when one of these sources occurs, there is a mixture of initialized counters and uninitialized registers in the dmac, and incorrect operation may result if a restart is executed in this state. therefore, when one of the above sources, other than te setting, occurs during use of the address reload function, sar_2, dar_2, and dmatcr_2 settings must be carried out before re-execution. 10.4.7 dma transfer ending conditions the dma transfer ending conditions vary for individual channels ending and for all channels ending together. individual channel ending conditions: there are two ending conditions. a transfer ends when the value of the channel?s dma transfer count register (dmatcr) is 0, or when the de bit of the channel?s chcr is cleared to 0. ? when dmatcr is 0: when the dmatcr value becomes 0 and the corresponding channel's dma transfer ends, the transfer end flag bit ( te) is set in the chcr. if the ie (interrupt enable) bit has been set, a dmac interrupt (dei) is requested of the cpu. ? when de of chcr is 0: software can halt a dma transfer by clearing the de bit in the channel?s chcr. the te bit is not set when this happens. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 205 of 882 rej09b0108-0400 conditions for ending all channels simultaneously: transfers on all channels end when the nmif (nmi flag) bit or ae (address error flag) bit is set to 1 in the dmaor, or when the dme bit in the dmaor is cleared to 0. ? when the nmif or ae bit is set to 1 in dmaor: when an nmi interrupt or dmac address error occurs, the nmif or ae bit is set to 1 in the dmaor and all channels stop their transfers. the dmac ob tains the bus mastership, and if these flags are set to 1 during execution of a transfer, dmac ha lts operation when the transfer processing currently being executed ends, and transfers the bu s mastership to the other bus master. consequently, even if the nmif or ae bits are set to 1 during a transfer, the dma source address register (sar), designation address register (dar), and transfer count register (tcr) are all updated. the te bit is not set. to resume the tr ansfers after nmi interrupt or ad dress error processing, clear the appropriate flag bit to 0. to avoid restarting a tr ansfer on a particular channel, clear its de bit to 0. transfer is halted when the processing of a on e unit transfer is comple te. in a dual address mode direct address transfer, even if an address error occurs or the nmi flag is set during read processing, the transfer will not be halted until after completion of the following write processing. in such a case, sar, dar, and tcr values are updated. in the same manner, the transfer is not halted in dual address mode indi rect address transfers until after the final write processing has ended. ? when dme is cleared to 0 in dmaor: clearing the dme bit to 0 in the dmaor aborts the transfers on all channels. the te bit is not set. 10.4.8 dmac access from cpu the space addressed by the dmac is 3-cycle sp ace. therefore, when the cpu becomes the bus master and accesses the dmac, a mi nimum of three system clock ( ) cycles are required for one bus cycle. also, since the dmac is located in word space, while a word -size access to the dmac is completed in one bus cycle, a longword-si ze access is automatically divided into two word accesses, requiring two bus cycles (six basic cloc k cycles). these two bu s cycles are executed consecutively; a different bus cycle is never inse rted between the two word accesses. this applies to both write accesses and read accesses. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 206 of 882 rej09b0108-0400 10.5 examples of use 10.5.1 example of dma transfer betw een on-chip sci and external memory in this example, on-chip seri al communication interface channe l 0 (sci0) received data is transferred to external memory using the dmac channel 3. table 10.6 indicates the transf er conditions and the setting values of each of the registers. table 10.6 transfer conditions and register set values for transfer between on-chip sci and external memory transfer conditions register value transfer source: rdr0 of on-chip sci0 sar_3 h'ffff81a5 transfer destination: external memory dar_3 h'00400000 transfer count: 64 times dmatcr_3 h'00000040 transfer source address: fixed chcr_3 h'00004d05 transfer destination address: incremented transfer request source: sci0 (rdr0) bus mode: cycle steal transfer unit: byte interrupt request generation at end of transfer channel priority ranking: 0 > 1 > 2 > 3 dmaor h'0001 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 207 of 882 rej09b0108-0400 10.5.2 example of dma transfer between external ram and external device with dack below is an transfer example in which the transfer source is an external memory and the transfer destination is an external device with dack, using channel 1 of the dmac which requires an external request in single address mode. table 10.7 indicates the transf er conditions and the setting values of each of the registers. table 10.7 transfer conditions and register set values for transfer between external ram and external device with dack transfer conditions register value transfer source: external ram sar_1 h'00400000 transfer destination: external device with dack dar_1 (access by dack) transfer count: 32 times dmatcr_1 h'00000020 transfer source address: decremented chcr_1 h'00002269 transfer destination address: (setting ineffective) transfer request source: external pin ( dreq1 ) edge detection bus mode: burst transfer unit: word no interrupt request generation at end of transfer channel priority ranking: 2 > 0 > 1 > 3 dmaor h'0201 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 208 of 882 rej09b0108-0400 10.5.3 example of dma transfer between a/d converter and on-c hip memory (address reload on) in this example, the on-chip a/d converter channel 0 is the transf er source and on-chip memory is the transfer destination, and the address reload function is on. table 10.8 indicates the transf er conditions and the setting values of each of the registers. table 10.8 transfer conditions and regi ster set values for transfer between a/d converter (a/d1) and on-chip memory transfer conditions register value transfer source: on-chip a/d converter (a/d1) sar_2 h'ffff8428 transfer destination: on-chip memory dar_2 h'fffff000 transfer count: 128 times (reload co unt 32 times) dmatcr_2 h'00000080 transfer source address: incremented chcr_2 h'00085b25 transfer destination address: incremented transfer request source: a/d converter (a/d 1) bus mode: burst transfer unit: byte interrupt request generation at end of transfer channel priority ranking: 0 > 2 > 3 > 1 dmaor h'0101 when address reload is on, the sar value returns to its initially established value every four transfers. in the above example, when a transfer request is inpu t from the a/d converter (a/d1), the byte size data is first read from the h'ffff 8482 register of the a/d converter (ad1) and that data is written to the on-chip memory address h'fffff000. because a byte size transfer was performed, the sar and dar values at this poi nt are h'ffff8429 and h'fffff001, respectively. also, because this is a burst tr ansfer, the bus master ship remain secured, so continuous data transfer is possible. when four transfers are completed, if the address reload is off, execution continues with the fifth and sixth transfers and the sar value continues to increment from h'ffff842b to h'ffff842c to h'ffff842d and so on. however, when the address reload is on, the dmac transfer is halted upon completion of the fourth one and the bus mast ership request signal to the cpu is cleared. at this time, the value stored in sar is not h'ffff842b to h'ffff842c, but h'ffff842b to h'ffff8428, a return to the initially established address. the dar value always continues to be incremented regardless of whether th e address reload is on or off. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 209 of 882 rej09b0108-0400 the dmac internal status, due to the above opera tion after completion of th e fourth transfer, is indicated in table 10.9 for bot h address reload on and off. table 10.9 dmac internal status item address reload on address reload off sar h'ffff8428 h'ffff842c dar h'fffff004 h'fffff004 dmatcr h'0000007c h'0000007c bus mastership rele ased maintained dmac operation halted processing continues interrupts not issu ed not issued transfer request source flag clear executed not executed notes: 1. interrupts are executed until the dmat cr value becomes 0, and if the ie bit of the chcr is set to 1, are issued regardless of whether the address reload is on or off. 2. if transfer request source flag clears are executed until the dmat cr value becomes 0, they are executed regardless of whet her the address reload is on or off. 3. designate burst mode when using the addr ess reload function. there are cases where abnormal operation will result if it is executed in cycle steal mode. 4. designate a multiple of four for t he dmatcr value when using the address reload function. there are cases where abnormal ope ration will result if anything else is designated. to execute transfers after the fifth one when the address reload is on, make the transfer request source issue another transfer request signal. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 210 of 882 rej09b0108-0400 10.5.4 example of dma transfer between ex ternal memory and sci1 transmit side (indirect address on) in this example, dmac channel 3 is used, an indi rect address designated external memory is the transfer source and the sci1 transmit side is the transfer destination. table 10.10 indicates the transfer conditions an d the setting values of each of the registers. table 10.10 transfer conditions and register set values for transfer between external memory and sci1 transmit side transfer conditions register value transfer source: external memory sar_3 h'00400000 value stored in address h'00400000 ? h'00450000 value stored in address h'00450000 ? h'55 transfer destination: on-chip sci1 (tdr1) dar_3 h'ffff81b3 transfer count: 10 times dmatcr_3 h'0000000a transfer source address: incremented chcr_3 h'00011e01 transfer destination address: fixed transfer request source: sci1 (tdr1) bus mode: cycle steal transfer unit: byte interrupt request not generated at end of transfer channel priority ranking: 0 > 1 > 2 > 3 dmaor h'0001 when indirect address mode is on, the data stored in the address established in sar is not used as the transfer source data. in the case of indirect addressing, the value stored in the sar address is read, then that value is used as the address and the data read from that address is used as the transfer source data, then that data is st ored in the address designated by the dar. in the table 10.10 example, when a transfer request from the tdr_1 of sci_1 is generated, a read of the address located at h'004000 00, which is the value set in sar_3, is performed first. the data h'00450000 is stored at this h'00400000 address, and the dmac first reads this h'00450000 value. it then uses this read va lue of h'00450000 as an address and reads the value of h'55 that is stored in the h'00450000 address. it then writes the value h'55 to the address h'ffff81b3 designated by dar_3 to complete one indirect address transfer. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 211 of 882 rej09b0108-0400 with indirect addressing, the fi rst executed data read from th e address established in sar_3 always results in a longword size transfer regardless of the ts0, ts1 bit designations for transfer data size. however, the transfer source address fixed and increment or decrement designations are as according to the sm0, sm1 bits. consequently, despite the fact that the transfer data size designation is byte in this example, the sar_3 value at the end of one transfer is h'00400004. the write operation is exactly the same as an or dinary dual address transfer write operation. 10.6 usage notes 1. the dma operation register (dmaor) can be accessed only in word (16-bit) units. the other registers can be accessed in word (16- bit) or longword (32-bit) units. 2. when rewriting the rs0 to rs3 bits of chcr_0 to chcr_3, first clear the de bit to 0 (set the de bit to 0 before doing rewrites with chcr). 3. when an nmi interrupt is input, the nmif bit of the dmaor is set even when the dmac is not operating. 4. set the dme bit of the dmaor to 0 and ma ke certain that any dm ac received transfer request processing has been completed before entering standby mode. 5. do not access the dmac, dtc, bsc, or ub c on-chip peripheral mo dules from the dmac. 6. when activating the dmac, do the chcr or dmaor setting as the final step. there are instances where abnormal operation will result if any other registers are established last. 7. after the dmatcr count becomes 0 and the dma transfer ends normally, always write a 0 to the dmatcr, even when executing the maximum number of transfers on the same channel. there are instances where ab normal operation will result if this is not done. 8. designate burst mode as the transfer mode when using th e address reload function. there are instances where abnormal operation will result in cycle steal mode. 9. designate a multiple of four for the dmatcr value when using the address reload function. there are instances where abnorm al operation will result if anything else is designated. 10. when detecting external requests by falling edge, maintain the external request pin at high level when performing the dmac establishment. 11. when operating in single address mode, establis h an external address as the address. there are instances where abnormal operation will result if an internal address is established. 12. do not access dmac register empty addr esses (h'ffff86b2 to h' ffff86bf). operation cannot be guaranteed when em pty addresses are accessed. 10. direct memory access controller (dmac) rev.4.00 mar. 27, 2008 page 212 of 882 rej09b0108-0400 11. multi-function timer pulse unit (mtu) timmtu1a_020020030800 rev.4.00 mar. 27, 2008 page 213 of 882 rej09b0108-0400 section 11 multi-func tion timer pulse unit (mtu) this lsi has an on-chip multi-function timer pulse unit (mtu) that comprises five 16-bit timer channels. the block diagram is shown in figure 11.1. 11.1 features ? maximum 16-pulse input/output ? selection of 8 counter input clocks for each channel ? the following operations can be set for each channel: ? waveform output at compare match ? input capture function ? counter clear operation ? multiple timer counters (tcnt) can be written to simultaneously ? simultaneous clearing by compare match and input capture is possible ? register simultaneous input/output is possible by synchronous counter operation ? a maximum 12-phase pwm output is possible in combination with synchronous operation ? buffer operation se ttable for channels 0, 3, and 4 ? phase counting mode settable independently for each of channels 1 and 2 ? cascade connection operation ? fast access via internal 16-bit bus ? 23 interrupt sources ? automatic transfer of register data ? a/d converter conversion start trigger can be generated ? module standby mode can be settable ? a total of six-phase waveform output, which includes complementary pwm output, and positive and negative phases of reset pwm output by interlocking operation of channels 3 and 4, is possible. ? ac synchronous motor (brushless dc motor) drive mode using complementary pwm output and reset pwm output is settable by interlocking operation of channels 0, 3, and 4, and the selection of two types of waveform outputs (chopping and level) is possible. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 214 of 882 rej09b0108-0400 table 11.1 mtu functions item channel 0 channel 1 ch annel 2 channel 3 channel 4 count clock p /1 p /4 p /16 p /64 tclka tclkb tclkc tclkd p /1 p /4 p /16 p /64 p /256 tclka tclkb p /1 p /4 p /16 p /64 p /1024 tclka tclkb tclkc p /1 p /4 p /16 p /64 p /256 p /1024 tclka tclkb p /1 p /4 p /16 p /64 p /256 p /1024 tclka tclkb general registers tgra_0 tgrb_0 tgra_1 tgrb_1 tgra_2 tgrb_2 tgra_3 tgrb_3 tgra_4 tgrb_4 general registers/ buffer registers tgrc_0 tgrd_0 ? ? tgrc_3 tgrd_3 tgrc_4 tgrd_4 i/o pins tioc0a tioc0b tioc0c tioc0d tioc1a tioc1b tioc2a tioc2b tioc3a tioc3b tioc3c tioc3d tioc4a tioc4b tioc4c tioc4d counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture 0 output 1 output compare match output toggle output input capture function synchronous operation pwm mode 1 pwm mode 2 ? ? complementary pwm mode ? ? ? reset pmw mode ? ? ? ac synchronous motor drive mode ? ? phase counting mode ? ? ? 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 215 of 882 rej09b0108-0400 item channel 0 channel 1 ch annel 2 channel 3 channel 4 buffer operation ? ? dmac activation tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture tgra_3 compare match or input capture tgra_4 compare match or input capture dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture and tcnt overflow or underflow a/d converter start trigger tgra_0 compare match or input capture tgra_1 compare match or input capture tgra_2 compare match or input capture tgra_3 compare match or input capture tgra_4 compare match or input capture interrupt sources 5 sources ? compare match or input capture 0a ? compare match or input capture 0b ? compare match or input capture 0c ? compare match or input capture 0d ? overflow 4 sources ? compare match or input capture 1a ? compare match or input capture 1b ? overflow ? underflow 4 sources ? compare match or input capture 2a ? compare match or input capture 2b ? overflow ? underflow 5 sources ? compare match or input capture 3a ? compare match or input capture 3b ? compare match or input capture 3c ? compare match or input capture 3d ? overflow 5 sources ? compare match or input capture 4a ? compare match or input capture 4b ? compare match or input capture 4c ? compare match or input capture 4d ? overflow or underflow [legend] : possible ?: not possible 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 216 of 882 rej09b0108-0400 internal data bus a/d converter conversion start si g nal tcnt tgra tgrb tgrc tgrd tcr tiorh tier tmdr tiorl tsr channel 3 tcnt tgra tgrb tgrc tgrd tmdr tiorl tsr tcr tiorh tier channel 4 tcnts tcdr tcbr tddr toer tocr tgcr bus i/f common tcnt tgra tgrb tmdr tsr tcr tior tier tsyr tstr channel 2 tcnt tgra tgrb tmdr tsr tcr tior tier channel 1 tcnt tgra tgrb tgrc tgrd tmdr tiorl tsr tcr tiorh tier channel 0 control lo g ic module data bus control lo g ic for channel 0 to 2 control lo g ic for channels 3 and 4 [le g end] tstr: tsyr: tcr: tmdr: tior (h, l): timer start re g ister timer synchro re g ister timer control re g ister timer mode re g ister timer i/o control re g isters (h, l) tier: tsr: tcnt: tgr (a, b, c, d): timer interrupt enable re g ister timer status re g ister timer counter timer g eneral re g isters (a, b, c, d) interrupt request si g nals channel 3: channel 4: tgia_3 tgib_3 tgic_3 tgid_3 tciv_3 tgia_4 tgib_4 tgic_4 tgid_4 tciv_4 interrupt request si g nals channel 0: channel 1: channel 2: tgia_0 tgib_0 tgic_0 tgid_0 tciv_0 tgia_1 tgib_1 tciv_1 tciu_1 tgia_2 tgib_2 tciv_2 tciu_2 tioc0a tioc0b tioc0c tioc0d tioc1a tioc1b tioc2a tioc2b input/output pins channel 0: channel 1: channel 2: p /1 p /4 p /16 p /64 p /256 p /1024 tclka tclkb tclkc tclkd clock input internal clock: external clock: tioc3a tioc3b tioc3c tioc3d tioc4a tioc4b tioc4c tioc4d input/output pins channel 3: channel 4: figure 11.1 block diagram of mtu 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 217 of 882 rej09b0108-0400 11.2 input/output pins table 11.2 pin configuration channel symbol i/o function common tclka input external clock a input pin (channel 1 phase counting mode a phase input) tclkb input external clock b input pin (channel 1 phase counting mode b phase input) tclkc input external clock c input pin (channel 2 phase counting mode a phase input) tclkd input external clock d input pin (channel 2 phase counting mode b phase input) 0 tioc0a i/o tgra_0 input capture inpu t/output compare output/pwm output pin tioc0b i/o tgrb_0 input capture inpu t/output compare output/pwm output pin tioc0c i/o tgrc_0 input capture inpu t/output compare output/pwm output pin tioc0d i/o tgrd_0 input capture inpu t/output compare output/pwm output pin 1 tioc1a i/o tgra_1 input capture inpu t/output compare output/pwm output pin tioc1b i/o tgrb_1 input capture inpu t/output compare output/pwm output pin 2 tioc2a i/o tgra_2 input capture inpu t/output compare output/pwm output pin tioc2b i/o tgrb_2 input capture inpu t/output compare output/pwm output pin 3 tioc3a i/o tgra_3 input capture inpu t/output compare output/pwm output pin tioc3b i/o tgrb_3 input capture inpu t/output compare output/pwm output pin tioc3c i/o tgrc_3 input capture inpu t/output compare output/pwm output pin tioc3d i/o tgrd_3 input capture inpu t/output compare output/pwm output pin 4 tioc4a i/o tgra_4 input capture inpu t/output compare output/pwm output pin tioc4b i/o tgrb_4 input capture inpu t/output compare output/pwm output pin tioc4c i/o tgrc_4 input capture inpu t/output compare output/pwm output pin tioc4d i/o tgrd_4 input capture inpu t/output compare output/pwm output pin 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 218 of 882 rej09b0108-0400 11.3 register descriptions the mtu has the following registers. for details on register addresses and register states during each process, refer to section 25, list of registers. to distinguis h registers in each channel, an underscore and the channel number are added as a suffix to the register name; tcr for channel 0 is expressed as tcr_0. ? timer control register_0 (tcr_0) ? timer mode register_0 (tmdr_0) ? timer i/o control register h_0 (tiorh_0) ? timer i/o control register l_0 (tiorl_0) ? timer interrupt enable register_0 (tier_0) ? timer status register_0 (tsr_0) ? timer counter_0 (tcnt_0) ? timer general register a_0 (tgra_0) ? timer general register b_0 (tgrb_0) ? timer general register c_0 (tgrc_0) ? timer general register d_0 (tgrd_0) ? timer control register_1 (tcr_1) ? timer mode register_1 (tmdr_1) ? timer i/o control register _1 (tior_1) ? timer interrupt enable register_1 (tier_1) ? timer status register_1 (tsr_1) ? timer counter_1 (tcnt_1) ? timer general register a_1 (tgra_1) ? timer general register b_1 (tgrb_1) ? timer control register_2 (tcr_2) ? timer mode register_2 (tmdr_2) ? timer i/o control register_2 (tior_2) ? timer interrupt enable register_2 (tier_2) ? timer status register_2 (tsr_2) ? timer counter_2 (tcnt_2) ? timer general register a_2 (tgra_2) ? timer general register b_2 (tgrb_2) ? timer control register_3 (tcr_3) ? timer mode register_3 (tmdr_3) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 219 of 882 rej09b0108-0400 ? timer i/o control register h_3 (tiorh_3) ? timer i/o control register l_3 (tiorl_3) ? timer interrupt enable register_3 (tier_3) ? timer status register_3 (tsr_3) ? timer counter_3 (tcnt_3) ? timer general register a_3 (tgra_3) ? timer general register b_3 (tgrb_3) ? timer general register c_3 (tgrc_3) ? timer general register d_3 (tgrd_3) ? timer control register_4 (tcr_4) ? timer mode register_4 (tmdr_4) ? timer i/o control register h_4 (tiorh_4) ? timer i/o control register l_4 (tiorl_4) ? timer interrupt enable register_4 (tier_4) ? timer status register_4 (tsr_4) ? timer counter_4 (tcnt_4) ? timer general register a_4 (tgra_4) ? timer general register b_4 (tgrb_4) ? timer general register c_4 (tgrc_4) ? timer general register d_4 (tgrd_4) common registers ? timer start register (tstr) ? timer synchronous register (tsyr) common registers for timers 3 and 4 ? timer output master enable register (toer) ? timer output control enable register (tocr) ? timer gate control register (tgcr) ? timer cycle data register (tcdr) ? timer dead time data register (tddr) ? timer subcounter (tcnts) ? timer cycle buffer register (tcbr) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 220 of 882 rej09b0108-0400 11.3.1 timer control register (tcr) the tcr registers are 8-bit readable/writable regi sters that control the tcnt operation for each channel. the mtu has a total of five tcr regist ers, one for each channel (channel 0 to 4). tcr register settings should be conducted only when tcnt operation is stopped. bit bit name initial value r/w description 7 6 5 cclr2 cclr1 cclr0 0 0 0 r/w r/w r/w counter clear 0 to 2 these bits select the tcnt counter clearing source. see tables 11.3 and 11.4 for details. 4 3 ckeg1 ckeg0 0 0 r/w r/w clock edge 0 and 1 these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. p /4 both edges = p /2 rising edge). if phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. internal clock edge selection is valid when the input clock is p /4 or slower. when p /1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: count at rising edge 01: count at falling edge 1x: count at both edges [legend] x: don?t care 2 1 0 tpsc2 tpsc1 tpsc0 0 0 0 r/w r/w r/w time prescaler 0 to 2 these bits select the tcnt counter clock. the clock source can be selected independently for each channel. see tables 11.5 to 11.8 for details. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 221 of 882 rej09b0108-0400 table 11.3 cclr0 to cclr2 (channels 0, 3, and 4) channel bit 7 cclr2 bit 6 cclr1 bit 5 cclr0 description 0, 3, 4 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is set by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer re gister, tcnt is not cleared because the buffer register setting has priority, and comp are match/input capture does not occur. table 11.4 cclr0 to cclr2 (channels 1 and 2) channel bit 7 reserved * 2 bit 6 cclr1 bit 5 cclr0 description 1, 2 0 0 0 tcnt clearing disabled 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation is select ed by setting the sync bit in tsyr to 1. 2. bit 7 is reserved in channels 1 and 2. it is always read as 0 and cannot be modified. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 222 of 882 rej09b0108-0400 table 11.5 tpsc0 to tpsc2 (channel 0) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 0 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input table 11.6 tpsc0 to tpsc2 (channel 1) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 1 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on p /256 1 counts on tcnt_2 overflow/underflow note: this setting is ignored when channel 1 is in phase counting mode. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 223 of 882 rej09b0108-0400 table 11.7 tpsc0 to tpsc2 (channel 2) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 2 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on p /1024 note: this setting is ignored when channel 2 is in phase counting mode. table 11.8 tpsc0 to tp sc2 (channels 3 and 4) channel bit 2 tpsc2 bit 1 tpsc1 bit 0 tpsc0 description 3, 4 0 0 0 internal clock: counts on p /1 1 internal clock: counts on p /4 1 0 internal clock: counts on p /16 1 internal clock: counts on p /64 1 0 0 internal clock: counts on p /256 1 internal clock: counts on p /1024 1 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 224 of 882 rej09b0108-0400 11.3.2 timer mode register (tmdr) the tmdr registers are 8-bit readab le/writable registers that are used to set the operating mode of each channel. the mtu has five tmdr registers, one for each channel. tm dr register settings should be changed only when tcnt operation is stopped. bit bit name initial value r/w description 7, 6 ? all 1 ? reserved these bits are always read as 1. the write value should always be 1. 5 bfb 0 r/w buffer operation b specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input captur e/output compare is not generated. in channels 1 and 2, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. 0: tgrb and tgrd operate normally 1: tgrb and tgrd used together for buffer operation 4 bfa 0 r/w buffer operation a specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input captur e/output compare is not generated. in channels 1 and 2, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. 0: tgra and tgrc operate normally 1: tgra and tgrc used together for buffer operation 3 2 1 0 md3 md2 md1 md0 0 0 0 0 r/w r/w r/w r/w modes 0 to 3 these bits are used to set the timer operating mode. see table 11.9 for details. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 225 of 882 rej09b0108-0400 table 11.9 md0 to md3 bit 3 md3 bit 2 md2 bit 1 md1 bit 0 md0 description 0 0 0 0 normal operation 1 setting prohibited 1 0 pwm mode 1 1 pwm mode 2 * 1 1 0 0 phase counting mode 1 * 2 1 phase counting mode 2 * 2 1 0 phase counting mode 3 * 2 1 phase counting mode 4 * 2 1 0 0 0 reset synchronous pwm mode * 3 1 setting prohibited 1 x setting prohibited 1 0 0 setting prohibited 1 complementary pwm mode 1 (transmit at peak) * 3 1 0 complementary pwm mode 2 (transmit at valley) * 3 1 complementary pwm mode 2 (transmit at peak and valley) * 3 [legend] x: don?t care notes: 1. pwm mode 2 can not be set for channels 3 and 4. 2. phase counting mode can not be set for channels 0, 3, and 4. 3. reset synchronous pwm mode, complementary pwm mode can only be set for channel 3. when channel 3 is set to reset synchronous pwm mode or complementary pwm mode, the channel 4 settings become ine ffective and automatically conform to the channel 3 settings. however, do not set ch annel 4 to reset synchronous pwm mode or complementary pwm mode. reset synchronous pwm mode and complementary pwm mode cannot be set for channels 0, 1, and 2. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 226 of 882 rej09b0108-0400 11.3.3 timer i/o cont rol register (tior) the tior registers are 8-bit read able/writable registers that cont rol the tgr registers. the mtu has eight tior registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. care is required as tior is affected by the tm dr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. when tgrc or tgrd is designated for buffer opera tion, this setting is invalid and the register operates as a buffer register. ? tiorh_0, tior_1, tior_2, tiorh_3, tiorh_4 bit bit name initial value r/w description 7 6 5 4 iob3 iob2 iob1 iob0 0 0 0 0 r/w r/w r/w r/w i/o control b0 to b3 specify the function of tgrb. see the following tables. tiorh_0: table 11.10 tior_1: table 11.12 tior_2: table 11.13 tiorh_3: table 11.14 tiorh_4: table 11.16 3 2 1 0 ioa3 ioa2 ioa1 ioa0 0 0 0 0 r/w r/w r/w r/w i/o control a0 to a3 specify the function of tgra. see the following tables. tiorh_0: table 11.18 tior_1: table 11.20 tior_2: table 11.21 tiorh_3: table 11.22 tiorh_4: table 11.24 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 227 of 882 rej09b0108-0400 ? tiorl_0, tiorl_3, tiorl_4 bit bit name initial value r/w description 7 6 5 4 iod3 iod2 iod1 iod0 0 0 0 0 r/w r/w r/w r/w i/o control d0 to d3 specify the function of tgrd. see the following tables. tiorl_0: table 11.11 tiorl_3: table 11.15 tiorl_4: table 11.17 3 2 1 0 ioc3 ioc2 ioc1 ioc0 0 0 0 0 r/w r/w r/w r/w i/o control c0 to c3 specify the function of tgrc. see the following tables. tiorl_0: table 11.19 tiorl_3: table 11.23 tiorl_4: table 11.25 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 228 of 882 rej09b0108-0400 table 11.10 tiorh_0 (channel 0) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_0 function tioc0b pin function 0 output retained * 0 1 initial output is 0 0 output at compare match 0 initial output is 0 1 output at compare match 0 1 1 initial output is 0 toggle output at compare match 0 0 output retained 1 initial output is 1 0 output at compare match 0 initial output is 1 1 output at compare match 0 1 1 1 output compare register initial output is 1 toggle output at compare match 1 0 input capture at rising edge 0 1 input capture at falling edge 0 1 x input capture register input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt _1 count- up/count-down [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 229 of 882 rej09b0108-0400 table 11.11 tiorl_0 (channel 0) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_0 function tioc0d pin function 0 0 0 0 output retained * 1 1 initial output is 0 0 output at compare match 1 0 output compare register * 2 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down [legend] x: don?t care notes: 1. after power-on reset, 0 is output until tior is set. 2. when the bfb bit in tmdr_0 is set to 1 and tgrd_0 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 230 of 882 rej09b0108-0400 table 11.12 tior_1 (channel 1) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_1 function tioc1b pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x input capture at generation of tgrc_0 compare match/input capture [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 231 of 882 rej09b0108-0400 table 11.13 tior_2 (channel 2) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_2 function tioc2b pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 232 of 882 rej09b0108-0400 table 11.14 tiorh_3 (channel 3) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_3 function tioc3b pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 233 of 882 rej09b0108-0400 table 11.15 tiorl_3 (channel 3) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_3 function tioc3d pin function 0 0 0 0 output retained * 1 1 output compare register * 2 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges [legend] x: don?t care notes: 1. after power-on rese t, 0 is output until tior is set. 2. when the bfb bit in tmdr_3 is set to 1 and tgrd_3 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 234 of 882 rej09b0108-0400 table 11.16 tiorh_4 (channel 4) description bit 7 iob3 bit 6 iob2 bit 5 iob1 bit 4 iob0 tgrb_4 function tioc4b pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 235 of 882 rej09b0108-0400 table 11.17 tiorl_4 (channel 4) description bit 7 iod3 bit 6 iod2 bit 5 iod1 bit 4 iod0 tgrd_4 function tioc4d pin function 0 0 0 0 output retained * 1 1 output compare register * 2 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges [legend] x: don?t care notes: 1. after power-on reset, 0 is output until tior is set. 2. when the bfb bit in tmdr_4 is set to 1 and tgrd_4 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 236 of 882 rej09b0108-0400 table 11.18 tiorh_0 (channel 0) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_0 function tioc0a pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 237 of 882 rej09b0108-0400 table 11.19 tiorl_0 (channel 0) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_0 function tioc0c pin function 0 0 0 0 output retained * 1 1 output compare register * 2 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges 1 x x capture input source is channel 1/count clock input capture at tcnt _1 count-up/count-down [legend] x: don?t care notes: 1. after power-on reset, 0 is output until tior is set. 2. when the bfa bit in tmdr_0 is set to 1 and tgrc_0 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 238 of 882 rej09b0108-0400 table 11.20 tior_1 (channel 1) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_1 function tioc1a pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 0 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges 1 x x input capture at generation of channel 0/tgra_0 compare match/input capture [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 239 of 882 rej09b0108-0400 table 11.21 tior_2 (channel 2) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_2 function tioc2a pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 240 of 882 rej09b0108-0400 table 11.22 tiorh_3 (channel 3) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_3 function tioc3a pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 241 of 882 rej09b0108-0400 table 11.23 tiorl_3 (channel 3) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_3 function tioc3c pin function 0 0 0 0 output retained * 1 1 output compare register * 2 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges [legend] x: don?t care notes: 1. after power-on reset, 0 is output until tior is set. 2. when the bfa bit in tmdr_3 is set to 1 and tgrc_3 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 242 of 882 rej09b0108-0400 table 11.24 tiorh_4 (channel 4) description bit 3 ioa3 bit 2 ioa2 bit 1 ioa1 bit 0 ioa0 tgra_4 function tioc4a pin function 0 0 0 0 output retained * 1 output compare register initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register input capture at both edges [legend] x: don?t care note: * after power-on reset, 0 is output until tior is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 243 of 882 rej09b0108-0400 table 11.25 tiorl_4 (channel 4) description bit 3 ioc3 bit 2 ioc2 bit 1 ioc1 bit 0 ioc0 tgrc_4 function tioc4c pin function 0 0 0 0 output retained * 1 1 output compare register * 2 initial output is 0 0 output at compare match 1 0 initial output is 0 1 output at compare match 1 initial output is 0 toggle output at compare match 1 0 0 output retained 1 initial output is 1 0 output at compare match 1 0 initial output is 1 1 output at compare match 1 initial output is 1 toggle output at compare match 1 x 0 0 input capture at rising edge 1 input capture at falling edge 1 x input capture register * 2 input capture at both edges [legend] x: don?t care notes: 1. after power-on reset, 0 is output until tior is set. 2. when the bfa bit in tmdr_4 is set to 1 and tgrc_4 is used as a buffer register, this setting is invalid and input captur e/output compare is not generated. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 244 of 882 rej09b0108-0400 11.3.4 timer interrupt enable register (tier) the tier registers are 8-bit read able/writable registers that co ntrol enabling or disabling of interrupt requests for each channel. the mtu has five tier registers, one for each channel. bit bit name initial value r/w description 7 ttge 0 r/w a/d conversion start request enable enables or disables gener ation of a/d conversion start requests by tgra input capture/compare match. 0: a/d conversion start request generation disabled 1: a/d conversion start request generation enabled 6 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 5 tcieu 0 r/w underflow interrupt enable enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu fl ag in tsr is set to 1 in channels 1 and 2. in channels 0, 3, and 4, bit 5 is reserved. it is always read as 0 and the write value should always be 0. 0: interrupt requests (tciu) by tcfu disabled 1: interrupt requests (tciu) by tcfu enabled 4 tciev 0 r/w overflow interrupt enable enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. 0: interrupt requests (tciv) by tcfv disabled 1: interrupt requests (tciv) by tcfv enabled 3 tgied 0 r/w tgr interrupt enable d enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0, 3, and 4. in channels 1 and 2, bit 3 is reserved. it is always read as 0 and the write value should always be 0. 0: interrupt requests (tgid ) by tgfd bit disabled 1: interrupt requests (tgid) by tgfd bit enabled 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 245 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 tgiec 0 r/w tgr interrupt enable c enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0, 3, and 4. in channels 1 and 2, bit 2 is reserved. it is always read as 0 and the write value should always be 0. 0: interrupt requests (tgic ) by tgfc bit disabled 1: interrupt requests (tgic) by tgfc bit enabled 1 tgieb 0 r/w tgr interrupt enable b enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. 0: interrupt requests (tgib) by tgfb bit disabled 1: interrupt requests (tgib) by tgfb bit enabled 0 tgiea 0 r/w tgr interrupt enable a enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. 0: interrupt requests (tgia) by tgfa bit disabled 1: interrupt requests (tgia) by tgfa bit enabled 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 246 of 882 rej09b0108-0400 11.3.5 timer status register (tsr) the tsr registers are 8-bit readable/writable regist ers that indicate the status of each channel. the mtu has five tsr registers, one for each channel. bit bit name initial value r/w description 7 tcfd 1 r count direction flag status flag that shows the di rection in which tcnt counts in channels 1, 2, 3, and 4. in channel 0, bit 7 is reserved. it is always read as 1 and the write value should always be 1. 0: tcnt counts down 1: tcnt counts up 6 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 5 tcfu 0 r/(w) * underflow flag status flag that indicate s that tcnt underflow has occurred when channels 1 and 2 are set to phase counting mode. only 0 can be written, for flag clearing. in channels 0, 3, and 4, bit 5 is reserved. it is always read as 0 and the write value should always be 0. [setting condition] ? when the tcnt value underflows (changes from h'0000 to h'ffff) [clearing condition] ? when 0 is written to tcfu after reading tcfu = 1 4 tcfv 0 r/(w) * overflow flag status flag that indicates that tcnt overflow has occurred. only 0 can be written, for flag clearing. [setting condition] ? when the tcnt value overflows (changes from h'ffff to h'0000) in channel 4, when the tcnt_4 value underflows (changes from h'0001 to h'0000) in complementary pwm mode, this flag is also set. [clearing condition] ? when 0 is written to tcfv after reading tcfv = 1 in cannel 4, when dtc is activated by tciv interrupt and the disel bit of dtmr in dtc is 0, this flag is also cleared. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 247 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 tgfd 0 r/(w) * input capture/output compare flag d status flag that indicates the occurrence of tgrd input capture or compare match in channels 0, 3, and 4. only 0 can be written, for flag clearing. in channels 1 and 2, bit 3 is reserved. it is always read as 0 and the write value should always be 0. [setting conditions] ? when tcnt = tgrd and tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal and tgrd is functioning as input capture register [clearing conditions] ? when dtc is activated by tgid interrupt and the disel bit of dtmr in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 2 tgfc 0 r/(w) * input capture/output compare flag c status flag that indicates the occurrence of tgrc input capture or compare match in channels 0, 3, and 4. only 0 can be written, for flag clearing. in channels 1 and 2, bit 2 is reserved. it is always read as 0 and the write value should always be 0. [setting conditions] ? when tcnt = tgrc and tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal and tgrc is functioning as input capture register [clearing conditions] ? when dtc is activated by tgic interrupt and the disel bit of dtmr in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 248 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 tgfb 0 r/(w) * input capture/output compare flag b status flag that indicates t he occurrence of tgrb input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgrb and tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal and tgrb is functioning as input capture register [clearing conditions] ? when dtc is activated by tgib interrupt and the disel bit of dtmr in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 0 tgfa 0 r/(w) * input capture/output compare flag a status flag that indicates t he occurrence of tgra input capture or compare match. only 0 can be written, for flag clearing. [setting conditions] ? when tcnt = tgra and tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal and tgra is functioning as input capture register [clearing conditions] ? when dtc is activated by tgia interrupt and the disel bit of dtmr in dtc is 0 ? when 0 is written to tgfa after reading tgfa = 1 note: * only 0 can be written to clear the flag. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 249 of 882 rej09b0108-0400 11.3.6 timer counter (tcnt) the tcnt registers are 16-bit r eadable/writable counters. the mt u has five tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset. the tcnt counters cannot be accessed in 8-bit un its; they must always be accessed as a 16-bit unit. 11.3.7 timer general register (tgr) the tgr registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture register s. the mtu has 16 tgr registers, four each for channels 0, 3, and 4 and two each for channels 1 and 2. tgrc and tgrd for channels 0, 3, and 4 can also be designated for operation as buffer registers. th e tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. tgr buffer register combinations are tgra and tgrc and tgrb and tgrd. the initial value of tgr is h'ffff. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 250 of 882 rej09b0108-0400 11.3.8 timer start register (tstr) tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. when setting the operating mode in tmdr or setting the count clock in tcr, first stop the tcnt counter. bit bit name initial value r/w description 7 6 cst4 cst3 0 0 r/w r/w counter start 4 and 3 these bits select operat ion or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_4 and tcnt_3 co unt operation is stopped 1: tcnt_4 and tcnt_3 per forms count operation 5 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 cst2 cst1 cst0 0 0 0 r/w r/w r/w counter start 2 to 0 these bits select operat ion or stoppage for tcnt. if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: tcnt_2 to tcnt_0 coun t operation is stopped 1: tcnt_2 to tcnt_0 per forms count operation 11.3.9 timer synchronous register (tsyr) tsyr is an 8-bit readable/writable register th at selects independent operation or synchronous operation for the channel 0 to 4 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 251 of 882 rej09b0108-0400 bit bit name initial value r/w description 7 6 sync4 sync3 0 0 r/w r/w timer synchronous operation 4 and 3 these bits are used to select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, the tcnt synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr0 to cclr2 in tcr. 0: tcnt_4 and tcnt_3 o perate independently (tcnt presetting/clearing is unrelated to other channels) 1: tcnt_4 and tcnt_3 performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible 5 to 3 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 2 1 0 sync2 sync1 sync0 0 0 0 r/w r/w r/w timer synchronous operation 2 to 0 these bits are used to select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, the tcnt synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit, the tcnt clearing source must also be set by means of bits cclr0 to cclr2 in tcr. 0: tcnt_2 to tcnt_0 op erates independently (tcnt presetting /clearing is unrelated to other channels) 1: tcnt_2 to tcnt_0 performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 252 of 882 rej09b0108-0400 11.3.10 timer output master enable register (toer) toer is an 8-bit readable/writable register that enables/disables output settings for output pins tioc4d, tioc4c, tioc3d, tioc4b, tioc4a, and tioc3b. these pins do not output correctly if the toer bits have not been set. set toer of ch3 and ch4 prior to setting tior of ch3 and ch4. bit bit name initial value r/w description 7, 6 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 5 oe4d 0 r/w master enable tioc4d this bit enables/disables the tioc4d pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 4 oe4c 0 r/w master enable tioc4c this bit enables/disables the tioc4c pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 3 oe3d 0 r/w master enable tioc3d this bit enables/disables the tioc3d pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 2 oe4b 0 r/w master enable tioc4b this bit enables/disables the tioc4b pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 1 oe4a 0 r/w master enable tioc4a this bit enables/disables the tioc4a pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 0 oe3b 0 r/w master enable tioc3b this bit enables/disables the tioc3b pin mtu output. 0: mtu output is disabled 1: mtu output is enabled 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 253 of 882 rej09b0108-0400 11.3.11 timer output co ntrol register (tocr) tocr is an 8-bit readable/writable register that enables/disables pwm synchronized toggle output in complementary pwm mode/reset synchronized pwm mode, and controls output level inversion of pwm output. bit bit name initial value r/w description 7 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 6 psye 0 r/w pwm synchronous output enable this bit selects the enable /disable of toggle output synchronized with the pwm period. 0: toggle output is disabled 1: toggle output is enabled 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 olsn 0 r/w output level select n this bit selects the reverse phase output level in reset-synchronized pwm mode/complementary pwm mode. see table 11.26 0 olsp 0 r/w output level select p this bit selects the positive phase output level in reset-synchronized pwm mode/complementary pwm mode. see table 11.27 table 11.26 output level select function bit 1 function compare match output olsn initial output active level up count down count 0 high level low level high level low level 1 low level high level low level high level note: the reverse phase waveform initial output val ue changes to active level after elapse of the dead time after count start. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 254 of 882 rej09b0108-0400 table 11.27 output level select function bit 0 function compare match output olsp initial output active level up count down count 0 high level low level low level high level 1 low level high level high level low level figure 11.2 shows an example of complementary pwm mode output (1 phase) when olsn = 1, olsp = 1. tcnt_3, and tcnt_4 values tgra_3 tgra_4 tddr h'0000 time tcnt_4 tcnt_3 positive phase output reverse phase output active level compare match output (up count) initial output initial output active level compare match output (down count) compare match output (down count) compare match output (up count) active level figure 11.2 complementary pwm mode output level example 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 255 of 882 rej09b0108-0400 11.3.12 timer gate cont rol register (tgcr) tgcr is an 8-bit readable/writable register that controls the waveform output necessary for brushless dc motor control in reset-synchronized pwm mode/complementary pwm mode. these register settings are ineffective for anything other than complementary pwm mode/reset- synchronized pwm mode. bit bit name initial value r/w description 7 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 6 bdc 0 r/w brushless dc motor this bit selects whether to make the functions of this register (tgcr) effective or ineffective. 0: ordinary output 1: functions of this register are made effective 5 n 0 r/w reverse phase output (n) control this bit selects whether the level output or the reset- synchronized pwm/complementary pwm output while the reverse pins (tioc3d, tioc4c, and tioc4d) are output. 0: level output 1: reset synchronized pwm/complementary pwm output 4 p 0 r/w positive phase output (p) control this bit selects whether the level output or the reset- synchronized pwm/complementary pwm output while the positive pin (tioc3b, tioc4a, and tioc4b) are output. 0: level output 1: reset synchronized pwm/complementary pwm output 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 256 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 fb 0 r/w external feedback signal enable this bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the mt u/channel 0 tgra, tgrb, tgrc input capture signals or by writing 0 or 1 to bits 2 to 0 in tgcr. 0: output switching is ex ternal input (input sources are channel 0 tgra, tgrb, tgrc input capture signal) 1: output switching is carried out by software (tgcr's uf, vf, wf settings). 2 1 0 wf vf uf 0 0 0 r/w r/w r/w output phase switch 2 to 0 these bits set the posit ive phase/negative phase output phase on or off state. the setting of these bits is valid only when the fb bit in this register is set to 1. in this case, the setting of bi ts 2 to 0 is a substitute for external input. see table 11.28. table 11.28 output level select function function bit 2 bit 1 bit 0 tioc3b tioc4a tioc4b tioc3d tioc4c tioc4d wf vf uf u phase v phase w phase u phase v phase w phase 0 0 0 off off off off off off 1 on off off off off on 1 0 off on off on off off 1 off on off off off on 1 0 0 off off on off on off 1 on off off off on off 1 0 off off on on off off 1 off off off off off off 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 257 of 882 rej09b0108-0400 11.3.13 timer subcounter (tcnts) tcnts is a 16-bit read-only counter that is used only in complementary pwm mode. the initial value of tcnts is h'0000. note: accessing the tcnts in 8-bit units is prohibited. always access in 16-bit units. 11.3.14 timer dead time data register (tddr) tddr is a 16-bit register, used only in complementary pwm mode, that specifies the tcnt_3 and tcnt_4 counter offset values. in comp lementary pwm mode, when the tcnt_3 and tcnt_4 counters are cleared and then restarted, the tddr register value is loaded into the tcnt_3 counter and the count operation starts. the initial value of tddr is h'ffff. note: accessing the tddr in 8-bit units is prohibited. always access in 16-bit units. 11.3.15 timer period data register (tcdr) tcdr is a 16-bit register used only in complementary pwm mode. set half the pwm carrier sync value as the tcdr register value. this register is constantly compared with the tcnts counter in complementary pwm mode, and when a match occurs, the tcnts counter switches direction (decrement to increment). the initial value of tcdr is h'ffff. note: accessing the tcdr in 8-bit units is prohibited. always access in 16-bit units. 11.3.16 timer period buffer register (tcbr) the timer period buffer register (tcbr) is a 16-b it register used only in complementary pwm mode. it functions as a buffer register for th e tcdr register. the t cbr register values are transferred to the tcdr regist er with the transfer timing set in the tmdr register. note: accessing the tcbr in 8-bit units is prohibited. always access in 16-bit units. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 258 of 882 rej09b0108-0400 11.3.17 bus master interface the timer counters (tcnt), general registers (tgr), timer subcounter (tcnts), timer period buffer register (tcbr), and timer dead time data re gister (tddr), and timer period data register (tcdr) are 16-bit registers. a 16-bit data bus to the bus master enables 16 -bit read/writes. 8-bit read/write is not possible. al ways access in 16-bit units. all registers other than the above registers are 8-b it registers. these are connected to the cpu by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 259 of 882 rej09b0108-0400 11.4 operation 11.4.1 basic functions each channel has a tcnt and tgr register. tcnt performs up-counting, an d is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input captur e register or output compare register. always select mtu external pins set function using the pin function controller (pfc). counter operation: when one of bits cst0 to cst4 is set to 1 in tstr, the tcnt counter for the corresponding channel begins counting. tcnt can operate as a free-running counter, periodic counter, for example. 1. example of count operation setting procedure figure 11.3 shows an example of the count operation setting procedure. operation selection select counter clock periodic counter select counter clearin g source select output compare re g ister set period free-runnin g counter start count operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 260 of 882 rej09b0108-0400 2. free-running count operation and periodic count operation: immediately after a reset, the mtu?s tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 11.4 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 11.4 free-runni ng counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compar e register, and counter clearing by compare match is selected by means of bits cclr0 to cclr2 in tcr. af ter the settings have been made, tcnt starts up-count operation as a periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt st arts counting up again from h'0000. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 261 of 882 rej09b0108-0400 figure 11.5 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match fla g cleared by software or dtc/dmac activation figure 11.5 period ic counter operation waveform output by compare match: the mtu can perform 0, 1, or toggle output from the corresponding output pin using compare match. 1. example of setting procedure for waveform output by compare match figure 11.6 shows an example of the setting procedure for waveform output by compare match output selection select waveform output mode set output timin g start count operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 262 of 882 rej09b0108-0400 2. examples of waveform output operation: figure 11.7 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made such that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no chan g e no chan g e no chan g e no chan g e 1 output 0 output figure 11.7 example of 0 output/1 output operation figure 11.8 shows an example of toggle output. in this example, tcnt has b een designated as a periodic co unter (with counter clearing on compare match b), and settings have been made such that the output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra to gg le output to gg le output counter cleared by tgrb compare match figure 11.8 example of toggle output operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 263 of 882 rej09b0108-0400 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. for channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. note: when another channel's counter input clock is used as the input capture input for channels 0 and 1, p /1 should not be selected as the count er input clock used for input capture input. input capture will not be generated if p /1 is selected. 1. example of input capture operation setting procedure figure 11.9 shows an example of the input capture operation setting procedure. input selection select input capture input start count [1] [2] [1] desi g nate tgr as an input capture re g ister by means of tior, and select risin g ed g e, fallin g ed g e, or both ed g es as the input capture source and input si g nal ed g e. [2] set the cst bit in tstr to 1 to start the count operation. figure 11.9 example of input ca pture operation setting procedure 2. example of input capture operation: figure 11.10 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, the falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 264 of 882 rej09b0108-0400 tcnt value h'0180 h'0000 tioca tgra h'0010 h'0005 counter cleared by tiocb input (fallin g ed g e) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb time figure 11.10 example of input capture operation 11.4.2 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incr emented with respect to a single time base. channels 0 to 4 can all be designated for synchronous operation. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 265 of 882 rej09b0108-0400 example of synchronous operation setting procedure: figure 11.11 shows an example of the synchronous operation setting procedure. no yes set synchronous operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 266 of 882 rej09b0108-0400 for details of pwm modes, see section 11.4.5, pwm modes. tcnt0 to tcnt2 values h'0000 tioc0a tioc1a tgrb_0 synchronous clearin g by tgrb_0 compare match tgra_2 tgra_1 tgrb_2 tgra_0 tgrb_1 tioc2a time figure 11.12 example of synchronous operation 11.4.3 buffer operation buffer operation, provided for channels 0, 3, and 4, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 11.29 shows the register combinations used in buffer operation. table 11.29 register combinat ions in buffer operation channel timer general re gister buffer register 0 tgra_0 tgrc_0 tgrb_0 tgrd_0 3 tgra_3 tgrc_3 tgrb_3 tgrd_3 4 tgra_4 tgrc_4 tgrb_4 tgrd_4 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 267 of 882 rej09b0108-0400 ? when tgr is an output compare register when a compare match occurs, the value in the bu ffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 11.13. buffer re g ister timer g eneral re g ister tcnt comparator compare match si g nal figure 11.13 compare match buffer operation ? when tgr is an inpu t capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 11.14. buffer re g ister timer g eneral re g ister tcnt input capture si g nal figure 11.14 input ca pture buffer operation example of buffer operation setting procedure: figure 11.15 shows an example of the buffer operation setting procedure. buffer operation select tgr function set buffer operation start count 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 268 of 882 rej09b0108-0400 examples of buffer operation: 1. when tgr is an output compare register figure 11.16 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compar e match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when comp are match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time that compare match a occurs. for details of pwm modes, see section 11.4.5, pwm modes. tcnt value tgrb_0 h'0000 tgrc_0 tgra_0 h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgra_0 h'0450 h'0200 transfer time figure 11.16 example of buffer operation (1) 2. when tgr is an i nput capture register figure 11.17 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon the occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 269 of 882 rej09b0108-0400 tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 11.17 example of buffer operation (2) 11.4.4 cascaded operation in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 counter clock upon overflow/underflow of tcnt_2 as set in bits tpsc0 to tpsc2 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 11.30 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1, the counter clock setting is invalid and the counters operates independently in phase counting mode. table 11.30 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt_1 tcnt_2 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 270 of 882 rej09b0108-0400 example of cascaded oper ation setting procedure: figure 11.18 shows an example of the setting procedure for cascaded operation. cascaded operation set cascadin g start count 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 271 of 882 rej09b0108-0400 11.4.5 pwm modes in pwm mode, pwm waveforms are output from the output pins. the output level can be selected as 0, 1, or toggle output in respon se to a compare match of each tgr. tgr registers settings can be used to output a pwm waveform in the range of 0% to 100% duty. designating tgr compare match as the counter clearin g source enables the period to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. 1. pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits io a0 to ioa3 and ioc0 to ioc3 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob0 to iob3 and iod0 to iod3 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. 2. pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization regi ster compare match, the output value of each pin is the initial value set in tior. if the set values of the cy cle and duty registers ar e identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 8-phase pwm output is possible in combination use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 11.31. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 272 of 882 rej09b0108-0400 table 11.31 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 tgra_0 tioc0a tgrb_0 tioc0a tioc0b tgrc_0 tioc0c 0 tgrd_0 tioc0c tioc0d tgra_1 tioc1a 1 tgrb_1 tioc1a tioc1b tgra_2 tioc2a 2 tgrb_2 tioc2a tioc2b tgra_3 cannot be set tgrb_3 tioc3a cannot be set tgrc_3 cannot be set 3 tgrd_3 tioc3c cannot be set 4 tgra_4 cannot be set tgrb_4 tioc4a cannot be set tgrc_4 tioc4c cannot be set tgrd_4 cannot be set note: in pwm mode 2, pwm output is not possible fo r the tgr register in which the period is set. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 273 of 882 rej09b0108-0400 example of pwm mode setting procedure: figure 11.20 shows an example of the pwm mode setting procedure. pwm mode select counter clock select counter clearin g source select waveform output level set tgr set pwm mode start count 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 274 of 882 rej09b0108-0400 figure 11.22 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgrb_1 compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgra_0 to tgrd_0, tgra_1), outputting a 5-phase pwm waveform. in this case, the value set in tgrb_1 is used as th e cycle, and the values set in the other tgrs are used as the duty levels. tcnt value tgrb_1 h'0000 tioc0a counter cleared by tgrb_1 compare match time tgra_1 tgrd_0 tgrc_0 tgrb_0 tgra_0 tioc0b tioc0c tioc0d tioc1a figure 11.22 example of pwm mode operation (2) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 275 of 882 rej09b0108-0400 figure 11.23 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not chan g e when cycle re g ister and duty re g ister compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not chan g e when cycle re g ister and duty re g ister compare matches occur simultaneously 0% duty figure 11.23 example of pwm mode operation (3) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 276 of 882 rej09b0108-0400 11.4.6 phase counting mode in phase counting mode, the phase difference betw een two external clock inputs is detected and tcnt is incremented/decremented accordingly. th is mode can be set for channels 1 and 2. when phase counting mode is set, an external cl ock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc0 to tpsc2 and bits ckeg0 and ckeg1 in tcr. however, the functions of bits cclr0 and cclr1 in tcr, and of tior, tier, and tgr, are valid, and input capture /compare match and interrupt functions can be used. this can be used for two-phase encoder pulse input. if overflow occurs when tcnt is counting up, the tcfv flag in tsr is set; if underflow occurs when tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag reveals whether tcnt is counting up or down. table 11.32 shows the correspondence between external clock pins and channels. table 11.32 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 is set to phase counting mode tclka tclkb when channel 2 is set to phase counting mode tclkc tclkd example of phase counting mode setting procedure: figure 11.24 shows an example of the phase counting mode setting procedure. phase countin g mode select phase countin g mode start count 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 277 of 882 rej09b0108-0400 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. 1. phase counting mode 1 figure 11.25 shows an example of phase counting mode 1 operation, and table 11.33 summarizes the tcnt up/down-count conditions. tcnt value time tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) up-count down-count figure 11.25 example of phase counting mode 1 operation table 11.33 up/down-count condit ions in phase counting mode 1 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level high level high level down-count low level high level low level [legend] : rising edge : falling edge 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 278 of 882 rej09b0108-0400 2. phase counting mode 2 figure 11.26 shows an example of phase counting mode 2 operation, and table 11.34 summarizes the tcnt up/down-count conditions. time down-count up-count tcnt value tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 11.26 example of phase counting mode 2 operation table 11.34 up/down-count condit ions in phase counting mode 2 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level don?t care low level don?t care low level don?t care high level up-count high level don?t care low level don?t care high level don?t care low level down-count [legend] : rising edge : falling edge 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 279 of 882 rej09b0108-0400 3. phase counting mode 3 figure 11.27 shows an example of phase counting mode 3 operation, and table 11.35 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 11.27 example of phase counting mode 3 operation table 11.35 up/down-count condit ions in phase counting mode 3 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level don?t care low level don?t care low level don?t care high level up-count high level down-count low level don?t care high level don?t care low level don?t care [legend] : rising edge : falling edge 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 280 of 882 rej09b0108-0400 4. phase counting mode 4 figure 11.28 shows an example of phase counting mode 4 operation, and table 11.36 summarizes the tcnt up/down-count conditions. time up-count down-count tcnt value tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 11.28 example of phase counting mode 4 operation table 11.36 up/down-count condit ions in phase counting mode 4 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level don?t care high level high level down-count low level high level don?t care low level [legend] : rising edge : falling edge 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 281 of 882 rej09b0108-0400 phase counting mode application example: figure 11.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgrc_0 compare match; tgra_0 and tgrc_0 are used for the compare match function and are set with the speed control period and position control period. tgrb_0 is used for input capture, with tgrb_0 and tgrd_0 operating in buffer mode. the channel 1 counter input clock is designated as the tgrb_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. tgra_1 and tgrb_1 for channel 1 are designated for input capture, and channel 0 tgra_0 and tgrc_0 compare matches are selected as the inpu t capture source and store the up/down-counter values for the control periods. this procedure enables the accurate detection of position and speed. tcnt_1 tcnt_0 channel 1 tgra_1 (speed period capture) tgra_0 (speed control period) tgrb_1 (position period capture) tgrc_0 (position control period) tgrb_0 (pulse width capture) tgrd_0 (buffer operation) channel 0 tclka tclkb ed g e detection circuit + - + - figure 11.29 phase counting mode application example 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 282 of 882 rej09b0108-0400 11.4.7 reset-synchronized pwm mode in the reset-synchronized pwm mode, three-phase output of positive and negative pwm waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. when set for reset-synchronized pwm mode, the tioc3b, tioc3d, tioc4a, tioc4c, tioc4b, and tioc4d pins function as pwm output pins and tcnt3 functions as an upcounter. table 11.37 shows the pwm output pins used. table 11.38 shows the settings of the registers. table 11.37 output pins for reset-synchronized pwm mode channel output pin description 3 tioc3b pwm output pin 1 tioc3d pwm output pin 1' (negativ e-phase waveform of pwm output 1) 4 tioc4a pwm output pin 2 tioc4c pwm output pin 2' (negativ e-phase waveform of pwm output 2) tioc4b pwm output pin 3 tioc4d pwm output pin 3' (negativ e-phase waveform of pwm output 3) table 11.38 register settings fo r reset-synchronized pwm mode register description of setting tcnt_3 initial setting of h'0000 tcnt_4 initial setting of h'0000 tgra_3 set count cycle for tcnt_3 tgrb_3 sets the turning point for pwm wavefo rm output by the tioc3b and tioc3d pins tgra_4 sets the turning point for pwm wavefo rm output by the tioc4a and tioc4c pins tgrb_4 sets the turning point for pwm wavefo rm output by the tioc4b and tioc4d pins 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 283 of 882 rej09b0108-0400 procedure for selecting the reset-synchronized pwm mode: figure 11.30 shows an example of procedure for selecting the reset synchronized pwm mode. stop countin g select counter clock and counter clear source set tgr reset-synchronized pwm mode brushless dc motor control settin g set tcnt enable waveform output set reset-synchronized pwm mode pwm cycle output enablin g , pwm output level settin g start count operation reset-synchronized pwm mode [1] clear the cst3 and cst4 bits in the tstr to 0 to halt the countin g of tcnt. the reset-synchronized pwm mode must be set up while tcnt_3 and tcnt_4 are halted. [2] set bits tpsc2-tpsc0 and ckeg1 and ckeg0 in the tcr_3 to select the counter clock and clock ed g e for channel 3. set bits cclr2-cclr0 in the tcr_3 to select tgra compare-match as a counter clear source. [3] when performin g brushless dc motor control, set bit bdc in the timer g ate control re g ister (tgcr) and set the feedback si g nal input source and output choppin g or g ate si g nal direct output. [4] reset tcnt_3 and tcnt_4 to h'0000. [5] tgra_3 is the period re g ister. set the waveform period value in tgra_3. set the transition timin g of the pwm output waveforms in tgrb_3, tgra_4, and tgrb_4. set times within the compare-match ran g e of tcnt_3. x tgra_3 (x: set value). [6] select enablin g /disablin g of to gg le output synchronized with the pmw cycle usin g bit psye in the timer output control re g ister (tocr), and set the pwm output level with bits olsp and olsn. [7] set bits md3-md0 in tmdr_3 to b'1000 to select the reset-synchronized pwm mode. do not set to tmdr_4. [8] set the enablin g /disablin g of the pwm waveform output pin in toer. [9] set the port control re g ister and the port i/o re g ister. [10] set the cst3 bit in the tstr to 1 to start the count operation. [1] [2] [3] [4] [5] [6] [7] [8] pfc settin g [9] [10] note: the output waveform starts to to gg le operation at the point of tcnt_3 = tgra_3 = x by settin g x = tgra, i.e., cycle = duty. figure 11.30 procedure for select ing reset-synchronized pwm mode 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 284 of 882 rej09b0108-0400 reset-synchronized pwm mode operation: figure 11.31 shows an example of operation in the reset-synchronized pwm mode. tcnt_3 and tcnt_4 operate as upcounters. the counter is cleared when a tcnt_3 and tgra_3 compare-match occurs, and then begins incrementing from h'0000. the pwm output pin output toggles w ith each occurrence of a tgrb_3, tgra_4, tgrb_4 compare-match, a nd upon counter clears. tgra_3 tgrb_3 tgrb_4 h'0000 tgra_4 tioc3b tioc3d tioc4a tioc4c tioc4b tioc4d time tcnt_3 and tcnt_4 values figure 11.31 reset-synchronized pwm mode operation example (when tocr?s olsn = 1 and olsp = 1) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 285 of 882 rej09b0108-0400 11.4.8 complementary pwm mode in the complementary pwm mode, three-phase output of non-overlapping positive and negative pwm waveforms can be obtained by combining channels 3 and 4. in complementary pwm mode, tioc3b, tioc3d, tioc4a, tioc4b, tioc4c, and tioc4d pins function as pwm output pins, the tioc3a pin can be set for toggle output synchronized with the pwm period. tcnt_3 and tcnt_4 function as up/down counters. table 11.39 shows the pwm output pins used. table 11.40 shows the settings of the registers used. a function to directly cut off the pwm output by using an external signal is supported as a port function. table 11.39 output pins fo r complementary pwm mode channel output pin description 3 tioc3a toggle output synchroni zed with pwm period (or i/o port) tioc3b pwm output pin 1 tioc3c i/o port * tioc3d pwm output pin 1 (non-overlapping negative-phas e waveform of pwm output 1) 4 tioc4a pwm output pin 2 tioc4b pwm output pin 3 tioc4c pwm output pin 2 (non-overlapping negative-phas e waveform of pwm output 2) tioc4d pwm output pin 3 (non-overlapping negative-phas e waveform of pwm output 3) note: * avoid setting the tioc3c pin as a time r i/o pin in the complementary pwm mode. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 286 of 882 rej09b0108-0400 table 11.40 register settings for complementary pwm mode channel counter/register descri ption read/write from cpu 3 tcnt_3 start of up-count from value set in dead time register maskable by bsc/bcr1 setting * tgra_3 set tcnt_3 upper limit value (1/2 carrier cycle + dead time) maskable by bsc/bcr1 setting * tgrb_3 pwm output 1 compare r egister maskable by bsc/bcr1 setting * tgrc_3 tgra_3 buffer register always readable/writable tgrd_3 pwm output 1/tgrb_3 buffer register always readable/writable 4 tcnt_4 up-count start, initialized to h'0000 maskable by bsc/bcr1 setting * tgra_4 pwm output 2 compare r egister maskable by bsc/bcr1 setting * tgrb_4 pwm output 3 compare r egister maskable by bsc/bcr1 setting * tgrc_4 pwm output 2/tgra_4 buffer register always readable/writable tgrd_4 pwm output 3/tgrb_4 buffer register always readable/writable timer dead time data register (tddr) set tcnt_4 and tcnt_3 offset value (dead time value) maskable by bsc/bcr1 setting * timer cycle data register (tcdr) set tcnt_4 upper limit value (1/2 carrier cycle) maskable by bsc/bcr1 setting * timer cycle buffer register (tcbr) tcdr buffer register always readable/writable subcounter (tcnts) subcounter for dead time generation read-only temporary register 1 (temp1) pwm output 1/tgrb_3 temporary register not readable/writable temporary register 2 (temp2) pwm output 2/tgra_4 temporary register not readable/writable temporary register 3 (temp3) pwm output 3/tgrb_4 temporary register not readable/writable note: * access can be enabled or disabled according to the setting of bit 13 (mturwe) in bsc/bcr1 (bus controller/bus control register 1). 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 287 of 882 rej09b0108-0400 tgrc_3 tddr tcnt_3 tgrd_3 tgrd_4 tgrc_4 tgrb_3 temp 1 tgra_4 temp 2 tgrb_4 temp 3 tcnts tcnt_4 tgra_3 tcdr tcbr comparator comparator match si g nal match si g nal output controller output protection circuit pwm cycle output pwm output 1 pwm output 2 pwm output 3 pwm output 4 pwm output 5 pwm output 6 poe0 poe1 poe2 poe3 external cutoff input external cutoff interrupt : re g isters that can always be read or written from the cpu : re g isters that cannot be read or written from the cpu (except for tcnts, which can only be read) : re g isters that can be read or written from the cpu (but for which access disablin g can be set by the bus controller) tgra_3 compare- match interrupt tcnt_4 underflow interrupt figure 11.32 block diagram of channels 3 and 4 in complementary pwm mode 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 288 of 882 rej09b0108-0400 example of complementary pwm mode setting procedure: an example of the complementary pwm mode setting procedure is shown in figure 11.33. complementary pwm mode stop count operation counter clock, counter clear source selection brushless dc motor control settin g tcnt settin g inter-channel synchronization settin g tgr settin g dead time, carrier cycle settin g pwm cycle output enablin g , pwm output level settin g complementary pwm mode settin g enable waveform output start count operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 289 of 882 rej09b0108-0400 outline of complementary pwm mode operation: in complementary pwm mode, 6-phase pwm output is possible. figure 11.34 illustrates counter operation in complementary pwm mode, and figure 11.35 shows an example of complementary pwm mode operation. 1. counter operation in complementary pwm mode, three counters?tcnt_3, tcnt_4, and tcnts?perform up/down-count operations. tcnt_3 is automatically initialized to the value set in tddr when complementary pwm mode is selected and the cst bit in tstr is 0. when the cst bit is set to 1, tcnt_3 counts up to the value set in tgra_3, then switches to down-counting when it matches tgra_3. when the tcnt3 value matches tddr, the counter switches to up-counting, and the operation is repeated in this way. tcnt_4 is initialized to h'0000. when the cst bit is set to 1, tcnt4 counts up in synchronization with tcnt_3, and switches to down-counting when it matches tcdr. on reaching h'0000, tcnt4 switches to up-counting, and the operation is repeated in this way. tcnts is a read-only counter. it need not be initialized. when tcnt_3 matches tcdr during tcnt_3 and tcnt_4 up/down-counting, down- counting is started, and when tcnts matches tcdr, the operation switches to up-counting. when tcnts matches tgra_3, it is cleared to h'0000. when tcnt_4 matches tddr during tcnt_3 and tcnt_4 down-counting, up-counting is started, and when tcnts matches tddr, the operation switches to down-counting. when tcnts reaches h'0000, it is set with the value in tgra_3. tcnts is compared with the co mpare register and temporary register in which the pwm duty is set during the count operation only. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 290 of 882 rej09b0108-0400 counter value tgra_3 tcdr tddr h'0000 tcnt_4 tcnts tcnt_3 tcnt_3 tcnt_4 tcnts time figure 11.34 complementary pwm mode counter operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 291 of 882 rej09b0108-0400 2. register operation: in complementary pwm mode, nine registers are used, comprising compar e registers, buffer registers, and temporary registers. figure 11.35 shows an example of complementary pwm mode operation. the registers which are constantly compared with the counters to perform pwm output are tgrb_3, tgra_4, and tgrb_4. when these registers match the counter, the value set in bits olsn and olsp in the timer output control register (tocr) is output. the buffer registers for th ese compare registers are tgrd_3, tgrc_4, and tgrd_4. between a buffer register and compare register there is a temporary re gister. the temporary registers cannot be accessed by the cpu. data in a compare register is changed by writing the new data to the corresponding buffer register. the buffer registers can be read or written at any time. the data written to a buffer register is constantly transferred to the tempor ary register in the ta interval. data is not transferred to the temporary register in the tb interval. data written to a buffer register in this interval is transferred to the temporary register at the end of the tb interval. the value transferred to a temporary register is transferred to the compare register when tcnts for which the tb interval ends matches tgra_3 when counting up, or h'0000 when counting down. the timing for transfer from the temporary register to the compare register can be selected with bits md3 to md0 in the timer mode register (tmdr). figure 11.35 shows an example in which the mode is selected in which the change is made in the trough. in the tb interval (tb1 in figure 11.35) in whic h data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. in this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. in this interval, the three counters?tcnt_3, tcnt_4, and tcnts?and two registers?compare register and temporary register?are compared, and pwm output controlled accordingly. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 292 of 882 rej09b0108-0400 tgra_3 tcdr tgra_4 tgrc_4 tddr h'0000 buffer re g ister tgrc_4 temporary re g ister temp2 compare re g ister tgra_4 output waveform output waveform tb2 ta tb1 ta tb2 ta tcnt_3 tcnt_4 tcnts (output waveform is active-low) h'6400 h'0080 h'6400 h'6400 h'0080 h'0080 transfer from temporary re g ister to compare re g ister transfer from temporary re g ister to compare re g ister figure 11.35 example of complementary pwm mode operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 293 of 882 rej09b0108-0400 3. initialization in complementary pwm mode, there are si x registers that must be initialized. before setting complementary pwm mode with b its md3 to md0 in the timer mode register (tmdr), the following initial register values must be set. tgrc_3 operates as the buffer register for tgra_3, and should be set with 1/2 the pwm carrier cycle + dead time td. the timer cycle buffer register (tcbr) operates as the buffer register for the timer cycle data register (tcd r), and should be set with 1/2 the pwm carrier cycle. set dead time td in the time r dead time data register (tddr). set the respective initial pwm duty values in buffer registers tgrd_3, tgrc_4, and tgrd_4. the values set in the five buffe r registers excluding tddr are transferred simultaneously to the corresponding compare registers when complementary pwm mode is set. set tcnt_4 to h'0000 before setting complementary pwm mode. table 11.41 registers and coun ters requiring initialization register/counter set value tgrc_3 1/2 pwm carrier cycle + dead time td tddr dead time td tcbr 1/2 pwm carrier cycle tgrd_3, tgrc_4, tgrd_4 initial pwm duty value for each phase tcnt_4 h'0000 note: the tgrc_3 set value must be the sum of 1/2 the pwm carrier cycle set in tcbr and dead time td set in tddr. 4. pwm output level setting in complementary pwm mode, the pwm pulse outp ut level is set with bits olsn and olsp in the timer output control register (tocr). the output level can be set for each of the three positive phases and three negative phases of 6- phase output. complementary pwm mode should be cleared before setting or changing output levels. 5. dead time setting in complementary pwm mode, pwm pulses are output with a non-overlapping relationship between the positive and negative phases. this non-overlap time is called the dead time. the non-overlap time is set in the timer dead time data register (tddr). the value set in tddr is used as the tcnt_3 counter start va lue, and creates non-overlap between tcnt_3 and tcnt_4. complementary pwm mode should be cleared before changing the contents of tddr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 294 of 882 rej09b0108-0400 6. pwm cycle setting in complementary pwm mode, the pwm pulse cy cle is set in two registers?tgra_3, in which the tcnt_3 upper limit value is set, and tcdr, in which the tcnt_4 upper limit value is set. the settings should be made so as to achieve the following relationship between these two registers: tgra_3 set value = tcdr set value + tddr set value the tgra_3 and tcdr settings are made by setting the values in buffer registers tgrc_3 and tcbr. the values set in tgrc_3 and tcbr are transferred simultaneously to tgra_3 and tcdr in accordance with the transfer timing selected with bits md3 to md0 in the timer mode register (tmdr). the updated pwm cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when perfor med in the trough. figure 11.36 illustrates the operation when the pwm cycle is updated at the crest. see the following section, register data updatin g, for the method of updating the data in each buffer register. counter value tgrc_3 update tgra_3 update tgra_3 tcnt_3 tcnt_4 time figure 11.36 example of pwm cycle updating 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 295 of 882 rej09b0108-0400 7. register data updating in complementary pwm mode, the buffer register is used to update the data in a compare register. the update data can be written to the bu ffer register at any time. there are five pwm duty and carrier cycle registers that have buffer registers and can be updated during operation. there is a temporary register between each of these registers and its buffer register. when subcounter tcnts is not counting, if buffer regi ster data is updated, the temporary register value is also rewritten. transfer is not performed from buffer registers to temporary registers when tcnts is counting; in this case, the value wr itten to a buffer regist er is transferred after tcnts halts. the temporary register value is tr ansferred to the compare register at the data update timing set with bits md3 to md0 in the timer mode register (tmdr). figure 11.37 shows an example of data updating in complementary pwm mode. th is example shows the mode in which data updating is performed at both the counter crest and trough. when rewriting buffer register data, a write to tgrd_4 must be performed at the end of the update. data transfer from the buffer regist ers to the temporary registers is performed simultaneously for all five registers after the write to tgrd_4. a write to tgrd_4 must be performed after writin g data to the registers to be updated, even when not updating all five registers, or when updating the tgrd_4 data. in this case, the data written to tgrd_4 should be the same as the data prior to the write operation. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 296 of 882 rej09b0108-0400 data update timing: c ounter c rest and trough transfer from temporary re g ister to compare re g ister transfer from temporary re g ister to compare re g ister transfer from temporary re g ister to compare re g ister transfer from temporary re g ister to compare re g ister transfer from temporary re g ister to compare re g ister transfer from temporary re g ister to compare re g ister counter value tgra_3 tgrc_4 tgra_4 h'0000 br data1 data2 data3 data4 data5 data6 data1 data1 data2 data3 data4 data6 data2 data3 data4 data5 data6 temp_r gr time : compare re g ister : buffer re g ister figure 11.37 example of data update in complementary pwm mode 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 297 of 882 rej09b0108-0400 8. initial output in complementary pwm mode: in complementary pwm mode, the initial output is determined by the setting of bits olsn and olsp in the timer output control register (tocr). this initial output is the pwm pulse non-active level, and is output from when complementary pwm mode is set with the timer mode register (tmdr) until tcnt_4 exceeds the value set in the dead time register (tddr). figure 11.38 shows an example of the initial output in complementary pwm mode. an example of the waveform when the initial pwm duty value is smaller than the tddr value is shown in figure 11.39. timer output c ontrol register settings olsn bit: 0 (initial output: hi g h; active level: low) olsp bit: 0 (initial output: hi g h; active level: low) tcnt3, 4 value tgr4_a tddr tcnt_3 tcnt_4 initial output dead time time active level active level tcnt3, 4 count start (tstr settin g ) complementary pwm mode (tmdr settin g ) positive phase output ne g ative phase output figure 11.38 example of initial output in complementary pwm mode (1) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 298 of 882 rej09b0108-0400 timer output c ontrol register settings olsn bit: 0 (initial output: hi g h; active level: low) olsp bit: 0 (initial output: hi g h; active level: low) tcnt_3, 4 value tgra_4 tddr tcnt_3 tcnt_4 initial output time active level tcnt_3, 4 count start (tstr settin g ) complementary pwm mode (tmdr settin g ) positive phase output ne g ative phase output figure 11.39 example of initial output in complementary pwm mode (2) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 299 of 882 rej09b0108-0400 9. complementary pwm mode pwm output generation method: in complementary pwm mode, 3-phase output is performed of pwm waveforms with a non- overlap time between the positive and negative phases. this non-overlap time is called the dead time. a pwm waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a co unter and data register. while tcnts is counting, data register and temporary register values are si multaneously compared to create consecutive pw m pulses from 0 to 100%. the relative timing of on and off compare- match occurrence may vary, but the compare-matc h that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. figures 11.40 to 11.42 show examples of waveform generation in complementary pwm mode. the positive phase/negative phase off timing is generated by a compare-match with the solid- line counter, and the on timing by a compare-matc h with the dotted-line counter operating with a delay of the dead time behind the solid-lin e counter. in the t1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. in the t2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. in normal cases, compare-matches occur in the order a b c d (or c d a' b' ), as shown in figure 11.40. if compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. if compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. if compare-match c occurs first following compare-match a , as shown in figure 11.41, compare-match b is ignored, and the negative phas e is turned off by compare-match d . this is because turning off of the pos itive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). similarly, in the example in figure 11.42, compare-match a' with the new data in the temporary register occurs before compare-match c , but other compare-matches occurring up to c , which turns off the positive phase, are ignored. as a result, the positive phase is not turned on. thus, in complementary pwm mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matc hes that occur before a turn -off timing compare-match are ignored. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 300 of 882 rej09b0108-0400 t2 period t1 period t1 period ab c a' b' d tgr3a_3 tcdr tddr h'0000 positive phase ne g ative phase figure 11.40 example of complementary pwm mode waveform output (1) t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase ne g ative phase c d a a b b figure 11.41 example of complementary pwm mode waveform output (2) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 301 of 882 rej09b0108-0400 ab c a' b' d t1 period t2 period t1 period tgra_3 tcdr tddr h'0000 positive phase ne g ative phase figure 11.42 example of complementary pwm mode waveform output (3) a b c d a' b' t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase ne g ative phase figure 11.43 example of complementary pwm mode 0% and 100% waveform output (1) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 302 of 882 rej09b0108-0400 t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase ne g ative phase a c d a b b figure 11.44 example of complementary pwm mode 0% and 100% waveform output (2) t2 period t1 period t1 period a b c d tgra_3 tcdr tddr h'0000 positive phase ne g ative phase figure 11.45 example of complementary pwm mode 0% and 100% waveform output (3) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 303 of 882 rej09b0108-0400 tgra_3 tcdr tddr h'0000 positive phase ne g ative phase t2 period t1 period t1 period a b c b' d a' figure 11.46 example of complementary pwm mode 0% and 100% waveform output (4) cad b t2 period t1 period t1 period tgra_3 tcdr tddr h'0000 positive phase ne g ative phase figure 11.47 example of complementary pwm mode 0% and 100% waveform output (5) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 304 of 882 rej09b0108-0400 10. complementary pwm mode 0% and 100% duty output: in complementary pwm mode, 0% and 100% duty cycles can be output as required. figures 11.43 to 11.47 show output examples. 100% duty output is performed when the data register value is set to h'0000. the waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as tg ra_3. the waveform in this case has a positive phase with a 100% off-state. on and off compare-matches occur simultaneously, but if a turn-on compare-match and turn- off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. 11. toggle output synchronized with pwm cycle in complementary pwm mode, toggle output can be performed in synchronization with the pwm carrier cycle by setting the psye bit to 1 in the timer output control register (tocr). an example of a toggle output waveform is shown in figure 11.48. this output is toggled by a compare-match between tcnt_3 and tg ra_3 and a compare- match between tcnt4 and h'0000. the output pin for this toggle output is the tioc3a pin. the initial output is 1. tgra_3 h'0000 to gg le output tioc3a pin tcnt_4 tcnt_3 figure 11.48 example of toggle output waveform synchronized with pwm output 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 305 of 882 rej09b0108-0400 12. counter clearing by another channel in complementary pwm mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (tsyr), and selecting synchronous clearing with bits cclr2 to cclr0 in the timer control register (tcr), it is possible to have tcnt_3, tcnt_4, and tcnts cleared by another channel. figure 11.49 illustrates the operation. use of this function enables counter clearing and restarting to be performed by means of an external signal. tgra_3 tcdr tddr h'0000 channel 1 input capture a tcnt_1 tcnt_3 tcnt_4 tcnts syn c hronous c ounter c learing by c hannel 1 input c apture a figure 11.49 counter clearing sy nchronized with another channel 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 306 of 882 rej09b0108-0400 13. example of ac synchronous motor (brushless dc motor) drive waveform output in complementary pwm mode, a brushless dc motor can easily be controlled using the timer gate control register (tgcr). figures 11.50 to 11.53 show examples of brushless dc motor drive waveforms created using tgcr. when output phase switching for a 3-phase brushless dc motor is performed by means of external signals detected with a hall element, etc ., clear the fb bit in tgcr to 0. in this case, the external signals indicating the polarity position are input to channel 0 timer input pins tioc0a, tioc0b, and tioc0c (set with pfc). when an edge is detected at pin tioc0a, tioc0b, or tioc0c, the output on/off state is switched automatically. when the fb bit is 1, the output on/off state is switched when the uf, vf, or wf bit in tgcr is cleared to 0 or set to 1. the drive waveforms are output from the complementary pwm mode 6-phase output pins. with this 6-phase output, in the case of on output, it is possible to use complementary pwm mode output and perform chopping output by setting the n bit or p bit to 1. when the n bit or p bit is 0, level output is selected. the 6-phase output active level (on output level) can be set with the olsn and olsp bits in the timer output control register (tocr) rega rdless of the setting of the n and p bits. external input tioc0a pin tioc0b pin tioc0c pin tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 0, p = 0, fb = 0, output a c tive level = high figure 11.50 example of output ph ase switching by external input (1) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 307 of 882 rej09b0108-0400 external input tioc0a pin tioc0b pin tioc0c pin tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 1, p = 1, fb = 0, output a c tive level = high figure 11.51 example of output ph ase switching by external input (2) tgcr uf bit vf bit wf bit tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 0, p = 0, fb = 1, output a c tive level = high figure 11.52 example of output phase switching by means of uf, vf, wf bit settings (1) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 308 of 882 rej09b0108-0400 tgcr uf bit vf bit wf bit tioc3b pin tioc3d pin tioc4a pin tioc4c pin tioc4b pin tioc4d pin 6-phase output when bdc = 1, n = 1, p = 1, fb = 1, output a c tive level = high figure 11.53 example of output phase switching by means of uf, vf, wf bit settings (2) 14. a/d conversion start request setting: in complementary pwm mode, an a/d convers ion start request can be issued using a tgra_3 compare-match or a compare-match on a channel other than channels 3 and 4. when start requests using a tgra_3 compare-matc h are set, a/d conversion can be started at the center of the pwm pulse. a/d conversion start requests can be set by setting the ttge bit to 1 in the timer interrupt enable register (tier). 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 309 of 882 rej09b0108-0400 complementary pwm mode output protection function: complementary pwm mode output has the following protection functions. 1. register and counter miswrite prevention function with the exception of the buffe r registers, which can be rewr itten at any time, access by the cpu can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary pwm mode by means of the mturwe bit in the bus controller?s bus control register 1 (bcr1). the applicable registers are some (21 in total) of the registers in channels 3 and 4 shown in the following: ? tcr_3 and tcr_4, tmdr_3 and tmdr_4, tiorh_3 and tiorh_4, tiorl_3 and tiorl_4, tier_3 and tier_4, tcnt_3 and tcnt_4, tgra_3 and tgra_4, tgrb_3 and tgrb_4, toer, tocr, tgcr, tcdr, and tddr. this function enables miswriting due to cpu runaway to be prevented by disabling cpu access to the mode registers, c ontrol registers, and counters. when the applicable registers are read in the access-disabled stat e, undefined values are returned. writing to these registers is ignored. 2. halting of pwm output by external signal the 6-phase pwm output pins can be set auto matically to the high -impedance state by inputting specified external signals. ther e are four external signal input pins. see section 11.9, port output enable (poe), for details. 3. halting of pwm output when oscillator is stopped if it is detected that the clock input to this lsi has stopped, the 6-phase pwm output pins automatically go to the high-imp edance state. the pin states ar e not guaranteed when the clock is restarted. see section 4.2, function for detecting oscillator halt. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 310 of 882 rej09b0108-0400 11.5 interrupt sources 11.5.1 interrupt sou rces and priorities there are three kinds of mtu interrupt source; tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by cl earing the status flag to 0. relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. for details, s ee section 6, interrupt controller (intc). table 11.42 lists the mtu interrupt sources. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 311 of 882 rej09b0108-0400 table 11.42 mtu interrupts channel name interrupt source interrupt flag dmac activation dtc activation priority 0 tgia_0 tgra_0 input capture/compar e match tgfa_0 possi ble possible high tgib_0 tgrb_0 input capture/compare match tgfb_0 not pos sible possible tgic_0 tgrc_0 input capture/compare match tgfc_0 not possible possible tgid_0 tgrd_0 input capture/compare match tgfd_0 not possible possible tciv_0 tcnt_0 overflow tcfv _0 not possible not possible 1 tgia_1 tgra_1 input capture/compar e match tgfa_1 possible possible tgib_1 tgrb_1 input capture/compare match tgfb_1 not pos sible possible tciv_1 tcnt_1 overflow tcfv _1 not possible not possible tciu_1 tcnt_1 underflow tcfu_1 not possible not possible 2 tgia_2 tgra_2 input capture/compar e match tgfa_2 possible possible tgib_2 tgrb_2 input capture/compare match tgfb_2 not pos sible possible tciv_2 tcnt_2 overflow tcfv _2 not possible not possible tciu_2 tcnt_2 underflow tcfu_2 not possible not possible 3 tgia_3 tgra_3 input capture/compar e match tgfa_3 possible possible tgib_3 tgrb_3 input capture/compare match tgfb_3 not pos sible possible tgic_3 tgrc_3 input capture/compare match tgfc_3 not possible possible tgid_3 tgrd_3 input capture/compare match tgfd_3 not possible possible tciv_3 tcnt_3 overflow tcfv _3 not possible not possible 4 tgia_4 tgra_4 input capture/compar e match tgfa_4 possible possible tgib_4 tgrb_4 input capture/compare match tgfb_4 not pos sible possible tgic_4 tgrc_4 input capture/compare match tgfc_4 not possible possible tgid_4 tgrd_4 input capture/compare match tgfd_4 not possible possible tciv_4 tcnt_4 overflow/underflow tcfv_4 not possible possible low note: this table shows the initia l state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 312 of 882 rej09b0108-0400 input capture/compar e match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tg r input capture/compare match on a particular channel. the interrupt reques t is cleared by clearing the tgf flag to 0. the mtu has 16 input capture/compare match interrupts , four each for channels 0, 3, and 4, and two each for channels 1 and 2. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the mtu has five overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing th e tcfu flag to 0. the mtu has two underflow interrupts, one each for channels 1 and 2. 11.5.2 dtc/dmac activation dtc activation: the dtc can be activated by the tgr in put capture/compare match interrupt in each channel. for details, see section 8, data transfer controller (dtc). a total of 17 mtu input capture/compare match in terrupts can be used as dtc activation sources, four each for channels 0 and 3, and two each fo r channels 1 and 2, and five for channel 4. dmac activation: the dmac can be activated by the tgra input capture/compare match interrupt in each channel. for details, see sec tion 10, direct memory access controller (dmac). a total of five mtu input capture/compare match interrupts can be used as dmac activation sources, one for each channel. 11.5.3 a/d converter activation the a/d converter can be activat ed by the tgra input capture/ compare match in each channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the mtu conversion start trigger has been selected on the a/d converter at this time, a/d conversion starts. in the mtu, a total of five tgra input capture/compare match interrupts can be used as a/d converter conversion start sour ces, one for each channel. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 313 of 882 rej09b0108-0400 11.6 operation timing 11.6.1 input/output timing tcnt count timing: figure 11.54 shows tcnt count timing in internal clock operation, and figure 11.55 shows tcnt count timing in external clock operation (normal mode), and figure 11.56 shows tcnt count timing in external clock operation (phase counting mode). tcnt tcnt input clock internal clock p n-1 n n+1 n+2 fallin g ed g e risin g ed g e figure 11.54 count timing in internal clock operation tcnt tcnt input clock external clock p n-1 n n+1 n+2 fallin g ed g e risin g ed g e fallin g ed g e figure 11.55 count timing in external clock operation p external clock tcnt input clock tcnt fallin g ed g e fallin g ed g e risin g ed g e n-1 n n+1 figure 11.56 count timing in external clock operation (phase counting mode) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 314 of 882 rej09b0108-0400 output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin (tioc pin). after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 11.57 shows output compare output timing (normal mode and pwm mode) and figure 11.58 shows output compare output timing (complementary pwm mode and reset synchronous pwm mode). tgr tcnt tcnt input clock n n n+1 compare match si g nal tioc pin p figure 11.57 output compare output timing (normal mode/pwm mode) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 315 of 882 rej09b0108-0400 p tcnt input clock tcnt n n+1 tgr compare match si g nal tioc pin n figure 11.58 output compare output timing (complementary pwm mode/reset synchronous pwm mode) input capture si gnal timing: figure 11.59 shows input capture signal timing. tcnt input capture input n n+1 n+2 n n+2 tgr input capture si g nal p figure 11.59 input capture input signal timing 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 316 of 882 rej09b0108-0400 timing for counter clearing by compare match/input capture: figure 11.60 shows the timing when counter clearing on compare match is specified, and figure 11.61 shows the timing when counter clearing on input capture is specified. tcnt counter clear si g nal compare match si g nal tgr n n h'0000 p figure 11.60 counter clea r timing (compare match) tcnt counter clear si g nal input capture si g nal tgr n h'0000 n p figure 11.61 counter clear timing (input capture) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 317 of 882 rej09b0108-0400 buffer operation timing: figures 11.62 and 11.63 show the timing in buffer operation. tgra, tgrb compare match buffer si g nal tcnt tgrc, tgrd n n n n n+1 p figure 11.62 buffer operation timing (compare match) tgra, tgrb tcnt input capture si g nal tgrc, tgrd n n n n+1 n n n+1 p figure 11.63 buffer operation timing (input capture) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 318 of 882 rej09b0108-0400 11.6.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 11.64 shows the timing for setting of the tgf flag in tsr on compare match, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n n n+1 compare match si g nal tgf fla g tgi interrupt p figure 11.64 tgi interrupt timing (compare match) tgf flag setting timing in case of input capture: figure 11.65 shows the timing for setting of the tgf flag in tsr on input capture, and tgi interrupt request signal timing. tgr tcnt input capture si g nal n n tgf fla g tgi interrupt p figure 11.65 tgi interrupt timing (input capture) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 319 of 882 rej09b0108-0400 tcfv flag/tcfu flag setting timing: figure 11.66 shows the timing for setting of the tcfv flag in tsr on overflow, and tciv interrupt request signal timing. figure 11.67 shows the timing for setting of the tcfu flag in tsr on underflow, and tciu interrupt request signal timing. overflow si g nal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv fla g tciv interrupt p figure 11.66 tciv interrupt setting timing underflow si g nal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu fla g tciu interrupt p figure 11.67 tciu interrupt setting timing 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 320 of 882 rej09b0108-0400 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc/dmac is activated, the fl ag is cleared automatically. figure 11.68 shows the timing for status flag cleari ng by the cpu, and figure 11.69 shows the timing for status flag clearing by the dtc/dmac. status fla g write si g nal address tsr address interrupt request si g nal tsr write cycle t1 t2 p figure 11.68 timing for st atus flag clearing by cpu interrupt request si g nal status fla g address source address dtc/dmac read cycle t1 t2 destination address t1 t2 dtc/dmac write cycle p figure 11.69 timing for status flag clearing by dtc/dmac activation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 321 of 882 rej09b0108-0400 11.7 usage notes 11.7.1 module standby mode setting mtu operation can be disabled or enabled using the module standby register. the initial setting is for mtu operation to be halted. register access is enabled by clearing module standby mode. for details, refer to section 24, power-down modes. 11.7.2 input clock restrictions the input clock pulse width must be at least 1.5 st ates in the case of single-edge detection, and at least 2.5 states in the case of both-edge detecti on. the mtu will not operate properly at narrower pulse widths. in phase counting mode, the phase difference and ove rlap between the two inpu t clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 11.70 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 11.70 phase difference, overlap, an d pulse width in phase counting mode 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 322 of 882 rej09b0108-0400 11.7.3 caution on period setting when counter clearing on compare match is set, tc nt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = p (n + 1) where f: counter frequency p : peripheral clock operating frequency n: tgr set value 11.7.4 contention between tc nt write and clear operations if the counter clear signal is generated in the t2 state of a tcnt write cy cle, tcnt clearing takes precedence and the tcnt write is not performed. figure 11.71 shows the timing in this case. counter clear si g nal write si g nal address p tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 11.71 contention between tcnt write and clear operations 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 323 of 882 rej09b0108-0400 11.7.5 contention be tween tcnt write and increment operations if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 11.72 shows the timing in this case. tcnt input clock write si g nal address p tcnt address tcnt tcnt write cycle t1 t2 nm tcnt write data figure 11.72 contention between tcnt write and increment operations 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 324 of 882 rej09b0108-0400 11.7.6 contention between tgr write and compare match if a compare match occurs in the t2 state of a tg r write cycle, the tgr wr ite is executed and the compare match signal is also generated. figure 11.73 shows the timing in this case. compare match si g nal write si g nal address p tgr address tcnt tgr write cycle t1 t2 nm tgr write data tgr n n+1 figure 11.73 contention betw een tgr write and compare match 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 325 of 882 rej09b0108-0400 11.7.7 contention between buffer register write and compare match if a compare match occurs in the t2 state of a tgr write cycle, the data that is transferred to tgr by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write. figures 11.74 and 11.75 show the timing in this case. compare match buffer si g nal write si g nal address p buffer re g ister address buffer re g ister tgr write cycle t1 t2 compare match si g nal tgr nm m buffer re g ister write data figure 11.74 contention between buffer re gister write and compa re match (channel 0) 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 326 of 882 rej09b0108-0400 p address write si g nal compare match si g nal compare match buffer si g nal tgr write cycle t1 t2 buffer re g ister address n n m buffer re g ister write data buffer re g ister tgr figure 11.75 contention between bu ffer register write and compare match (channels 3 and 4) 11.7.8 contention between tgr read and input capture if an input capture signal is generated in the t1 stat e of a tgr read cycle, the data that is read will be that in the buffer af ter input capture transfer. figure 11.76 shows the timing in this case. input capture si g nal read si g nal address p tgr read cycle t1 t2 tgr x m m internal data bus tgr address figure 11.76 contention between tgr read and input capture 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 327 of 882 rej09b0108-0400 11.7.9 contention between tgr write and input capture if an input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the wr ite to tgr is not performed. figure 11.77 shows the timing in this case. input capture si g nal write si g nal address p tcnt tgr write cycle t1 t2 m tgr m tgr address figure 11.77 contention betw een tgr write and input capture 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 328 of 882 rej09b0108-0400 11.7.10 contention between buffer register write and input capture if an input capture signal is generated in the t2 st ate of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 11.78 shows the timing in this case. input capture si g nal write si g nal address p tcnt buffer re g ister write cycle t1 t2 n tgr n m m buffer re g ister buffer re g ister address figure 11.78 contention between bu ffer register write and input capture 11.7.11 tcnt2 write and overflow/underflow contention in cascade connection with timer counters tcnt1 and tcnt2 in a cascade connection, when a contention occurs during tcnt_1 count (during a tcnt_2 overflow/underflow) in the t 2 state of the tcnt_2 write cycle, the write to tcnt_2 is conducted, and the tcnt_1 count signal is disabled. at this point, if there is match with tgra_1 and th e tcnt_1 value, a compare signal is issued. furthermore, when the tcnt_1 count clock is sel ected as the input capture source of channel 0, tgra_0 to d_0 carry out the input capture operation. in addition, when the compare match/input capture is selected as the input capture sour ce of tgrb_1, tgrb_1 carries out input capture operation. the timing is shown in figure 11.79. for cascade connections, be sure to synchronize settings for channels 1 and 2 when setting tcnt clearing. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 329 of 882 rej09b0108-0400 t1 t2 h'fffe h'ffff n n + 1 h'ffff m m n p qp m disabled tcnt_2 write data tcnt_2 address tcnt write cycle p address write si g nal tcnt_2 tgra_2 to tgrb_2 ch2 compare- match si g nal a/b tcnt_1 input clock tcnt_1 tgra_1 ch1 compare- match si g nal a tgrb_1 ch1 input capture si g nal b tcnt_0 tgra_0 to tgrd_0 ch0 input capture si g nal a to d figure 11.79 tcnt_2 write and overflow/underflow contention with cascade connection 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 330 of 882 rej09b0108-0400 11.7.12 counter value during co mplementary pwm mode stop when counting operation is suspended with tcnt_3 and tcnt_4 in complementary pwm mode, tcnt_3 has the timer dead time register (tddr) value, and tcnt_4 is held at h'0000. when restarting complementary pwm mode, countin g begins automatically from the initialized state. this explanatory diagram is shown in figure 11.80. when counting begins in another operating mode, be sure that tcnt_3 and tcnt_4 are set to the initial values. tgra_3 tcdr tddr h'0000 tcnt_3 tcnt_4 complementary pwm mode operation complementary pwm mode operation counter operation stop complementary pmw restart figure 11.80 counter value during complementary pwm mode stop 11.7.13 buffer operation setting in complementary pwm mode in complementary pwm mode, conduct rewrites by buffer operation for the pwm cycle setting register (tgra_3), timer cycle data register (tcdr), and duty setting registers (tgrb_3, tgra_4, and tgrb_4). in complementary pwm mode, channel 3 and chan nel 4 buffers operate in accordance with bit settings bfa and bfb of tmdr_3. when tmdr_3?s bfa bit is set to 1, tgrc_3 functions as a buffer register for tgra_3. at the same time, tgrc_4 functions as the buffer register for tgra_4, while the tcbr functions as the tcdr?s buffer register. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 331 of 882 rej09b0108-0400 11.7.14 reset sync pwm mode buffer operation and compare match flag when setting buffer operation for reset sync pw m mode, set the bfa and bfb bits of tmdr_4 to 0. the tioc4c pin will be unable to produce its waveform output if the bfa bit of tmdr_4 is set to 1. in reset sync pwm mode, the channel 3 and channel 4 buffers operate in accordance with the bfa and bfb bit settings of tmdr_3. for example, if the bfa bit of tmdr_3 is set to 1, tgrc_3 functions as the buffer register for tgra_3. at the same time, tgrc_4 functions as the buffer register for tgra_4. the tgfc bit and tgfd bit of tsr_3 and tsr_4 are not set when tgrc_3 and tgrd_3 are operating as buffer registers. figure 11.81 shows an example of operations for tgr_3, tgr_4, tioc3, and tioc4, with tmdr_3?s bfa and bfb bits set to 1, and tmdr_4?s bfa and bfb bits set to 0. tgra_3 tgrc_3 tgrb_3, tgra_4, tgrb_4 tgrd_3, tgrc_4, tgrd_4 h'0000 tioc3a tioc3b tioc3d tioc4a tioc4c tioc4b tioc4d tgfc tgfd tgra_3, tgrc_3 tgrb_3, tgrd_3, tgra_4, tgrc_4, tgrb_4, tgrd_4 buffer transfer with compare match a3 tcnt3 not set not set point a point b figure 11.81 buffer operation and compare-match flags in reset synchronous pwm mode 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 332 of 882 rej09b0108-0400 11.7.15 overflow flags in reset synchronous pwm mode when set to reset synchronous pwm mode, tcnt_3 and tcnt_4 start counting when the cst3 bit of tstr is set to 1. at this point, tcnt_4?s count clock source and count edge obey the tcr_3 setting. in reset synchronous pwm mode, with cycle re gister tgra_3?s set va lue at h'ffff, when specifying tgr3a compare-match for the counter clear source, tcnt_3 and tcnt_4 count up to h'ffff, then a compare-match occurs with tgra_3, and tcnt_3 and tcnt_4 are both cleared. at this point, tsr?s overflow flag tcfv bit is not set. figure 11.82 shows a tcfv bit operation example in reset synchronous pwm mode with a set value for cycle register tgra_3 of h'ffff, when a tgra_3 compare-match has been specified without synchronous setting for the counter clear source. tgra_3 (h'ffff) h'0000 tcfv_3 tcfv_4 tcnt_3 = tcnt_4 counter cleared by compare match 3a not set not set figure 11.82 reset synchronous pwm mode overflow flag 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 333 of 882 rej09b0108-0400 11.7.16 contention between overflo w/underflow and counter clearing if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 11.83 shows the operation timing when a tgr compare match is sp ecified as the clearing source, and when h'ff ff is set in tgr. counter clear si g nal tcnt tcnt input clock p h'ffff h'0000 tgf tcfv disabled figure 11.83 contention between overflow and co unter clearing 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 334 of 882 rej09b0108-0400 11.7.17 contention between tcnt write and overflow/underflow if there is an up-count or down-count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set. figure 11.84 shows the operation timing when there is contention between tcnt write and overflow. write si g nal address p tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv fla g figure 11.84 contention betw een tcnt write and overflow 11.7.18 cautions on transition from normal operation or pwm mode 1 to reset- synchronous pwm mode when making a transition from channel 3 or 4 normal operation or pwm mode 1 to reset- synchronous pwm mode, if the counter is halted with the output pins (tioc3b, tioc3d, tioc4a, tioc4c, tioc4b, tioc4d) in the high-imp edance state, followed by the transition to reset-synchronous pwm mode and operation in that mode, the initial pin output will not be correct. when making a transition from normal operation to reset-synchronous pwm mode, write h'11 to registers tiorh_3, tiorl_3, tiorh_4, and tiorl_4 to initialize the output pins to low level output, then set an initial register value of h'00 before making the mode transition. when making a transition from pwm mode 1 to reset-synchronous pwm mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of h'00 before making the transition to reset-synchronous pwm mode. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 335 of 882 rej09b0108-0400 11.7.19 output level in complementary pw m mode and reset-synchronous pwm mode when channels 3 and 4 are in complementary pwm mode or reset-synchronous pwm mode, the pwm waveform output level is set with the olsp and olsn bits in the timer output control register (tocr). in the case of complementary pwm mode or reset-synchronous pwm mode, tior should be set to h'00. 11.7.20 interrupts in module standby mode if module standby mode is entered when an interrup t has been requested, it will not be possible to clear the cpu interrupt source or the dtc/dmac activation source. interrupts should therefore be disabled before entering module standby mode. 11.7.21 simultaneous capture of tcnt _1 and tcnt_2 in cascade connection when timer counters 1 and 2 (tcnt_1 and tcnt_2) are operated as a 32-bit counter in cascade connection, the cascade counter value cannot be ca ptured successfully even if input-capture input is simultaneously done to tioc1a and tioc2a or to tioc1b an d tioc2b. this is because the input timing of tioc1a and tioc2a or of tioc1b and tioc2b may not be the same when external input-capture signals to be input into tcnt_1 and tcnt_2 are taken in synchronization with the internal clock. for example, tcnt_1 (the counter for upper 16 bits) does not capture the count-up value by overflow from tcnt_2 (the counter for lower 16 bits) but captures the count value before the count-up. in this case, the values of tcnt_1 = h'fff1 and tcnt_2 = h'0000 should be transferred to tgra_1 and tgra_2 or to tgrb_1 and tgrb_2, but the values of tcnt_1 = h'fff0 and tcnt_2 = h'0000 are erroneously transferred. 11.7.22 note on buffer operation setting when enabling buffer operation, clear to 0 bits tgiec and tg ied (corresponding to tgrc and tgrd, which are used as buffer registers) in the timer interrupt enable register (tier). 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 336 of 882 rej09b0108-0400 11.8 mtu output pin initialization 11.8.1 operating modes the mtu has the following six operating modes. waveform output is possible in all of these modes. ? normal mode (channels 0 to 4) ? pwm mode 1 (channels 0 to 4) ? pwm mode 2 (channels 0 to 2) ? phase counting modes 1 to 4 (channels 1 and 2) ? complementary pwm mode (channels 3 and 4) ? reset-synchronous pwm mode (channels 3 and 4) the mtu output pin initialization method for each of these modes is described in this section. 11.8.2 reset start operation the mtu output pins (tioc*) are initialized low by a reset and in standby mode. since mtu pin function selection is performed by the pin functio n controller (pfc), when the pfc is set, the mtu pin states at that point are output to the ports. when mtu output is selected by the pfc immediately after a reset, the mtu output initial level, low, is output directly at the port. when the active level is low, the system will operate at this point, and therefore the pfc setting should be made after initialization of the mtu output pins is completed. note: channel number and port notation are substituted for *. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 337 of 882 rej09b0108-0400 11.8.3 operation in case of re-setting due to error during operation, etc. if an error occurs during mtu operation, mtu output should be cut by the system. cutoff is performed by switching the pin output to port output with the pfc and outputting the inverse of the active level. for large-current pins, output can also be cut by hardware, using port output enable (poe). the pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. the mtu has six operating modes, as stated above. there are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. possible mode transition combinations are shown in table 11.43. table 11.43 mode transition combinations after before normal pwm1 pwm2 pcm cpwm rpwm normal (1) (2) (3) (4) (5) (6) pwm1 (7) (8) (9) (10) (11) (12) pwm2 (13) (14) (15) (16) none none pcm (17) (18) (19) (20) none none cpwm (21) (22) none none (23) (24) (25) rpwm (26) (27) none none (28) (29) [legend] normal: normal mode pwm1: pwm mode 1 pwm2: pwm mode 2 pcm: phase counting modes 1 to 4 cpwm: complementary pwm mode rpwm: reset-synchronous pwm mode 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 338 of 882 rej09b0108-0400 11.8.4 overview of initialization procedures and mode transitions in case of error during operation, etc. ? when making a transition to a mode (normal, pwm1, pwm2, pcm) in which the pin output level is selected by the timer i/o control register (tior) setting, initialize the pins by means of a tior setting. ? in pwm mode 1, since a waveform is not output to the tioc*b (tioc *d) pin, setting tior will not initialize the pins. if initialization is required, carry it out in normal mode, then switch to pwm mode 1. ? in pwm mode 2, since a waveform is not output to the cycle register pin, setting tior will not initialize the pins. if initialization is requir ed, carry it out in normal mode, then switch to pwm mode 2. ? in normal mode or pwm mode 2, if tgrc an d tgrd operate as buffer registers, setting tior will not initialize the buffer register pins. if initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. ? in pwm mode 1, if either tgrc or tgrd operates as a buffer register, setting tior will not initialize the tgrc pin. to initialize the tgrc pin, clear buffer mode, carry out initialization, then set buffer mode again. ? when making a transition to a mode (cpwm, rpwm) in which the pin output level is selected by the timer output control register (tocr) setting, switch to normal mode and perform initialization with tior, then restore ti or to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (toer). then operate the unit in accordance with the m ode setting procedure (tocr se tting, tmdr setting, toer setting). note: channel number is substituted for * indicated in this article. pin initialization procedures are described below for the numbered combinations in table 11.43. the active level is assumed to be low. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 339 of 882 rej09b0108-0400 operation when error occurs during normal mode operation, and op eration is restarted in normal mode: figure 11.85 shows an explanatory diag ram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen n=0 to 15 hi-z hi-z figure 11.85 error occurrence in normal mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the hi gh-impedance state. 2. after a reset, the tmdr setting is for normal mode. 3. for channels 3 and 4, enable output with toer before initializing the pins with tior. 4. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. output goes low on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. not necessary when restarting in normal mode. 11. the count operation is stopped by tstr. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 340 of 882 rej09b0108-0400 operation when error occurs during normal mode operation, and op eration is restarted in pwm mode 1: figure 11.86 shows an explanatory diag ram of the case where an error occurs in normal mode and operation is restar ted in pwm mode 1 after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (tioc * b) n=0 to 15 hi-z hi-z figure 11.86 error occurrence in normal mode, recovery in pwm mode 1 1 to 10 are the same as in figure 11.85. 11. set pwm mode 1. 12. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized. if initialization is required, initialize in no rmal mode, then switch to pwm mode 1.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 341 of 882 rej09b0108-0400 operation when error occurs during normal mode operation, and op eration is restarted in pwm mode 2: figure 11.87 shows an explanatory diag ram of the case where an error occurs in normal mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm2) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (cycle re g ister) n=0 to 15 hi-z hi-z figure 11.87 error occurrence in normal mode, recovery in pwm mode 2 1 to 10 are the same as in figure 11.85. 11. set pwm mode 2. 12. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized. if initialization is required, initialize in norm al mode, then switch to pwm mode 2.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: pwm mode 2 can only be set for channels 0 to 2, and therefore toer setting is not necessary. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 342 of 882 rej09b0108-0400 operation when error occurs during normal mode operation, and op eration is restarted in phase counting mode: figure 11.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pcm) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen n=0 to 15 hi-z hi-z figure 11.88 error occurrence in normal mode, recovery in phase counting mode 1 to 10 are the same as in figure 11.85. 11. set phase counting mode. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: phase counting mode can only be set for ch annels 1 and 2, and therefore toer setting is not necessary. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 343 of 882 rej09b0108-0400 operation when error occurs during normal mode operation, and op eration is restarted in complementary pwm mode: figure 11.89 shows an explanat ory diagram of the case where an error occurs in normal mode and operation is restarted in complementary pwm mode after re- setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tior (0 init 0 out) 12 tior ( disabled ) 13 toer (0) 14 tocr 15 tmdr (cpwm) (16) toer (1) (17) pfc (mtu) (18) tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.89 error occurrence in normal mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 11.85. 11. initialize the normal mode waveform generation section with tior. 12. disable operation of the normal mode waveform generation section with tior. 13. disable channel 3 and 4 output with toer. 14. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 15. set complementary pwm. 16. enable channel 3 and 4 output with toer. 17. set mtu output with the pfc. 18. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 344 of 882 rej09b0108-0400 operation when error occurs during normal mode operation, and op eration is restarted in reset-synchronous pwm mode: figure 11.90 shows an explan atory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous pwm mode after re-setting. 1 reset 2 tmdr (normal) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tior (0 init 0 out) 12 tior ( disabled ) 13 toer (0) 14 tocr 15 tmdr (cpwm) 16 toer (1) 17 pfc (mtu) 18 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.90 error occurrence in normal mode, recovery in reset-synchronous pwm mode 1 to 13 are the same as in figure 11.89. 14. select the reset-synchronous pwm output level and cyclic output enabling/disabling with tocr. 15. set reset-synchronous pwm. 16. enable channel 3 and 4 output with toer. 17. set mtu output with the pfc. 18. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 345 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 1 operation, and operation is restarted in normal mode: figure 11.91 shows an explanatory diag ram of the case where an error occurs in pwm mode 1 and operation is restar ted in normal mode after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (tioc * b) n=0 to 15 hi-z hi-z figure 11.91 error occurrence in pwm mode 1, recovery in normal mode 1. after a reset, mtu output is low and ports are in the hi gh-impedance state. 2. set pwm mode 1. 3. for channels 3 and 4, enable output with toer before initializing the pins with tior. 4. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 1, the tioc*b side is not initialized.) 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. output goes low on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. the count operation is stopped by tstr. 11. set normal mode. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 346 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 1 operation, and operation is restarted in pwm mode 1: figure 11.92 shows an explanatory diag ram of the case where an error occurs in pwm mode 1 and operation is restar ted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (tioc * b) not initialized (tioc * b) n=0 to 15 hi-z hi-z figure 11.92 error occurrence in pwm mode 1, recovery in pwm mode 1 1 to 10 are the same as in figure 11.91. 11. not necessary when restarting in pwm mode 1. 12. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 347 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 1 operation, and operation is restarted in pwm mode 2: figure 11.93 shows an explanatory diag ram of the case where an error occurs in pwm mode 1 and operation is restar ted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm2) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (tioc * b) not initialized (cycle re g ister) n=0 to 15 hi-z hi-z figure 11.93 error occurrence in pwm mode 1, recovery in pwm mode 2 1 to 10 are the same as in figure 11.91. 11. set pwm mode 2. 12. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: pwm mode 2 can only be set for channels 0 to 2, and therefore toer setting is not necessary. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 348 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 1 operation, and operation is restarted in phase counting mode: figure 11.94 shows an explanatory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in phase counting mode after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pcm) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (tioc * b) n=0 to 15 hi-z hi-z figure 11.94 error occurrence in pwm mode 1, recovery in phase counting mode 1 to 10 are the same as in figure 11.91. 11. set phase counting mode. 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. note: phase counting mode can only be set for ch annels 1 and 2, and therefore toer setting is not necessary. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 349 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 1 operation, and operation is restarted in complementary pwm mode: figure 11.95 shows an explan atory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in complementary pwm mode after re- setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (0 init 0 out) 13 tior ( disabled ) 14 toer (0) 15 tocr 16 tmdr (cpwm) 17 toer (1) 18 pfc (mtu) 19 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 not initialized (tioc3b) not initialized (tioc3d) hi-z hi-z hi-z figure 11.95 error occurrence in pwm mode 1, recovery in complementary pwm mode 1 to 10 are the same as in figure 11.91. 11. set normal mode for initialization of the normal mode waveform generation section. 12. initialize the pwm mode 1 waveform generation section with tior. 13. disable operation of the pwm mode 1 waveform generation section with tior. 14. disable channel 3 and 4 output with toer. 15. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 16. set complementary pwm. 17. enable channel 3 and 4 output with toer. 18. set mtu output with the pfc. 19. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 350 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 1 operation, and operation is restarted in reset-synchronous pwm mode: figure 11.96 shows an explan atory diagram of the case where an error occurs in pwm mode 1 and operation is restarted in reset-synchronous pwm mode after re-setting. 1 reset 2 tmdr (pwm1) 3 toer (1) 5 pfc (mtu) 4 tior (1 init 0 out) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (0 init 0 out) 13 tior ( disabled ) 14 toer (0) 15 tocr 16 tmdr (rpwm) 17 toer (1) 18 pfc (mtu) 19 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 not initialized (tioc3b) not initialized (tioc3d) hi-z hi-z hi-z figure 11.96 error occurrence in pwm mode 1, recovery in reset-synchronous pwm mode 1 to 14 are the same as in figure 11.95. 15. select the reset-synchronous pwm output level and cyclic output enabling/disabling with tocr. 16. set reset-synchronous pwm. 17. enable channel 3 and 4 output with toer. 18. set mtu output with the pfc. 19. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 351 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 2 operation, and operation is restarted in normal mode: figure 11.97 shows an explanatory diag ram of the case where an error occurs in pwm mode 2 and operation is restar ted in normal mode after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (cycle re g ister) n=0 to 15 hi-z hi-z figure 11.97 error occurrence in pwm mode 2, recovery in normal mode 1. after a reset, mtu output is low and ports are in the hi gh-impedance state. 2. set pwm mode 2. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence. in pwm mode 2, the cycle register pins are not initialized. in the example, tioc *a is the cycle register.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 352 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 2 operation, and operation is restarted in pwm mode 1: figure 11.98 shows an explanatory diag ram of the case where an error occurs in pwm mode 2 and operation is restar ted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (tioc * b) not initialized (cycle re g ister) n=0 to 15 hi-z hi-z figure 11.98 error occurrence in pwm mode 2, recovery in pwm mode 1 1 to 9 are the same as in figure 11.97. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc*b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 353 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 2 operation, and operation is restarted in pwm mode 2: figure 11.99 shows an explanatory diag ram of the case where an error occurs in pwm mode 2 and operation is restar ted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (cycle re g ister) not initialized (cycle re g ister) n=0 to 15 hi-z hi-z figure 11.99 error occurrence in pwm mode 2, recovery in pwm mode 2 1 to 9 are the same as in figure 11.97. 10. not necessary when restarting in pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 354 of 882 rej09b0108-0400 operation when error occurs during pwm mo de 2 operation, and operation is restarted in phase counting mode: figure 11.100 shows an explanat ory diagram of the case where an error occurs in pwm mode 2 and operation is restarted in phase counting mode after re-setting. 1 reset 2 tmdr (pwm2) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (cycle re g ister) n=0 to 15 hi-z hi-z figure 11.100 error occurrence in pwm mode 2, recovery in phase counting mode 1 to 9 are the same as in figure 11.97. 10. set phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 355 of 882 rej09b0108-0400 operation when error occurs during phase counting mode operation, and operation is restarted in normal mode: figure 11.101 shows an explanat ory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (normal) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen n=0 to 15 hi-z hi-z figure 11.101 error occurrence in phase co unting mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the hi gh-impedance state. 2. set phase counting mode. 3. initialize the pins with tior. (the example shows initial high output, with low output on compare-match occurrence.) 4. set mtu output with the pfc. 5. the count operation is started by tstr. 6. output goes low on compare-match occurrence. 7. an error occurs. 8. set port output with the pfc and output the inverse of the active level. 9. the count operation is stopped by tstr. 10. set in normal mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 356 of 882 rej09b0108-0400 operation when error occurs during phase counting mode operation, and operation is restarted in pwm mode 1: figure 11.102 shows an explanat ory diagram of the case where an error occurs in phase counting mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm1) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen not initialized (tioc * b) n=0 to 15 hi-z hi-z figure 11.102 error occurrence in phase co unting mode, recovery in pwm mode 1 1 to 9 are the same as in figure 11.101. 10. set pwm mode 1. 11. initialize the pins with tior. (in pwm mode 1, the tioc *b side is not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 357 of 882 rej09b0108-0400 operation when error occurs during phase counting mode operation, and operation is restarted in pwm mode 2: figure 11.103 shows an explanat ory diagram of the case where an error occurs in phase counting mode and operation is restarted in pwm mode 2 after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pwm2) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen n=0 to 15 hi-z hi-z not initialized (cycle re g ister) figure 11.103 error occurrence in phase co unting mode, recovery in pwm mode 2 1 to 9 are the same as in figure 11.101. 10. set pwm mode 2. 11. initialize the pins with tior. (in pwm mode 2, the cycle register pins are not initialized.) 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 358 of 882 rej09b0108-0400 operation when error occurs during phase counting mode operation, and operation is restarted in phase counting mode: figure 11.104 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 reset 2 tmdr (pcm) 3 tior (1 init 0 out) 5 tstr (1) 4 pfc (mtu) 6 match 7 error occurs 8 pfc (port) 9 tstr (0) 10 tmdr (pcm) 11 tior (1 init 0 out) 12 pfc (mtu) 13 tstr (1) mtu module output tioc * a tioc * b port output pen pen n=0 to 15 hi-z hi-z figure 11.104 error occurren ce in phase counting mode, recovery in phase counting mode 1 to 9 are the same as in figure 11.101. 10. not necessary when restarting in phase counting mode. 11. initialize the pins with tior. 12. set mtu output with the pfc. 13. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 359 of 882 rej09b0108-0400 operation when error occurs during complementary pwm mode operation, and operation is restarted in normal mode: figure 11.105 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and oper ation is restarted in normal mode after re-setting. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.105 error occurrence in complementary pwm mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the hi gh-impedance state. 2. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 3. set complementary pwm. 4. enable channel 3 and 4 output with toer. 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. the complementary pwm waveform is output on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. the count operation is stopped by tstr. (mtu output becomes the complementary pwm output initial value.) 11. set normal mode. (mtu output goes low.) 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 360 of 882 rej09b0108-0400 operation when error occurs during complementary pwm mode operation, and operation is restarted in pwm mode 1: figure 11.106 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and op eration is restarted in pwm mode 1 after re-setting. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 not initialized (tioc3b) not initialized (tioc3d) hi-z hi-z hi-z figure 11.106 error occurrence in complementary pwm mode, recovery in pwm mode 1 1 to 10 are the same as in figure 11.105. 11. set pwm mode 1. (mtu output goes low.) 12. initialize the pins with tior. (in pwm mode 1, the tioc *b side is not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 361 of 882 rej09b0108-0400 operation when error occurs during complementary pwm mode operation, and operation is restarted in complementary pwm mode: figure 11.107 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in complementary pwm mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 pfc (mtu) 12 tstr (1) 13 match mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.107 error occurrence in complementary pwm mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 11.105. 11. set mtu output with the pfc. 12. operation is restarted by tstr. 13. the complementary pwm waveform is output on compare-match occurrence. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 362 of 882 rej09b0108-0400 operation when error occurs during complementary pwm mode operation, and operation is restarted in complementary pwm mode: figure 11.108 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in complementary pwm mode after re -setting (when operation is restarted using completely new cycle and duty settings). 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 toer (0) 13 tocr 14 tmdr (cpwm) 15 toer (1) 16 pfc (mtu) 17 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.108 error occurrence in complementary pwm mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 11.105. 11. set normal mode and make new settings. (mtu output goes low.) 12. disable channel 3 and 4 output with toer. 13. select the complementary pwm mode output level and cyclic output enabling/disabling with tocr. 14. set complementary pwm. 15. enable channel 3 and 4 output with toer. 16. set mtu output with the pfc. 17. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 363 of 882 rej09b0108-0400 operation when error occurs during complementary pwm mode operation, and operation is restarted in reset-synchronous pwm mode: figure 11.109 shows an explanatory diagram of the case where an error occurs in complementary pwm mode and operation is restarted in reset-synchronous pwm mode. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 toer (0) 13 tocr 14 tmdr (rpwm) 15 toer (1) 16 pfc (mtu) 17 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.109 error occurrence in complementary pwm mode, recovery in reset-synchronous pwm mode 1 to 10 are the same as in figure 11.105. 11. set normal mode. (mtu output goes low.) 12. disable channel 3 and 4 output with toer. 13. select the reset-synchronous pwm mode output level and cyclic output enabling/disabling with tocr. 14. set reset-synchronous pwm. 15. enable channel 3 and 4 output with toer. 16. set mtu output with the pfc. 17. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 364 of 882 rej09b0108-0400 operation when error occurs during rese t-synchronous pwm mode operation, and operation is restarted in normal mode: figure 11.110 shows an explanatory diagram of the case where an error occurs in re set-synchronous pwm mode and operation is restarted in normal mode after re-setting. 1 reset 2 tocr 3 tmdr (cpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (normal) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.110 error occurrence in reset-synchronous pwm mode, recovery in normal mode 1. after a reset, mtu output is low and ports are in the hi gh-impedance state. 2. select the reset-synchronous pwm output level and cyclic output enabling/disabling with tocr. 3. set reset-synchronous pwm. 4. enable channel 3 and 4 output with toer. 5. set mtu output with the pfc. 6. the count operation is started by tstr. 7. the reset-synchronous pwm waveform is output on compare-match occurrence. 8. an error occurs. 9. set port output with the pfc and output the inverse of the active level. 10. the count operation is stopped by tstr. (mtu output becomes the reset-synchronous pwm output initial value.) 11. set normal mode. (mtu positive phase output is low, and negative phase output is high.) 12. initialize the pins with tior. 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 365 of 882 rej09b0108-0400 operation when error occurs during rese t-synchronous pwm mode operation, and operation is restarted in pwm mode 1: figure 11.111 shows an explanatory diagram of the case where an error occurs in reset-synchronous pwm mode and operation is restarted in pwm mode 1 after re-setting. 1 reset 2 tocr 3 tmdr (rpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 tmdr (pwm1) 12 tior (1 init 0 out) 13 pfc (mtu) 14 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 not initialized (tioc3b) not initialized (tioc3d) hi-z hi-z hi-z figure 11.111 error occurrence in reset-synchronous pwm mode, recovery in pwm mode 1 1 to 10 are the same as in figure 11.110. 11. set pwm mode 1. (mtu positive phase output is low, and negative phase output is high.) 12. initialize the pins with tior. (in pwm mode 1, the tioc *b side is not initialized.) 13. set mtu output with the pfc. 14. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 366 of 882 rej09b0108-0400 operation when error occurs during rese t-synchronous pwm mode operation, and operation is restarted in complementary pwm mode: figure 11.112 shows an explanatory diagram of the case where an error occurs in reset-synchronous pwm mode and operation is restarted in complementary pwm mode after re-setting. 1 reset 2 tocr 3 tmdr (rpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 toer (0) 12 tocr 13 tmdr (cpwm) 14 toer (1) 15 pfc (mtu) 16 tstr (1) mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z figure 11.112 error occurrence in reset-synchronous pwm mode, recovery in complementary pwm mode 1 to 10 are the same as in figure 11.110. 11. disable channel 3 and 4 output with toer. 12. select the complementary pwm output level and cyclic output enabling/disabling with tocr. 13. set complementary pwm. (the mtu cyclic output pin goes low.) 14. enable channel 3 and 4 output with toer. 15. set mtu output with the pfc. 16. operation is restarted by tstr. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 367 of 882 rej09b0108-0400 operation when error occurs during rese t-synchronous pwm mode operation, and operation is restarted in reset-synchronous pwm mode: figure 11.113 shows an explanatory diagram of the case where an error occurs in reset-synchronous pwm mode and operation is restarted in reset-sync hronous pwm mode after re-setting. 1 reset 2 tocr 3 tmdr (rpwm) 5 pfc (mtu) 4 toer (1) 6 tstr (1) 7 match 8 error occurs 9 pfc (port) 10 tstr (0) 11 pfc (mtu) 12 tstr (1) 13 match mtu module output tioc3a tioc3b tioc3d port output pe9 pe8 pe11 hi-z hi-z hi-z hi-z hi-z hi-z figure 11.113 error occurrence in reset-synchronous pwm mode, recovery in reset-synchronous pwm mode 1 to 10 are the same as in figure 11.110. 11. set mtu output with the pfc. 12. operation is restarted by tstr. 13. the reset-synchronous pwm waveform is output on compare-match occurrence. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 368 of 882 rej09b0108-0400 11.9 port output enable (poe) the port output enable (poe) can be used to es tablish a high-impedance state for high-current pins, by changing the poe0 to poe3 pin input, depending on the output status of the high-current pins (pe9/tioc3b/sck3/ trst *, pe11/tioc3d/rxd3/tdo*, pe12/tioc4a/txd3/tck*, pe13/tioc4b/ mres , pe14/tioc4c/dack0, pe15/tioc4d/dack1/ irqout ). it can also simultaneously generate interrupt requests. the high-current pins can also be set to high-impedance regardless of whether these pin functions are selected in cases such as when the oscillator stops or in software standby mode. for details, refer to section 17.1.11, high-current port control register (ppcr). however, when using the e10a, the high-impedance function is disabled when an oscillation stop is detected, port output enable (poe), or in th e software standby state for the three pins of pe9/tioc3b/sck3/ trst , pe11/tioc3d/rxd3/tdo, and pe12/tioc4a/txd3/tck of the sh7145. note: * only in the sh7145. 11.9.1 features ? each of the poe0 to poe3 input pins can be set for falling edge, p /8 16, p /16 16, or p /128 16 low-level sampling. ? high-current pins can be set to high-impedance state by poe0 to poe3 pin falling-edge or low-level sampling. ? high-current pins can be set to high-impedance state when the high-current pin output levels are compared and simultaneous low-level output continues for one cycle or more. ? interrupts can be generated by input-level sampling or output-level comparison results. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 369 of 882 rej09b0108-0400 the poe has input-level detection circuitry and outp ut-level detection circuitry, as shown in the block diagram of figure 11.114. tioc3b tioc3d tioc4a tioc4c tioc4b tioc4d poe3 poe2 poe1 poe0 output level detection circuit output level detection circuit output level detection circuit input level detection circuit fallin g -ed g e detection circuit low-level detection circuit ocsr icsr1 /8 /16 /128 hi g h- impedance request control si g nal interrupt request [le g end] ocsr: output level control/status re g ister icsr1: input level control/status re g ister figure 11.114 poe block diagram 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 370 of 882 rej09b0108-0400 11.9.2 pin configuration table 11.44 pin configuration name abbreviation i/o description port output enable input pins poe0 to poe3 input input request signals to make high- current pins high-impedance state table 11.45 shows output-level comparisons with pin combinations. table 11.45 pin combinations pin combination i/o description pe9/tioc3b and pe11/tioc3d output all high -current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. pe12/tioc4a and pe14/tioc4c output all high -current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. pe13/tioc4b/ mres and pe15/tioc4d/ irqout output all high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. 11.9.3 register descriptions the poe has the two registers. the input level control/status register 1 (icsr1) controls both poe0 to poe3 pin input signal detection and interrupts. the output level control/status register (ocsr) controls both the enable/disable of output comparison and interrupts. input level control/status register 1 (icsr1): the input level control/status register (icsr1) is a 16-bit readable/writabl e register that selects the poe0 to poe3 pin input modes, controls the enable/disable of interrupts, and indicates status. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 371 of 882 rej09b0108-0400 bit bit name initial value r/w description 15 poe3f 0 r/(w) * poe3 flag this flag indicates that a high impedance request has been input to the poe3 pin [clearing condition] ? by writing 0 to poe3f after reading a poe3f = 1 [setting condition] ? when the input set by icsr1 bits 7 and 6 occurs at the poe3 pin 14 poe2f 0 r/(w) * poe2 flag this flag indicates that a high impedance request has been input to the poe2 pin [clearing condition] ? by writing 0 to poe2f after reading a poe2f = 1 [setting condition] ? when the input set by icsr1 bits 5 and 4 occurs at the poe2 pin 13 poe1f 0 r/(w) * poe1 flag this flag indicates that a high impedance request has been input to the poe1 pin [clearing condition] ? by writing 0 to poe1f after reading a poe1f = 1 [setting condition] ? when the input set by icsr1 bits 3 and 2 occurs at the poe1 pin 12 poe0f 0 r/(w) * poe0 flag this flag indicates that a high impedance request has been input to the poe0 pin [clear condition] ? by writing 0 to poe0f after reading a poe0f = 1 [set condition] ? when the input set by icsr1 bits 1 and 0 occurs at the poe0 pin 11 to 9 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 372 of 882 rej09b0108-0400 bit bit name initial value r/w description 8 pie 0 r/w port interrupt enable this bit enables/disables interrupt requests when any of the poe0f to poe3f bits of the icsr1 are set to 1 0: interrupt requests disabled 1: interrupt requests enabled 7 6 poe3m1 poe3m0 0 0 r/w r/w poe3 mode 1, 0 these bits select the input mode of the poe3 pin 00: accept request on falling edge of poe3 input 01: accept request when poe3 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe3 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe3 input has been sampled for 16 p /128 clock pulses, and all are low level. 5 4 poe2m1 poe2m0 0 0 r/w r/w poe2 mode 1, 0 these bits select the input mode of the poe2 pin 00: accept request on falling edge of poe2 input 01: accept request when poe2 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe2 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe2 input has been sampled for 16 p /128 clock pulses, and all are low level. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 373 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 2 poe1m1 poe1m0 0 0 r/w r/w poe1 mode 1, 0 these bits select the input mode of the poe1 pin 00: accept request on falling edge of poe1 input 01: accept request when poe1 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe1 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe1 input has been sampled for 16 p /128 clock pulses, and all are low level. 1 0 poe0m1 poe0m0 0 0 r/w r/w poe0 mode 1, 0 these bits select the input mode of the poe0 pin 00: accept request on falling edge of poe0 input 01: accept request when poe0 input has been sampled for 16 p /8 clock pulses, and all are low level. 10: accept request when poe0 input has been sampled for 16 p /16 clock pulses, and all are low level. 11: accept request when poe0 input has been sampled for 16 p /128 clock pulses, and all are low level. note: * only 0 can be written to clear the flag. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 374 of 882 rej09b0108-0400 output level control/status register (ocsr): the output level control/status register (ocsr) is a 16-bit readable/writable register that c ontrols the enable/disable of both output level comparison and interrupts, and indicates status. if the osf bit is set to 1, the high current pins become high impedance. bit bit name initial value r/w description 15 osf 0 r/(w) * output short flag this flag indicates that any one pair of the three pairs of 2 phase outputs compared have simultaneously become low level outputs. [clearing condition] ? by writing 0 to osf after reading an osf = 1 [setting condition] ? when any one pair of the three 2-phase outputs simultaneously become low level 14 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 oce 0 r/w output level compare enable this bit enables the start of output level comparisons. when setting this bit to 1, pay attention to the output pin combinations shown in table 11.43, mode transit ion combinations. when 0 is output, the osf bit is set to 1 at the same time when this bit is set, and output goes to high impedance. accordingly, bits 15 to 11 and bit 9 of the port e data register (pedr) are set to 1. for the mtu output comparison, set the bit to 1 after setting the mtu's output pins with th e pfc. set this bit only when using pins as outputs. when the oce bit is set to 1, if oie = 0 a high- impedance request will not be issued even if osf is set to 1. therefore, in order to have a high- impedance request issued according to the result of the output level comparison, the oie bit must be set to 1. when oce = 1 and oie = 1, an interrupt request will be generated at the same time as the high-impedance request: however, this interrupt can be masked by means of an interrupt controller (intc) setting. 0: output level compare disabled 1: output level compare enabled; makes an output high impedance request when osf = 1. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 375 of 882 rej09b0108-0400 bit bit name initial value r/w description 8 oie 0 r/w output short interrupt enable this bit makes interrupt requests when the osf bit of the ocsr is set. 00: interrupt requests disabled 01: interrupt request enabled 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. note: * only 0 can be written to write the flag. 11.9.4 operation input level detection operation: if the input conditions set by the icsr1 occur on any of the poe pins, all high-current pins become high-impedance state. note however, that these high-current pins become high-impedance state only when general input/output function or mtu function is selected in these pins. 1. falling edge detection when a change from high to low level is input to the poe pins. 2. low-level detection figure 11.115 shows the low-level detection operation. sixteen continuous low levels are sampled with the sampling clock established by the icsr1. if even one high level is detected during this interval, the low level is not accepted. sampling starts when detecting the falling edge of the poe pin. thereby, negate the poe pin when using poe function after sampling. furthermore, the timing when the large-curren t pins enter the high-i mpedance state from the sampling clock is the same in both falling-edge detection and in low-level detection. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 376 of 882 rej09b0108-0400 p samplin g clock 3 poe input pe9/ tioc3b when low level is sampled at all points when hi g h level is sampled at least once fla g set ( poe received) fla g not set hi g h-impedance state * note: * other lar g e-current pins (pe11/tioc3d, pe12/tioc4a, pe13/tioc4b/ mres , pe14/tioc4c, pe15/tioc4d/ irqout ) also g o to the hi g h-impedance state at the same timin g . 2 1 2 1 16 13 8/16/128 clock cycles figure 11.115 low-leve l detection operation output-level compare operation: figure 11.116 shows an example of the output-level compare operation for the combination of pe9/tioc3b and pe11/tioc3d. the operation is the same for the other pin combinations. p pe11/ tioc3d pe9/ tioc3b low level overlappin g detected hi g h impedance state figure 11.116 output-lev el detection operation 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 377 of 882 rej09b0108-0400 release from high-impedance state: high-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on rese t, or by clearing all of the bit 12 to 15 (poe0f to poe3f) flags of the icsr1. high-current pins that have become high- impedance due to output-level detection can be rel eased either by returning them to their initial state with a power-on reset, or by first clearing bit 9 (oce) of the ocsr to disable output-level compares, then clearing the bit 15 (osf) flag. however, when returning from high-impedance state by clearing the osf flag, always do so only after outputting a high level from the high- current pins (tioc3b, tioc3d, tioc4a, tioc4b, tioc4c, and tioc4d). high-level outputs can be achieved by setting the mtu internal registers. poe timing: figure 11.117 shows an example of timing from poe input to high impedance of pin. poe input ck fallin g ck pe9/ tioc3b fallin g ed g e detected hi g h impedance state * note: * other lar g e-current pins (pe11/tioc3d, pe12/tioc4a, pe13/tioc4b/ mres , pe14/tioc4c, pe15/tioc4d/ irqout ) also g oes to the hi g h impedance state at the same timin g figure 11.117 falling edge detection operation 11.9.5 usage notes 1. make sure to set the input to the poe pin high, before detecting the level of the poe pin. 2. to clear the poe3f to poe0f bits in the input level control/status register 1 (icsr1) and the osf bit in the output level control/status register (ocsr) to 0, read icsr1, icsr2, and ocsr first. if there are bits which are read as 1, clear those bits to 0. then write 1 to the other bits. 11. multi-function timer pulse unit (mtu) rev.4.00 mar. 27, 2008 page 378 of 882 rej09b0108-0400 12. watchdog timer wdt0400a_030020030800 rev.4.00 mar. 27, 2008 page 379 of 882 rej09b0108-0400 section 12 watchdog timer the watchdog timer (wdt) is an 8-bit timer that can reset this lsi internally if the counter overflows without rewriting the counter value due to a system crash or the like. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer operation, an interval timer interrupt is generated each time the counter overflows. the block diagram of the wdt is shown in figure 12.1. 12.1 features ? switchable between watchdog timer mode and interval timer mode in watchdog timer mode ? output wdtovf signal if the counter overflows, it is possible to select whether this lsi is internally reset or not. a power-on reset or manual reset can be selected as an in internal reset. in interval timer mode ? if the counter overflows, the wdt generates an interval timer interrupt (iti). ? clears software standby mode ? selectable from eight counter input clocks. 12. watchdog timer rev.4.00 mar. 27, 2008 page 380 of 882 rej09b0108-0400 overflow interrupt control iti (interrupt request si g nal) internal reset si g nal * 2 reset control rstcsr tcnt tscr /2 /64 /128 /256 /512 /1024 /4096 /8192 clock clock select internal clock sources bus interface module bus internal bus wdt [le g end] tcsr: timer control/status re g ister tcnt: timer counter rstcsr: reset control/status re g ister notes: 1. if this pin needs to be pulled-down,the resistance value must be 1m or hi g her. 2. the internal reset si g nal can be g enerated by re g ister settin g . power-on reset or manual reset can be selected. wdtovf * 1 figure 12.1 block diagram of wdt 12.2 input/output pin table 12.1 shows the pin configuration. table 12.1 pin configuration pin abbreviation i/o function watchdog timer overflow wdtovf output outputs the count er overflow signal in watchdog timer mode 12. watchdog timer rev.4.00 mar. 27, 2008 page 381 of 882 rej09b0108-0400 12.3 register descriptions the wdt has the following three registers. for details, see section 25, list of registers. to prevent accidental overwriting, tcsr, tcnt, and rs tcsr have to be written to in a method different from normal registers. for details, see section 12.6 .1, notes on register access. ? timer control/status register (tcsr) ? timer counter (tcnt) ? reset control/status register (rstcsr) 12.3.1 timer counter (tcnt) tcnt is an 8-bit readable/writable upcounter. when the timer enable bit (tme) in the timer control/status register (tcsr) is set to 1, tcnt starts counting pulses of an internal clock selected by clock select bits 2 to 0 (cks2 to cks0) in tcsr. when the value of tcnt overflows (changes from h'ff to h'00), a watchdog timer overflow signal ( wdtovf ) or interval timer interrupt (iti) is generated, depending on the mode selected in the wt/ it bit of tcsr. the initial value of tcnt is h'00. 12. watchdog timer rev.4.00 mar. 27, 2008 page 382 of 882 rej09b0108-0400 12.3.2 timer control/s tatus register (tcsr) tcsr is an 8-bit readable/writable register. its functions include selecting the clock source to be input to tcnt, and the timer mode. bit bit name initial value r/w description 7 ovf 0 r/(w) * 1 overflow flag indicates that tcnt has overflowed in interval timer mode. only a write of 0 is permitted, to clear the flag. this flag is not set in watchdog timer mode. [setting condition] ? when tcnt overflows in interval timer mode. [clearing condition] ? when writing 0 to this bit after reading this bit or when writing 0 to the tme bit in interval timer mode. 6 wt/ it 0 r/w timer mode select selects whether the wdt is used as a watchdog timer or interval timer. when tcnt overflows, the wdt either generates an interval timer interrupt (iti) or generates a wdtovf signal, depending on the mode selected. 0: interval timer mode interval timer interrupt (iti) request to the cpu when tcnt overflows 1: watchdog timer mode wdtovf signal output externally when tcnt overflows. for details on the tcnt overflow in watchdog timer mode, see section 12.3.3, reset control/status register (rstcsr). 5 tme 0 r/w timer enable enables or disables the timer. 0: timer disabled tcnt is initialized to h'00 and count-up stops 1: timer enabled tcnt starts counting. a wdtovf signal or interrupt is generated when tcnt overflows. 12. watchdog timer rev.4.00 mar. 27, 2008 page 383 of 882 rej09b0108-0400 bit bit name initial value r/w description 4, 3 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 2 1 0 cks2 cks1 cks0 0 0 0 r/w r/w r/w clock select 2 to 0 select one of eight internal clock sources for input to tcnt. the clock signals are obtained by dividing the frequency of the system clock ( ). the overflow frequency for = 40 mhz is enclosed in parentheses * 2 . 000: clock /2 (overflow interval: 12.8 s) 001: clock /64 (overflow interval: 409.6 s) 010: clock /128 (overflow interval: 0.8 ms) 011: clock /256 (overflow interval: 1.6 ms) 100: clock /512 (overflow interval: 3.3 ms) 101: clock /1024 (overflow interval: 6.6 ms) 110: clock /4096 (overflow interval: 26.2 ms) 111: clock /8192 (overflow interval: 52.4 ms) notes: 1. only a 0 can be written after reading 1. 2. the overflow interval listed is the time from when the tcnt begins counting at h'00 until an overflow occurs. 12. watchdog timer rev.4.00 mar. 27, 2008 page 384 of 882 rej09b0108-0400 12.3.3 reset control/st atus register (rstcsr) rstcsr is an 8-bit readable/writable register th at controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. bit bit name initial value r/w description 7 wovf 0 r/(w) * watchdog timer overflow flag this bit is set when tcnt overflows in watchdog timer mode. this bit cannot be set in interval timer mode. [setting condition] ? set when tcnt overflows in watchdog timer mode [clearing condition] ? cleared by reading wovf, and then writing 0 to wovf 6 rste 0 r/w reset enable specifies whether or not an internal reset signal is generated in the chip if tcnt overflows in watchdog timer mode. 0: internal reset signal is not generated even if tcnt overflows (though this lsi is not reset, tcnt and tcsr in wdt are reset) 1: internal reset signal is generated if tcnt overflows 5 rsts 0 r/w reset select selects the type of internal reset generated if tcnt overflows in watchdog timer mode. 0: power-on reset 1: manual reset 4 to 0 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. note: * only 0 can be written for flag clearing. 12. watchdog timer rev.4.00 mar. 27, 2008 page 385 of 882 rej09b0108-0400 12.4 operation 12.4.1 watchdog timer mode to use the wdt as a watchdog timer, set the wt/ it and tme bits of tcsr to 1. software must prevent tcnt overflow by rewriting the tcnt value (normally by writing h'00) before overflow occurs. no tcnt overflows will occur while the system is operating normally, but if tcnt fails to be rewritten and overflows occur due to a system crash or the like, a wdtovf signal is output externally. the wdtovf signal can be used to reset the system. the wdtovf signal is output for 128 clock cycles. if the rste bit in rstcsr is set to 1, a signal to reset the chip will be generated internally simultaneous to the wdtovf signal when tcnt overflows. e ither a power-on reset or a manual reset can be selected by the rsts bit in rstcsr . the internal reset signal is output for 512 clock cycles. when a wdt overflow reset is generated simultaneously with a reset input at the res pin, the res reset takes priority, and the wovf bit in rstcsr is cleared to 0. the following are not initialized by a wdt reset signal: ? port output enable (poe) registers of mtu ? pin function controller (pfc) registers ? i/o port registers ? reset control/status register (rstcsr) of watchdog timer (wdt) these registers are initialized only by an external power-on reset. besides, tcnt and tcsr of the wdt are not initialized by a manual reset from the mres pin, but are initialized by an internal manual reset generated by a wdt overflow. 12. watchdog timer rev.4.00 mar. 27, 2008 page 386 of 882 rej09b0108-0400 tcnt value h'ff h'00 wdtovf si g nal internal reset si g nal * overflow h?00 written in tcnt wt/ it = 1 tme = 1 h?00 written in tcnt wt/ it = 1 tme = 1 wovf = 1 wdtovf and internal reset g enerated 128 clocks 512 clocks wt/ it : timer mode select bit tme: timer enable bit note: * internal reset si g nal occurs only when the rste bit is set to 1. time figure 12.2 operation in watchdog timer mode 12.4.2 interval timer mode to use the wdt as an interval timer, clear wt/ it to 0 and set tme to 1 in tcsr. an interval timer interrupt (iti) is generated each time the tim er counter (tcnt) overflows. this function can be used to generate interval timer interrupts at regular intervals. tcnt value h'ff h'00 overflow wt/ it = 0 tme = 1 overflow overflow overflow iti iti iti iti time iti: interval timer interrupt request g eneration figure 12.3 operation in interval timer mode 12. watchdog timer rev.4.00 mar. 27, 2008 page 387 of 882 rej09b0108-0400 12.4.3 clearing soft ware standby mode the watchdog timer has a special function to clear software standby mode with an nmi interrupt or irq0 to irq7 interrupts. when using software standby mode, set the wdt as described below. before transition to software standby mode: the tme bit in tcsr must be cleared to 0 to stop the watchdog timer counter before entering software standby mode. the chip cannot enter software standby mode while the tme bit is set to 1. set bits cks2 to cks0 in tcsr so that the counter overflow interval is equal to or longer than the oscillation settling time. see section 26.3, ac characteristics, for the oscillation settling time. recovery from software standby mode: when an nmi signal or irq0 to irq7 signals are received in software standby mode, the clock oscillator star ts running and tcnt starts incrementing at the rate select ed by bits cks2 to cks0 befo re software standby mode was entered. when tcnt overflows (cha nges from h'ff to h'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and software standby mode ends. for details on software standby mode, see section 24, power-down modes. 12.4.4 timing of setting overflow flag (ovf) in interval timer mode, when tcnt overflows, th e ovf bit of tcsr is set to 1 and an interval timer interrupt (iti) is simultaneously requ ested. figure 12.4 shows this timing. tcnt overflow si g nal (internal si g nal) ovf h?ff h?00 figure 12.4 timing of setting ovf 12. watchdog timer rev.4.00 mar. 27, 2008 page 388 of 882 rej09b0108-0400 12.4.5 timing of setting watchd og timer overflow flag (wovf) when tcnt overflows in watchdog timer mode, the wovf bit of rstcsr is set to 1 and a wdtovf signal is output. when the rste bit in rstcsr is set to 1, tcnt overflow enables an internal reset signal to be generated for the entire chip. figure 12.5 shows this timing. tcnt overflow si g nal (internal si g nal) wovf h'ff h'00 figure 12.5 timing of setting wovf 12.5 interrupt source during interval timer mode operation, an overflow generates an interval timer interrupt (iti). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. table 12.2 wdt interrupt source (in interval timer mode) name interrupt source interrupt flag dmac/dtc activation iti tcnt overflow ovf impossible 12. watchdog timer rev.4.00 mar. 27, 2008 page 389 of 882 rej09b0108-0400 12.6 usage notes 12.6.1 notes on register access the watchdog timer?s tcnt, tcsr, and rstcsr re gisters differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: these registers must be written by a word transfer instruction. they cannot be written by byte transfer instructions. tcnt and tcsr both have the same write address. the write data must be contained in the lower byte of the written word. the upper byte must be h'5a (for tcnt) or h'a5 (for tcsr) (figure 12.6). this transfers the write data from the lower byte to tcnt or tcsr. 15 8 7 0 15 8 7 0 h'5a h'a5 write data write data ? writin g to tcnt ? writin g to tcsr address: h'ffff8610 address: h'ffff8610 figure 12.6 writing to tcnt and tcsr writing to rstcsr: rstcsr must be written by a wo rd access to address h'ffff8612. it cannot be written by byte transfer instructions. procedures for writing 0 to wovf (bit 7) and for writing to rste (bit 6) and rsts (bit 5) are different, as shown in figure 12.7. to write 0 to the wovf bit, the write data must be h'a5 in the upper byte and h'00 in the lower byte. this clears the wovf bit to 0. the rste and rsts bits are not affected. to write to the rste and rsts bits, the upper byte must be h'5a and the lower byte must be the write data. the values of bits 6 and 5 of the lower byte are transferred to the rste and rsts bits, respectively. the wovf bit is not affected. 12. watchdog timer rev.4.00 mar. 27, 2008 page 390 of 882 rej09b0108-0400 15 8 7 0 15 8 7 0 h'a5 h'5a write data ? writin g 0 to the wovf bit ? writin g to the rste and rsts bits address: h'ffff8612 address: h'ffff8612 h?00 figure 12.7 writing to rstcsr reading from tcnt, tcsr, and rstcsr: tcnt, tcsr, and rstcsr are read like other registers. use byte transfer instructions. the read addresses are h'ffff8610 for tcsr, h'ffff8611 for tcnt, and h'ffff8613 for rstcsr. 12.6.2 tcnt write an d increment contention if a timer counter increment clock pulse is generate d during the t3 state of a write cycle to tcnt, the write takes priority and the timer counter is no t incremented. figure 12.8 shows this operation. address internal write si g nal tcnt input clock tcnt n m t 1 t 2 tcnt write cycle counter write data t 3 tcnt address figure 12.8 contention betw een tcnt write and increment 12. watchdog timer rev.4.00 mar. 27, 2008 page 391 of 882 rej09b0108-0400 12.6.3 changing cks2 to cks0 bit values if the values of bits cks2 to cks0 in the timer control/status register (tcsr) are rewritten while the wdt is running, the count may not increment correctly. always stop the watchdog timer (by clearing the tme bit to 0) before changi ng the values of bits cks2 to cks0. 12.6.4 changing between watchdog timer and interval timer modes to prevent incorrect operation, always stop th e watchdog timer (by clear ing the tme bit to 0) before switching between interval timer mode and watchdog timer mode. 12.6.5 system reset by wdtovf signal if a wdtovf output signal is input to the res pin, the chip cannot initialize correctly. avoid inputting the wdtovf signal to the res pin directly. to reset th e entire system with the wdtovf signal, use the circuit shown in figure 12.9. reset input reset si g nal to entire system this lsi res wdtovf figure 12.9 example of system reset circuit using wdtovf signal 12.6.6 internal reset in watchdog timer mode if the rste bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a tcnt overflow occurs, but tcnt and tcsr in the wdt will be reset. 12. watchdog timer rev.4.00 mar. 27, 2008 page 392 of 882 rej09b0108-0400 12.6.7 manual reset in watchdog timer mode when an internal reset is effected by tcnt ove rflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. therefore, the bus cycle is retained in a manual reset, but if a manual reset occurs while the bus is released, manual reset exception processing will be deferred until the cpu acquires the bus. however, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the internal manu al reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. 12.6.8 note on using wdtovf signal do not pull down the wdtovf pin. if necessary, pull it down with resistance larger than 1 m . 13. serial communication interface (sci) scis200b_030020030800 rev.4.00 mar. 27, 2008 page 393 of 882 rej09b0108-0400 section 13 serial co mmunication interface (sci) this lsi has four independent serial communication interface (sc i) channels. the sci can handle both asynchronous and clocked synchronous serial communication. serial data communication can be carried out with standard asynchrono us communication chips such as a universal asynchronous receiver/transmitte r (uart) or asynchronous communication interface adapter (acia). a function is also provided for serial communication between processors (multiprocessor communication function). the sci al so supports a smart card (ic card) interface conforming to iso/iec 7816-3 (identification card) as an extension function for asynchronous mode. 13.1 features ? choice of asynchronous or clocked synchronous serial communication mode ? full-duplex communication capability the transmitter and receiver are mutually independ ent, enabling transmission and reception to be executed simultaneously. double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. ? on-chip baud rate generator allows any bit rate to be selected external clock can be selected as a transfer clock source (except for a smart card interface). ? choice of lsb-first or msb-first transfer* (ex cept in the case of as ynchronous mode 7-bit data) ? four interrupt sources four interrupt sources ? tran smit-end, transmit-data-empty, receive-data-full, and receive error ? that can issue requests. the transmit-data-empty interrupt and receive data full in terrupts can activate the direct memory access controller (dmac) and th e data transfer controller (dtc). ? module standby mode can be set asynchronous mode ? data length: 7 or 8 bits ? stop bit length: 1 or 2 bits ? parity: even, odd, or none ? communication between multiprocessors ? receive error detection: parity , overrun, and framing errors ? break detection: break can be detected by r eading the rxd pin level directly in case of a framing error 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 394 of 882 rej09b0108-0400 clocked synchronous mode ? data length: 8 bits ? receive error detection: overrun errors detected smart card interface ? data is automatically retransmitted if an error si gnal is received while da ta is being transmitted ? direct convention and inverse convention both supported note: * the description in this sec tion is based on lsb-first transfer. figure 13.1 shows a block diagram of the sci. rxd txd sck clock p p /8 p /32 p /128 tei txi rxi eri ssr scr smr sdcr transmission/ reception control baud rate g enerator brr module data bus rdr tsr rsr parity g eneration [le g end] rsr: receive shift re g ister rdr: receive data re g ister tsr: transmit shift re g ister tdr: transmit data re g ister smr: serial mode re g ister scr: serial control re g ister ssr: serial status re g ister brr: bit rate re g ister sdcr: serial direction control re g ister tdr bus interface internal data bus parity check external clock figure 13.1 block diagram of sci 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 395 of 882 rej09b0108-0400 13.2 input/output pins table 13.1 shows the pins for each sci channel. table 13.1 pin configuration channel pin name * i/o function sck0 i/o sci0 clock input/output rxd0 input sci0 receive data input 0 txd0 output sci0 transmit data output sck1 i/o sci1 clock input/output rxd1 input sci1 receive data input 1 txd1 output sci1 transmit data output sck2 i/o sci2 clock input/output rxd2 input sci2 receive data input 2 txd2 output sci2 transmit data output 3 sck3 i/o sci3 clock input/output rxd3 input sci3 receive data input txd3 output sci3 transmit data output note: * pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 396 of 882 rej09b0108-0400 13.3 register descriptions the sci has the following registers for each channel. for details on register addresses and register states during each processing, refer to section 25, list of registers. the serial mode register (smr), serial control register (scr), and serial status register (ssr) are described separately for normal serial communication in terface mode and smart card interface mode because their bit functions differ in part. channel 0 ? serial mode register_0 (smr_0) ? bit rate register_0 (brr_0) ? serial control register_0 (scr_0) ? transmit data register_0 (tdr_0) ? transmit shift register_0 (tsr_0) ? serial status re gister_0 (ssr_0) ? receive data register_0 (rdr_0) ? receive shift register_0 (rsr_0) ? serial direction contro l register_0 (sdcr_0) channel 1 ? serial mode register_1 (smr_1) ? bit rate register_1 (brr_1) ? serial control register_1 (scr_1) ? transmit data register_1 (tdr_1) ? transmit shift register_1 (tsr_1) ? serial status re gister_1 (ssr_1) ? receive data register_1 (rdr_1) ? receive shift register_1 (rsr_1) ? serial direction contro l register_1 (sdcr_1) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 397 of 882 rej09b0108-0400 channel 2 ? serial mode register_2 (smr_2) ? bit rate register_2 (brr_2) ? serial control register_2 (scr_2) ? transmit data register_2 (tdr_2) ? transmit shift register_2 (tsr_2) ? serial status re gister_2 (ssr_2) ? receive data register_2 (rdr_2) ? receive shift register_2 (rsr_2) ? serial direction contro l register_2 (sdcr_2) channel 3 ? serial mode register_3 (smr_3) ? bit rate register_3 (brr_3) ? serial control register_3 (scr_3) ? transmit data register_3 (tdr_3) ? transmit shift register_3 (tsr_3) ? serial status re gister_3 (ssr_3) ? receive data register_3 (rdr_3) ? receive shift register_3 (rsr_3) ? serial direction contro l register_3 (sdcr_3) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 398 of 882 rej09b0108-0400 13.3.1 receive shi ft register (rsr) rsr is a shift register used to receive serial data that is input to the rxd pin and convert it into parallel data. when one byte of data has been r eceived, it is transferre d to rdr automatically. rsr cannot be directly read or written to by the cpu. 13.3.2 receive data register (rdr) rdr is an 8-bit register that stores receive da ta. when the sci has received one byte of serial data, it transfers the received serial data from rs r to rdr where it is stored. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this wa y, enables continuous receive operations to be performed. after confirmi ng that the rdrf bit in ssr is set to 1, read rdr for only once. rdr cannot be written to by the cpu. the initial value of rdr is h'00. 13.3.3 transmit shift register (tsr) tsr is a shift register that transmits serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin. tsr cannot be directly accessed by the cpu. 13.3.4 transmit data register (tdr) tdr is an 8-bit register that stores transmit data. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to ts r and starts transmission. the double-buffered structures of tdr and tsr enables continuous se rial transmission. if the next transmit data has already been written to tdr during serial transmi ssion, the sci transfers the written data to tsr to continue transmission. although tdr can be read or written to by the cpu at all times, to achieve reliable serial transmission, write transmit data to tdr for only once after confirming that the tdre bit in ssr is set to 1. the initial value of tdr is h'ff. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 399 of 882 rej09b0108-0400 13.3.5 serial mode register (smr) smr is used to set the sci?s serial transfer format and select the baud rate generator clock source. some bit functions of smr differ between normal serial communication interface mode and smart card interface mode. ? normal serial communication interf ace mode (when smif in sdcr is 0) bit bit name initial value r/w description 7 c/ a 0 r/w communication mode 0: asynchronous mode 1: clocked synchronous mode 6 chr 0 r/w character length (enabled only in asynchronous mode) 0: selects 8 bits as the data length. 1: selects 7 bits as the data length. lsb-first is fixed and the msb (bit 7) of t dr is not transmitted in transmission. in clocked synchronous mode, a fixed data length of 8 bits is used. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. fo r a multiprocessor format, parity bit addition and checking are not performed regardless of the pe bit setting. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 400 of 882 rej09b0108-0400 bit bit name initial value r/w description 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus parity bit is even. 1: selects odd parity. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 3 stop 0 r/w stop bit length (enabled only in asynchronous mode) selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits in reception, only the first stop bit is checked. if the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 mp 0 r/w multiprocessor mode (enabled only in asynchronous mode) when this bit is set to 1, the multiprocessor communication function is enabled. the pe bit and o/ e bit settings are invalid in multiprocessor mode. 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the clock source for the baud rate generator. 00: p clock (n = 0) 01: p /8 clock (n = 1) 10: p /32 clock (n = 2) 11: p /128 clock (n = 3) for the relation between the setting of cks1 and cks2 and the baud rate, see section 13.3.9, bit rate register (brr). n is the decimal display of the value of n in brr (see section 13.3.9, bit rate register (brr)). 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 401 of 882 rej09b0108-0400 ? smart card interface mode (w hen smif in sdcr is 1) bit bit name initial value r/w description 7 gm 0 r/w gsm mode when this bit is set to 1, the sci operates in gsm mode. in gsm mode, the timing of the tend setting is advanced by 11.0 etu, and cl ock output control function is added. for details, refe r to section 13.7.7, clock output control. 6 blk 0 r/w when this bit is set to 1, the sci operates in block transfer mode. for details on block transfer mode, refer to section 13.7.3, block transfer mode. during reception in smart ca rd interface mode, this bit must be set to 1. 5 pe 0 r/w parity enable (enabled only in asynchronous mode) when this bit is set to 1, the parity bit is added to transmit data in transmission, and the parity bit is checked in reception. in smart card interface mode, this bit must be set to 1. 4 o/ e 0 r/w parity mode (enabled only when the pe bit is 1 in asynchronous mode) 0: selects even parity. 1: selects odd parity. for details on setting this bi t in smart card interface mode, refer to section 13.7 .2, data format (except for block transfer mode). 3 2 bcp1 bcp0 0 0 r/w r/w basic clock pulse 1 and 0 these bits select the number of basic clock cycles in a 1-bit transfer interval in smart card interface mode. 00: 32 clocks (s = 32) 01: 64 clocks (s = 64) 10: 372 clocks (s = 372) 11: 256 clocks (s = 256) for details, refer to sect ion 13.7.4, receive data sampling timing and reception margin. s stands for the value of s in brr (see section 13.3.9, bit rate register (brr)). 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 402 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 0 cks1 cks0 0 0 r/w r/w clock select 1 and 0 these bits select the clock source for the on-chip baud rate generator. 00: p clock (n = 0) 01: p /8 clock (n = 1) 10: p /32 clock (n = 2) 11: p /128 clock (n = 3) for details on the relationship between the setting of these bits and the baud rate, refer to section 13.3.9, bit rate register (brr). n is t he decimal representation of the value of n in brr (see section 13.3.9, bit rate register (brr)). note: etu (elementary time unit): abbreviation for the transfer period for one bit. 13.3.6 serial control register (scr) scr is a register that performs enabling or disabling of sci transfer operations and interrupt requests, and selection of the tr ansfer clock source. for details on interrupt requests, refer to section 13.8, interrupt sources. some bit functions of scr differ between normal serial communication interface mode an d smart card interface mode. ? normal serial communi cation interface mode (when smif in sdcr is 0) bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, a txi interrupt request is enabled. txi interrupt request cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0, or clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag in ssr, then clearing the flag to 0, or clearing the rie bit to 0. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 403 of 882 rej09b0108-0400 bit bit name initial value r/w description 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be made to decide the transfer format before setting the te bit to 1. when this bit is cleared to 0, transmit operation is disabled, and the tdre flag in ssr is fixed to 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. serial reception is started in this state when a start bit is detected in asynchronous mode or synchronous clock input is detected in clocked synchronous mode. smr setting must be made to decide the receive format before setting the re bit to 1. clearing the re bit to 0 disables reception and does not affect the rdrf, fer, per, and orer flags, which retain their states. 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) when this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the rdrf, fer, and orer status flags in ssr is prohibited. on receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. for details, refer to section 13.5, mu ltiprocessor communication function. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr, are not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting are enabled. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 404 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 teie 0 r/w transmit end interrupt enable when this bit is set to 1, a tei interrupt request is enabled. tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. 1 0 cke1 cke0 0 0 r/w r/w clock enable 1 and 0 select the clock source and sck pin function. asynchronous mode: 00: internal clock, sck pin used for input pin (input signal is ignored) or output pin (output level is undefined) 01: internal clock, sck pin used for clock output (the output clock frequency is the same as the bit rate) 10: external clock, sck pin used for clock input (the input clock frequency is 16 times the bit rate) 11: external clock, sck pin used for clock input (the input clock frequency is 16 times the bit rate) clocked synchronous mode: 00: internal clock, sck pin used for synchronous clock output 01: internal clock, sck pin used for synchronous clock output 10: external clock, sck pin used for synchronous clock input 11: external clock, sck pin used for synchronous clock input 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 405 of 882 rej09b0108-0400 ? smart card interface mode (w hen smif in sdcr is 1) bit bit name initial value r/w description 7 tie 0 r/w transmit interrupt enable when this bit is set to 1, a txi interrupt request is enabled. txi interrupt request cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0, or clearing the tie bit to 0. 6 rie 0 r/w receive interrupt enable when this bit is set to 1, rxi and eri interrupt requests are enabled. rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf, fer, per, or orer flag in ssr, then clearing the flag to 0, or clearing the rie bit to 0. 5 te 0 r/w transmit enable when this bit is set to 1, transmission is enabled. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be made to decide the transfer format before setting the te bit to 1. when this bit is cleared to 0, transmit operation is disabled, and the tdre flag in ssr is fixed to 1. 4 re 0 r/w receive enable when this bit is set to 1, reception is enabled. serial reception is started in this state when a start bit is detected in asynchronous mode or synchronous clock input is detected in clocked synchronous mode. smr setting must be made to decide the receive format before setting the re bit to 1. clearing the re bit to 0 disables reception and does not affect the rdrf, fer, per, and orer flags, which retain their states. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 406 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 mpie 0 r/w multiprocessor interrupt enable (enabled only when the mp bit in smr is 1 in asynchronous mode) write 0 to this bit in smart card interface mode. when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr, are not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting are enabled. 2 teie 0 r/w transmit end interrupt enable write 0 to this bit in smart card interface mode. tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. 1 0 cke1 cke0 0 0 r/w r/w clock enable 1 and 0 enable or disable clock output from the sck pin. the clock output can be dynamically switched in gsm mode. for details, refer to section 13.7.7, clock output control. when the gm bit in smr is 0: 00: output disabled (sck pin functions as an input pin (ignored) or as an output pin (level is undefined)) 01: clock output 1x: reserved when the gm bit in smr is 1: 00: output fixed low 01: clock output 10: output fixed high 11: clock output [legend] x: don?t care 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 407 of 882 rej09b0108-0400 13.3.7 serial status register (ssr) ssr is a register containing st atus flags of the sci and multiprocessor bits for transfer. 1 cannot be written to flags tdre, rdrf, orer, per, and fer; they can only be cleared. some bit functions of ssr differ between normal serial communication interface mode and smart card interface mode. ? normal serial communication interf ace mode (when smif in sdcr is 0) bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? power-on reset or software standby mode ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dmac is activated by a txi interrupt request. ? when the dtc is activated by a txi interrupt request and transferred data to tdr while the disel bit in dtmr of dtc is 0. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 408 of 882 rej09b0108-0400 bit bit name initial value r/w description 6 rdrf 0 r/(w) * receive data register full indicates that the received data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to rdrf after reading rdrf = 1 ? when the dmac is activated by a rxi interrupt request. ? when the dtc is activated by an rxi interrupt and transferred data from rdr while the disel bit in dtmr of dtc is 0. rdr and the rdrf flag are not affected and retain their previous states even if the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. 5 orer 0 r/(w) * overrun error indicates that an overrun error occurred during reception, causing abnormal termination. [setting condition] ? when the next serial reception is completed while rdrf = 1 the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued either. [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains its previous value when the re bit in scr is cleared to 0. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 409 of 882 rej09b0108-0400 bit bit name initial value r/w description 4 fer 0 r/(w) * framing error indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. [setting condition] ? when the stop bit is 0 in 2 stop bit mode, only the first stop bit is checked for a value to 1; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to fer after reading fer = 1 the fer flag is not affected and retains its previous value when the re bit in scr is cleared to 0. 3 per 0 r/(w) * parity error indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [setting condition] ? when a parity error is detected during reception if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to per after reading per = 1 the per flag is not affected and retains its previous value when the re bit in scr is cleared to 0. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 410 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 tend 1 r transmit end indicates that transmission has been ended. [setting conditions] ? power-on reset or software standby mode ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dmac is activated by a txi interrupt request. ? when the dtc is activated by a txi interrupt and transmit data is written to tdr while the disel bit in dtmr of dtc is 0. 1 mpb 0 r multiprocessor bit stores the multiprocessor bit in the receive data. when the re bit in scr is cleared to 0, its previous state is retained. 0 mpbt 0 r/w multiprocessor bit transfer sets the multiprocessor bit value to be added to the transmit data. note: * only 0 can be written to clear the flag. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 411 of 882 rej09b0108-0400 ? smart card interface mode (w hen smif in sdcr is 1) bit bit name initial value r/w description 7 tdre 1 r/(w) * transmit data register empty indicates whether tdr contains transmit data. [setting conditions] ? power-on reset or software standby mode ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dmac is activated by a txi interrupt ? when the dtc is activated by a txi interrupt and transmit data is transferred to tdr while the disel bit in dtmr of the dtc is 0 6 rdrf 0 r/(w) * receive data register full indicates that the receive data is stored in rdr. [setting condition] ? when serial reception ends normally and receive data is transferred from rsr to rdr [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to rdrf after reading rdrf = 1 ? when the dmac is activated by an rxi interrupt ? when the dtc is activated by an rxi interrupt and data is transferred from rdr while the disel bit in dtmr of the dtc is 0 the rdrf flag is not affected and retains its previous value even if the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 412 of 882 rej09b0108-0400 bit bit name initial value r/w description 5 orer 0 r/(w) * overrun error indicates that an overrun error occurred during reception, causing abnormal termination. [setting condition] ? when the next serial reception is completed while rdrf = 1 the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to orer after reading orer = 1 the orer flag is not affected and retains its previous state even if the re bit in scr is cleared to 0. 4 ers 0 r/(w) * error signal status indicates that the status of an error signal returned from the receive side at transmission. [setting condition] ? when the low level of the error signal is sampled [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to ers after reading ers = 1 the ers flag is not affected and retains its previous state even if the te bit in scr is cleared to 0. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 413 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 per 0 r/(w) * parity error indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. [setting condition] ? when a parity error is detected during reception if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. [clearing conditions] ? power-on reset or software standby mode ? when 0 is written to per after reading per = 1 the per flag is not affected and retains its previous state even if the re bit in scr is cleared to 0. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 414 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 tend 1 r transmit end this bit is set to 1 when no error signal has been sent back from the receive side and the next transmit data is ready to be transferred to tdr. [setting conditions] ? power-on reset or software standby mode ? when the te bit in scr is 0 and the esr bit is also 0 ? when the esr bit is 0 and the tdre bit is 1 after the specified interval following transmission of 1-byte data the timing of bit setting differs according to the register setting as follows: when gm = 0 and blk = 0, 2.5 etu after transmission starts when gm = 0 and blk = 1, 1.0 etu after transmission starts when gm = 1 and blk = 0, 1.5 etu after transmission starts when gm = 1 and blk = 1, 1.0 etu after transmission starts [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dmac is activated by a txi interrupt ? when the dtc is activated by a txi interrupt and transmit data is transferred to tdr while the disel bit in dtmr of the dtc is 0 1 mpb 0 r multiprocessor this bit is not used in smart card interface mode. 0 mpbt 0 r/w multiprocessor bit transfer write 0 to this bit in smart card interface mode. note: * only 0 can be written to clear the flag. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 415 of 882 rej09b0108-0400 13.3.8 serial direction control register (sdcr) sdcr selects lsb-first or msb-first transfer and se ts the smart card interface. with an 8-bit data length, lsb-first/msb-first selection is available regardless of the communication mode. with a 7-bit data length, lsb-first transfer must be selected. the description in this section assumes lsb- first transfer. bit bit name initial value r/w description 7 to 4 ? all 1 r reserved the write value should al ways be 1. operation cannot be guaranteed if 0 is written. 3 dir 0 r/w data transfer direction selects the serial/parallel conversion direction. 0: transfer in lsb-first 1: transfer in msb-first the bit setting is valid only when the transfer data format is 8 bits. for 7-bit data, lsb-first is fixed. 2 sinv 0 r/w smart card data invert specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit. to invert the parity bit, invert the o/ e bit in smr. this bit is valid only in smart card interface mode. in normal asynchronous mode or clocked synchronous mode, clear this bit to 0. 0: tdr contents are transmitt ed as they are. receive data is stored as it is in rdr 1: tdr contents are in verted before being transmitted. receive data is stored in inverted form in rdr 1 ? 1 r reserved this bit is always read as 1 and cannot be modified. 0 smif 0 r/w smart card interface mode select this bit is set to 1 to make the sci operate in smart card interface mode. 0: normal asynchronous mode or clocked synchronous mode 1: smart card interface mode 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 416 of 882 rej09b0108-0400 13.3.9 bit rate register (brr) brr is an 8-bit register that adjusts the bit rate. as the sci performs baud rate generator control independently for each channel, different bit rates can be set for each channel. table 13.2 shows the relationships between the n setting in brr and the effective bit rate b 0 for asynchronous, clocked synchronous, and smart card interface modes. the initial value of brr is h'ff, and it can be read from or written to by the cpu at all times. table 13.2 relationships between n sett ing in brr and effective bit rate b 0 mode asynchronous mode (n = 0) asynchronous mode (n = 1 to 3) clocked synchronous mode (n = 0) clocked synchronous mode (n = 1 to 3) b 0 = p 10 6 32 2 2n (n + 1) bit rate error b 0 b 1 smaet card interface mode (n = 0) smaet card interface mode (n = 1 to 3) b 0 = p 10 6 32 2 2n+1 (n + 1) b 0 = p 10 6 4 2 2n (n + 1) b 0 = p 10 6 4 2 2n+1 (n + 1) b 0 = p 10 6 s 2 2n+1 (n + 1) b 0 = p 10 6 s 2 2n+2 (n + 1) error (%) = ? 1 100 ? ? ? ? b 0 b 1 error (%) = ? ? ? 1 100 ? ? ? ? b 0 b 1 error (%) = ? 1 100 ? ? ? ? b 0 b 1 error (%) = ? 1 100 ? ? ? ? [legend] b 0 : effective bit rate (bit/s) actual transfe r speed according to the register settings b 1 : logical bit rate (bit/s) specified transfer speed of the target system n: brr setting for baud rate generator (0 n 255) p : peripheral clock operating frequency (mhz) n and s: determined by the smr settings shown in the following tables. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 417 of 882 rej09b0108-0400 smr setting cks1 cks0 n 0 0 0 0 1 1 1 0 2 1 1 3 smr setting bcp1 bcp0 s 0 0 32 0 1 64 1 0 372 1 1 256 table 13.3 shows sample n settings in brr in normal asynchronous mode. table 13.4 shows the maximum bit rate for each frequency in normal asynchronous mode. table 13.6 shows sample n settings in brr in clocked synchronous mode. table 13.8 shows sample n settings in brr in smart card interface mode. table 13.9 shows the maxi mum bit rate for each frequency in smart card interface mode. for details, refer to secti on 13.4.2, receive data sampling timing and reception margin in async hronous mode and section 13.7.4, r eceive data sampling timing and reception margin. tables 13 .5 and 13.7 show the maximum bit rates with external clock input. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 418 of 882 rej09b0108-0400 table 13.3 brr settings for various bit rates (asynchronous mode) (1) operating frequency p (mhz) 4 6 8 10 12 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 1 140 0.74 1 212 0.03 2 70 0.03 2 88 ?0.25 2 106 ?0.44 150 1 103 0.16 1 155 0.16 2 51 0.16 2 64 0.16 2 77 0.16 300 1 51 0.16 1 77 0.16 2 25 0.16 1 129 0.16 2 38 0.16 600 1 25 0.16 1 38 0.16 2 12 0.16 1 64 0.16 1 77 0.16 1200 1 12 0.16 0 155 0.16 1 25 0.16 1 32 ?1.36 1 38 0.16 2400 0 51 0.16 0 77 0.16 1 12 0.16 0 129 0.16 0 155 0.16 4800 0 25 0.16 0 38 0.16 0 51 0.16 0 64 0.16 0 77 0.16 9600 0 12 0.16 0 19 ?2.34 0 25 0.16 0 32 ?1.36 0 38 0.16 14400 0 8 ?3.55 0 12 0.16 0 16 2.12 0 21 ?1.36 0 25 0.16 19200 0 6 ?6.99 0 9 ?2.34 0 12 0.16 0 15 1.73 0 19 ?2.34 28800 0 3 8.51 0 6 ?6.99 0 8 ?3.55 0 10 ?1.36 0 12 0.16 31250 0 3 0.00 0 5 0.00 0 7 0.00 0 9 0.00 0 11 0.00 38400 0 2 8.51 0 4 ?2.34 0 6 ?6.99 0 7 1.73 0 9 ?2.34 table 13.3 brr settings for various bit rates (asynchronous mode) (2) operating frequency p (mhz) 14 16 18 20 22 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 123 0.23 2 141 0.03 2 159 ?0.12 2 177 ?0.25 2 194 0.16 150 2 90 0.16 2 103 0.16 2 116 0.16 2 129 0.16 2 142 0.16 300 2 45 ?0.93 2 51 0.16 2 58 ?0.69 2 64 0.16 2 71 ?0.54 600 2 22 ?0.93 1 103 0.16 1 116 0.16 1 129 0.16 1 142 0.16 1200 1 45 ?0.93 1 51 0.16 1 58 ?0.69 1 64 0.16 1 71 ?0.54 2400 1 22 ?0.93 0 207 0.16 0 233 0.16 1 32 ?1.36 1 35 ?0.54 4800 0 90 0.16 0 103 0.16 0 116 0.16 0 129 0.16 0 142 0.16 9600 0 45 ?0.93 0 51 0.16 0 58 ?0.69 0 64 0.16 0 71 ?0.54 14400 0 29 1.27 0 34 ?0.79 0 38 0.16 0 42 0.94 0 47 ?0.54 19200 0 22 ?0.93 0 25 0.16 0 28 1.02 0 32 ?1.36 0 35 ?0.54 28800 0 14 1.27 0 16 2.12 0 19 ?2.34 0 21 ?1.36 0 23 ?0.54 31250 0 13 0.00 0 15 0.00 0 17 0.00 0 19 0.00 0 21 0.00 38400 0 10 3.57 0 12 0.16 0 14 ?2.34 0 15 1.73 0 17 ?0.54 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 419 of 882 rej09b0108-0400 table 13.3 brr settings for various bit rates (asynchronous mode) (3) operating frequency p (mhz) 24 25 26 28 30 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 2 212 0.03 2 221 ?0.02 2 230 ?0.08 2 248 ?0.17 3 66 ?0.62 150 2 155 0.16 2 162 ?0.15 2 168 0.16 2 181 0.16 2 194 0.16 300 2 77 0.16 2 80 0.47 2 84 ?0.43 2 90 0.16 2 97 ?0.35 600 1 155 0.16 1 162 ?0.15 1 168 0.16 1 181 0.16 2 48 ?0.35 1200 1 77 0.16 1 80 0.47 1 84 ?0.43 1 90 0.16 1 97 ?0.35 2400 1 38 0.16 1 40 ?0.76 1 41 0.76 1 45 ?0.93 1 48 ?0.35 4800 0 155 0.16 0 162 ?0.15 0 168 0.16 0 181 0.16 0 194 0.16 9600 0 77 0.16 0 80 0.47 0 84 ?0.43 0 90 0.16 0 97 ?0.35 14400 0 51 0.16 0 53 0.47 0 55 0.76 0 60 ?0.39 0 64 0.16 19200 0 38 0.16 0 40 ?0.76 0 41 0.76 0 45 ?0.93 0 48 ?0.35 28800 0 25 0.16 0 26 0.47 0 27 0.76 0 29 1.27 0 32 ?1.36 31250 0 23 0.00 0 24 0.00 0 25 0.00 0 27 0.00 0 29 0.00 38400 0 19 ?2.34 0 19 1.73 0 20 0.76 0 22 ?0.93 0 23 1.73 table 13.3 brr settings for various bit rates (asynchronous mode) (4) operating frequency p (mhz) 32 34 36 38 40 logical bit rate (bit/s) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) n n error ( % ) 110 3 70 0.03 3 74 0.62 3 79 ?0.12 3 83 0.40 3 88 ?0.25 150 2 207 0.16 2 220 0.16 2 233 0.16 2 246 0.16 3 64 0.16 300 2 103 0.16 2 110 ?0.29 2 116 0.16 2 123 ?0.24 2 129 0.16 600 2 51 0.16 2 54 0.62 2 58 ?0.69 2 61 ?0.24 2 64 0.16 1200 1 103 0.16 1 110 ?0.29 1 116 0.16 1 123 ?0.24 1 129 0.16 2400 1 51 0.16 1 51 6.42 1 58 ?0.69 1 61 ?0.24 1 64 0.16 4800 0 207 0.16 0 220 0.16 0 234 ?0.27 0 246 0.16 1 32 ?1.36 9600 0 103 0.16 0 110 ?0.29 0 116 0.16 0 123 ?0.24 0 129 0.16 14400 0 68 0.64 0 73 ?0.29 0 77 0.16 0 81 0.57 0 86 ?0.22 19200 0 51 0.16 0 54 0.62 0 58 ?0.69 0 61 ?0.24 0 64 0.16 28800 0 34 ?0.79 0 36 ?0.29 0 38 0.16 0 40 0.57 0 42 0.94 31250 0 31 0.00 0 33 0.00 0 35 0.00 0 37 0.00 0 39 0.00 38400 0 25 0.16 0 27 ?1.18 0 28 1.02 0 30 ?0.24 0 32 ?1.36 note: settings with an error of 1 % or less are recommended. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 420 of 882 rej09b0108-0400 table 13.4 maximum bit rate for each f requency when using ba ud rate generator (asynchronous mode) p (mhz) n n maximum bit rate (bit/s) 4 0 0 125000 8 0 0 250000 10 0 0 312500 12 0 0 375000 14 0 0 437500 16 0 0 500000 18 0 0 562500 20 0 0 625000 22 0 0 687500 24 0 0 750000 25 0 0 781250 26 0 0 812500 28 0 0 875000 30 0 0 937500 32 0 0 1000000 34 0 0 1062500 36 0 0 1125000 38 0 0 1187500 40 0 0 1250000 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 421 of 882 rej09b0108-0400 table 13.5 maximum bit rate with external clock input (asynchronous mode) p (mhz) external clock (mhz) maximum bit rate (bit/s) 4 1.0000 62500 6 1.5000 93750 8 2.0000 125000 10 2.5000 156250 12 3.0000 187500 14 3.5000 218750 16 4.0000 250000 18 4.5000 281250 20 5.0000 312500 22 5.5000 343750 24 6.0000 375000 25 6.2500 390625 26 6.5000 406250 28 7.0000 437500 30 7.5000 468750 32 8.0000 500000 34 8.5000 531250 36 9.0000 562500 38 9.5000 593750 40 10.0000 625000 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 422 of 882 rej09b0108-0400 table 13.6 brr settings for various bit rates (clocked synchronous mode) (1) operating frequency p (mhz) 4 6 8 10 12 logical bit rate (bit/s) n n n n n n n n n n 250 2 124 2 187 2 249 3 77 3 93 500 1 249 2 93 2 124 2 155 2 187 1000 1 124 1 187 1 249 2 77 2 93 2500 1 49 1 74 1 99 1 124 1 149 5000 1 24 ? ? 1 49 1 61 1 74 10000 0 99 0 149 1 24 0 249 ? ? 25000 0 39 0 59 1 9 0 99 1 14 50000 0 19 0 29 1 4 0 49 0 59 100000 0 9 0 14 0 19 0 24 0 29 250000 0 3 0 5 0 7 0 9 0 11 500000 0 1 0 2 0 3 0 4 0 5 1000000 0 0 * ? ? 0 1 ? ? 0 2 2500000 ? ? ? ? ? ? 0 0 * ? ? 5000000 ? ? ? ? ? ? ? ? ? ? table 13.6 brr settings for various bit rates (clocked synchronous mode) (2) operating frequency p (mhz) 14 16 18 20 22 logical bit rate (bit/s) n n n n n n n n n n 250 3 108 3 124 3 140 3 155 3 171 500 2 218 2 249 3 69 3 77 3 85 1000 2 108 2 124 2 140 2 155 3 42 2500 1 174 2 49 1 224 1 249 2 68 5000 1 86 2 24 1 112 1 124 1 137 10000 1 43 1 49 1 55 1 62 1 68 25000 0 139 1 19 0 179 1 24 0 219 50000 0 69 1 9 0 89 0 99 0 109 100000 0 34 1 4 0 44 0 49 0 54 250000 0 13 1 1 0 17 0 19 0 21 500000 0 6 1 0 0 8 0 9 0 10 1000000 ? ? 0 3 ? ? 0 4 ? ? 2500000 ? ? ? ? ? ? 0 1 ? ? 5000000 ? ? ? ? ? ? 0 0 * ? ? 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 423 of 882 rej09b0108-0400 table 13.6 brr settings for various bit rates (clocked synchronous mode) (3) operating frequency p (mhz) 24 25 26 28 30 logical bit rate (bit/s) n n n n n n n n n n 250 3 187 3 194 3 202 3 218 3 233 500 3 93 3 97 3 101 3 108 3 116 1000 2 187 2 194 2 202 2 218 2 233 2500 2 74 2 77 2 80 2 86 2 93 5000 1 149 1 155 1 162 1 174 1 187 10000 1 74 1 77 1 80 1 86 1 93 25000 1 29 0 249 ? ? 1 34 ? ? 50000 1 14 0 124 0 129 0 139 0 149 100000 0 59 0 62 0 64 0 69 0 74 250000 0 23 0 24 0 25 0 27 0 29 500000 0 11 ? ? 0 12 0 13 0 14 1000000 0 5 ? ? ? ? 0 6 ? ? 2500000 ? ? ? ? ? ? ? ? 0 2 5000000 ? ? ? ? ? ? ? ? ? ? table 13.6 brr settings for various bit rates (clocked synchronous mode) (4) operating frequency p (mhz) 32 34 36 38 40 logical bit rate (bit/s) n n n n n n n n n n 250 3 249 ? ? ? ? ? ? ? ? 500 3 124 3 132 3 140 3 147 3 155 1000 2 249 3 65 3 69 3 73 3 77 2500 2 99 2 105 2 112 2 118 2 124 5000 2 49 1 212 1 224 1 237 1 249 10000 2 24 1 105 1 112 1 118 1 124 25000 2 9 ? ? 1 44 ? ? 1 49 50000 2 4 0 169 0 179 0 189 1 24 100000 1 9 0 84 0 89 0 94 0 99 250000 1 3 0 33 0 35 0 37 0 39 500000 1 1 0 16 0 17 0 18 0 19 1000000 1 0 ? ? 0 8 ? ? 0 9 2500000 ? ? ? ? ? ? ? ? 0 3 5000000 ? ? ? ? ? ? ? ? 0 1 [legend] ? : can be set, but there will be a degree of error. * : continuous transfer is not possible. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 424 of 882 rej09b0108-0400 table 13.7 maximum bit rate with external clock input (clocked synchronous mode) p (mhz) external clock (mhz) maximum bit rate (bit/s) 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 22 3.6667 3666666.7 24 4.0000 4000000.0 25 4.1667 4166666.7 26 4.3333 4333333.3 28 4.6667 4666666.7 30 5.0000 5000000.0 32 5.3333 5333333.3 34 5.6667 5666666.7 36 6.0000 6000000.0 38 6.3333 6333333.3 40 6.6667 6666666.7 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 425 of 882 rej09b0108-0400 table 13.8 examples of bit rate for variou s brr settings (smart card interface mode) (when n = 0 and s = 372) operating frequency p (mhz) 4 8 16 24 25 bit rate (bps) n error (%) n error (%) n error (%) n error (%) n error (%) 9600 0 44 0 12 1 12 2 12 3 12 operating frequency p (mhz) 32 40 bit rate (bps) n error (%) n error (%) 9600 3 12 3 40 table 13.9 maximum bit rate at various f requencies (smart card interface mode) (when s = 372) p (mhz) maximum bit rate (bps) n n 4 5376 0 0 8 10753 0 0 16 21505 0 0 24 32258 0 0 25 33602 0 0 32 43011 0 0 40 53763 0 0 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 426 of 882 rej09b0108-0400 13.4 operation in asynchronous mode figure 13.2 shows the general format for asynchronous serial communication. one frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the comm unication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex commun ication. both the tran smitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit or none one unit of transfer data (character or frame) figure 13.2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 427 of 882 rej09b0108-0400 13.4.1 data transfer format table 13.10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. for details on the multiprocessor bit, refer to section 13.5, multiprocessor communication function. table 13.10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 x x x x s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 1234567 8 9 101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop [le g end] s: start bit stop: stop bit p: parity bit mpb: multiprocessor bit x: don?t care 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 428 of 882 rej09b0108-0400 13.4.2 receive data samplin g timing and reception marg in in asynchronous mode in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the bit rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched inte rnally at the rising edge of the 8th pulse of the basic clock as shown in figure 13.3. thus the reception margin in asynchronous mode is given by formula (1) below. m = 0. 5 ? 1 2n (d ? 0. 5 ) n ? ? (l ? 0.5) f 100% ............................ formula (1) where m: reception margin ( % ) n: ratio of bit rate to clock (n = 16) d: clock duty (d = 0 to 1.0) l: frame length (l = 9 to 12) f: absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin is given by formula below. m = {0.5 ? 1/(2 16)} 100 [%] = 46.875% however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization samplin g timin g start bit d0 d1 data samplin g timin g 15 0 7 15 0 0 7 figure 13.3 receive data sampling timing in asynchronous mode 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 429 of 882 rej09b0108-0400 13.4.3 clock either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as th e sci?s serial clock, according to the setting of the c/a bit in smr and the cke1 and cke0 bits in scr. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13.4. the clock must not be stopped during operation. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 sck txd figure 13.4 relation between output clock and transmit data phase (asynchronous mode) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 430 of 882 rej09b0108-0400 13.4.4 sci initializatio n (asynchronous mode) before transmitting and receiving da ta, you should first clear the te an d re bits in scr to 0, then initialize the sci as described below. when the ope rating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not initialize the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when the external clock is used in asynchronous mode, the clock must be supplied even during initialization. wait yes [1] start transmission clear rie, tie, teie, mpie, * te and re bits in scr to 0 [2] no set value in brr [3] [4] [5] 1-bit interval elapsed? < initialization completion> [1] set the clock selection in scr. [2] set the data transfer format in smr and scmr. [3] write a value correspondin g to the bit rate to brr. not necessary if an external clock is used. [4] set pfc of the external pin used. set rxd input durin g receivin g and txd output durin g transmittin g . set sck input/output accordin g to contents set by cke1 and cke0. when cke1 and cke0 are 0 in asynchronous mode, settin g the sck pin is unnecessary. outputtin g clocks from the sck pin starts at synchronous clock output settin g . [5] wait at least one bit interval, then set the te bit or re bit in scr to 1. * at this time, the txd, rxd, and sck pins can be used. the txd pin is in a mark state durin g transmittin g , and rxd pin is in an idle state for waitin g the start bit durin g receivin g . set data transfer format in smr set pfc of the external pin used sck, txd, rxd set rie, tie, teie, and mpie bits set te and re bits in scr to 1 set cke1 and cke0 bits in scr (te and re bits are 0) note: * in simultaneous transmit/receive operation, the te and re bits must be cleared to 0 or set to 1 simultaneously. figure 13.5 sample sci initialization flowchart 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 431 of 882 rej09b0108-0400 13.4.5 data transmission (asynchronous mode) figure 13.6 shows an example of the operation for transmission in asynchronous mode. in transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if is cleared to 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt request (txi) is generated. because the txi in terrupt routine writes the next transmit data to tdr before transmission of the current transmit data has fi nished, continuous transmission can be enabled. 3. data is sent from the txd pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. the sci checks the tdre flag at the timing for sending the stop bit. 5. if the tdre flag is 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. 6. if the tdre flag is 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?mark state? is entered in which 1 is output. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit data written to tdr and tdre fla g cleared to 0 in txi interrupt processin g routine tei interrupt request g enerated idle state (mark state) txd txi interrupt request g enerated txi interrupt request g enerated figure 13.6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 432 of 882 rej09b0108-0400 figure 13.7 shows a sample flowchart fo r transmission in asynchronous mode. no 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 433 of 882 rej09b0108-0400 13.4.6 serial data recep tion (asynchronous mode) figure 13.8 shows an example of the operation for reception in asynchronous mode. in serial reception, the sci operates as described below. 1. the sci monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in rsr, and checks the parity bit and stop bit. 2. if an overrun error (when reception of the next data is completed while the rdrf flag is still set to 1) occurs, the oer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive data is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if a parity error is detected, the per bit in ss r is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 4. if a framing error (when the stop bit is 0) is detected, the fer bit in ssr is set to 1 and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. 5. if reception finishes successfully, the rdrf b it in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interr upt processing routine reads th e receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit eri interrupt request g enerated by framin g error idle state (mark state) rdr data read and rdrf fla g cleared to 0 in rxi interrupt processin g routine rxi interrupt request g enerated rxd figure 13.8 example of sci operation in reception (example with 8-bit data, parity, one stop bit) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 434 of 882 rej09b0108-0400 table 13.11 shows the states of the ssr status flags and receive data handling when a receive error is detected. if a receive error is detected, the rdrf flag retains its state before receiving data. reception cannot be resumed while a receive error flag is se t to 1. accordingly, clear the oer, fer, per, and rdrf bits to 0 before resuming reception. figure 13.9 shows a sample flow chart for serial data reception. table 13.11 ssr status flag s and receive data handling ssr status flag rdrf * oer fer per receive data receive error type 1 1 0 0 lost overrun error 0 0 1 0 transferred to rdr framing error 0 0 0 1 transferred to rdr parity error 1 1 1 0 lost overrun error + framing error 1 1 0 1 lost overrun error + parity error 0 0 1 1 transferred to rdr framing error + parity error 1 1 1 1 lost overrun error + framing error + parity error note: * the rdrf flag retains its st ate before data reception. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 435 of 882 rej09b0108-0400 yes 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 436 of 882 rej09b0108-0400 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 437 of 882 rej09b0108-0400 13.5 multiprocessor communication function use of the multiprocessor communication function en ables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. when multiprocessor communicati on is carried out, each receiving station is addressed by a unique id code. the serial communi cation cycle consists of two component cycles: an id transmission cycle which sp ecifies the receiving st ation, and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. if the multiprocessor bit is 1, th e cycle is an id transmi ssion cycle, and if the multiprocessor bit is 0, the cycle is a data transm ission cycle. figure 13.10 shows an example of inter-processor communication using the multipro cessor format. the transmitting station first sends the id code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station sk ips data until data with a 1 multip rocessor bit is sent. when data with a 1 multiprocessor bit is recei ved, the receiving station compar es that data with its own id. the station whose id matches then receives the data sent next. stations wh ose id does not match continue to skip data until data with a 1 multiprocesso r bit is again received. the sci uses the mpie bit in scr to implement this function. when the mpie bit is set to 1, transfer of receive data from rsr to rdr, error flag detection, and setting the ssr status flags, rdrf, fer, and oer to 1 are inhibited until da ta with a 1 multiprocesso r bit is received. on reception of receive character with a 1 multiprocessor bit, the mpbr bit in ssr is set to 1 and the mpie bit is automatically cleared, thus normal reception is resumed. if the rie bit in scr is set to 1 at this time, an rxi interrupt is generated. when the multiprocessor format is selected, the parity bit setting is invalid. all other bit settings are the same as those in no rmal asynchronous mode. the clock used for multiprocessor communication is the same as that in normal asynchronous mode. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 438 of 882 rej09b0108-0400 transmittin g station receivin g station a (id = 01) receivin g station b (id = 02) receivin g station c (id = 03) receivin g station d (id = 04) serial transmission line serial data id transmission cycle = receivin g station specification data transmission cycle = data transmission to receivin g station specified by id (mpb = 1) (mpb = 0) h'01 h'aa [le g end] mpb: multiprocessor bit figure 13.10 example of communica tion using multip rocessor format (transmission of data h'aa to receiving station a) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 439 of 882 rej09b0108-0400 13.5.1 multiprocessor seri al data transmission figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. for an id transmission cycle, set the mpbt bit in ssr to 1 before transmission. for a data transmission cycle, clear the mpbt b it in ssr to 0 before transmission. all other sci operations are the same as those in asynchronous mode. no 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 440 of 882 rej09b0108-0400 13.5.2 multiprocessor s erial data reception figure 13.13 shows a sample flowchart for multiproces sor serial data reception. if the mpie bit in scr is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. on receiving data with a 1 multiprocessor bi t, the receive data is transferred to rdr. an rxi interrupt request is generated at this time. all other sci operations are the same as in asynchronous mode. figure 13.12 shows an example of sci operatio n for multiprocessor format reception. mpie rxd rxd rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 01 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit data (id2) start bit stop bit start bit data (data2) stop bit rxi interrupt request (multiprocessor interrupt) g enerated idle state (mark state) rdrf rdr data read and rdrf fla g cleared to 0 in rxi interrupt processin g routine if not this station?s id, mpie bit is set to 1 a g ain rxi interrupt request is not g enerated, and rdr retains its state id1 (a) data does not match station?s id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 01 1 1 mpb mpb rxi interrupt request (multiprocessor interrupt) g enerated idle state (mark state) rdrf rdr data read and rdrf fla g cleared to 0 in rxi interrupt processin g routine matches this station?s id, so reception continues, and data is received in rxi interrupt processin g routine mpie bit is set to 1 a g ain id2 (b) data matches station?s id data2 id1 mpie = 0 mpie = 0 figure 13.12 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 441 of 882 rej09b0108-0400 yes 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 442 of 882 rej09b0108-0400 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 443 of 882 rej09b0108-0400 13.6 operation in clocked synchronous mode figure 13.14 shows the general format for clocked synchronous communication. in clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. data is transferred in 8-bit units. in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. in clocked synchronous mode, the sci receives data in synchroniza tion with the rising edge of the se rial clock. after 8-bit data is output, the transmission line holds the msb state. in clocked synchronous mode, no parity or multiprocessor bit is adde d. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be r ead or written during transmission or reception, enab ling continuous data transfer. don?t care don?t care one unit of transfer data (character or frame) bit 0 serial data synchronization clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * * note: * hi g h except in continuous transfer figure 13.14 data format in clocked synchronous communication (for lsb-first) 13.6.1 clock either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the sck pin can be selected, according to the setting of cke1 and cke0 bits in scr. when the sci is operated on an internal clock, the serial clock is output from the sck pin. eight serial clock pulses are output in the transfer of one character, and when no transfer is performed, the cl ock is fixed high. however, du ring receive-only operation the synchronization clock is output until an overrun error occurs or the re bit is cleared to 0. when receive operation in single-character units is desired, select an external clock as the clock source. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 444 of 882 rej09b0108-0400 13.6.2 sci initialization (clocked synchronous mode) before transmitting and receiving da ta, you should first clear the te an d re bits in scr to 0, then initialize the sci as described in a sample flowch art in figure 13.15. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te b it is cleared to 0, the tdre flag is set to 1. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. wait no yes 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 445 of 882 rej09b0108-0400 13.6.3 serial data transmission (clocked synchronous mode) figure 13.16 shows an example of sci operation for transmission in clocked synchronous mode. in serial transmission, the sci operates as described below. 1. the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. 2. after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty (txi) interrupt request is generated. because the txi interrup t routine writes the next transmit data to tdr before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the txd pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. the sci checks the tdre flag at the timing for sending the msb (bit 7). 5. if the tdre flag is cleared to 0, data is tr ansferred from tdr to tsr, and serial transmission of the next frame is started. 6. if the tdre flag is set to 1, the tend flag in ssr is set to 1, and the txd pin maintains the output state of the last bit. if the teie bit in s cr is set to 1 at this time, a tei interrupt request is generated. the sck pin is fixed high. figure 13.17 shows a sample flowchart for serial data transmission. even if the tdre flag is cleared to 0, transmission will not start while a receive error flag (o rer, fer, or per) is set to 1. make sure to clear the receive error flags to 0 be fore starting transmission. note that clearing the re bit to 0 does not clear the receive error flags. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 446 of 882 rej09b0108-0400 transfer direction bit 0 serial data synchroniza- tion clock 1 frame tdre tend bit 1 bit 7 bit 0 bit 1 bit 6 bit 7 txi interrupt request g enerated data written to tdr and tdre fla g cleared to 0 in txi interrupt processin g routine tei interrupt request g enerated txi interrupt request g enerated figure 13.16 sample sci transmission operation in clocked synchronous mode no 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 447 of 882 rej09b0108-0400 13.6.4 serial data reception (clocked synchronous mode) figure 13.18 shows an example of sci operation for reception in clocked synchronous mode. in serial reception, the sci operates as described below. 1. the sci performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, an d stores the received data in rsr. 2. if an overrun error (when reception of the next data is completed while the rdrf flag is still set to 1) occurs, the orer bit in ssr is set to 1. if the rie bit in scr is set to 1 at this time, an eri interrupt request is generated. receive da ta is not transferred to rdr. the rdrf flag remains to be set to 1. 3. if reception finishes successfully, the rdrf b it in ssr is set to 1, and receive data is transferred to rdr. if the rie bit in scr is set to 1 at this time, an rxi interrupt request is generated. because the rxi interr upt processing routine reads th e receive data transferred to rdr before reception of the next receive data has finished, continuous reception can be enabled. bit 7 serial data synchroniza- tion clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request g enerated rdr data read and rdrf fla g cleared to 0 in rxi interrupt processin g routine eri interrupt request g enerated by overrun error rxi interrupt request g enerated figure 13.18 example of sci operation in reception 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 448 of 882 rej09b0108-0400 reception cannot be resumed while a receive error flag is set to 1. accordingly, clear the orer, fer, per, and rdrf bits to 0 before resuming reception. figure 13.19 shows a sample flowchart for serial data reception. an overrun error occurs or synchronous clocks ar e output until the re bit is cleared to 0 when an internal clock is selected and only receive operatio n is possible. when reception will be carried out in a unit of one frame, be sure to carry out a dummy transmission with only one frame by the simultaneous transmit and receive operations at the same time. yes 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 449 of 882 rej09b0108-0400 13.6.5 simultaneous serial data transmission and recep tion (clocked synchronous mode) figure 13.20 shows a samp le flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations after the sci initialization. to switch fr om transmit mode to simultaneous transmit and receive mode, after checking that the sci has fi nished transmission and the tdre and tend flags are set to 1, clear te to 0. then simultaneou sly set te and re to 1 with a single instruction. to switch from receive mode to simultaneous transmit and receive mode, after checking that the sci has finished reception, clear re to 0. then after checking that the rdrf and receive error flags (orer, fer, and per) are cleared to 0, si multaneously set te and re to 1 with a single instruction. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 450 of 882 rej09b0108-0400 yes 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 451 of 882 rej09b0108-0400 13.7 smart card interface the sci supports an ic card (smart card ) interface that confor ms to iso/iec 7816-3 (identification card) as an exte nsion function for the serial comm unication interface. switching to smart card interface mode is carried out by means of a register setting. 13.7.1 pin connection example figure 13.21 shows an example of connection with the smart card. in communication with an ic card, as both transmission and r eception are carried out on a single data transmission line, but the txd pin is always fixed to output. note that the following controls are needed to avoid signal collision: (1) control of data directions between txd and i/o in the external circuit and (2) setting of the txd pin to an input port except in transmission. similarly, since the rxd pin is always fixed to input, connect a pull-up resistor to avoid the open state. when the clock generated by the sci is supplied to an ic card, the sck pin output is input to the clk pin of the ic card. if an internal clock is used in an ic card, the connection between the sck and clk pins is unnecessary. this lsi port output can be used as the reset signal. connection between the power supply and ground pins is also necessary. txd rxd this lsi v cc i/o ic card data line external circuit clk rst sck port clock line reset line figure 13.21 example of pin conn ections for smart card interface 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 452 of 882 rej09b0108-0400 13.7.2 data format (except for block transfer mode) figure 13.22 shows the transfer data format in smart card interface mode. ? one frame consists of 8-bit data plus a parity bit in asynchronous mode. ? in transmission, a guard time of at least 2 et u (elementary time unit: th e time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. ? if a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. ? if an error signal is sampled during transmission, the same data is retransmitted automatically after a delay of 2 etu or longer. ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmittin g station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmittin g station output de receivin g station output start bit data bits parity bit error si g nal [le g end] ds: d0 to d7: dp: de: figure 13.22 normal smart card interface data format data transfer with other types of ic cards (direct convention and inverse convention) should be performed as described in the following. ds azzazz z za a (z) (z) state d0 d1 d2 d3 d4 d5 d6 d7 dp figure 13.23 direct conv ention (dir = sinv = o/ e = 0) with the direction convention type ic and the above sample start character, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the above start character data is h'3b. for the direct convention type, clear the dir and sinv 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 453 of 882 rej09b0108-0400 bits in sdcr to 0. according to smart card regulations, clear the o/ e bit in smr to 0 to select even parity mode. ds azzaaa z aa a (z) (z) state d7 d6 d5 d4 d3 d2 d1 d0 dp figure 13.24 inverse conv ention (dir = sinv = o/ e = 1) with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first or der. the above start character data is h'3f. for the inverse convention type, set the dir and sinv bits in sdcr to 1. according to smart card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state z. in this lsi, the sinv bit inverts only data bits d0 to d7. therefore, set the o/ e bit in smr to 1 to invert the parity bit for both transmission and reception. 13.7.3 block transfer mode operation in block transfer mode is the same as that in the normal smart card interface mode, except for the following points. ? in reception, though the parity check is performed , no error signal is output even if an error is detected. however, the per bit in ssr is set to 1 and must be cleared before receiving the parity bit of the next frame. ? in transmission, a guard time of at least 1 etu is left between the end of the parity bit and the start of the next frame. ? in transmission, because retransmission is not pe rformed, the tend flag is set to 1, 11.5 etu after transmission start. ? as with the normal smart card interface, the er s flag indicates the error signal status, but since error signal transfer is not performe d, this flag is always cleared to 0. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 454 of 882 rej09b0108-0400 13.7.4 receive data sampling timing and rece ption margin in smart card interface mode an internal clock generated by the on-chip baud rate generator can only be used as a transmit/receive clock. in this mode, the sci operates on a basic clock with a frequency of 32, 64, 372, or 256 times the bit rate (fixed to 16 times in normal asynchronous mode) as determined by bits bcp 1 and bcp0. in reception, the sc i samples the falling edge of the start bit using the basic clock, and performs internal synchronization. as shown in figure 13.25, by sampling receive data at the rising edge of the 16th, 32 nd, 186th, or 128t h pulse of the basic clock, data can be latched at the middle of the bit. the reception margin is given by the following formula. m = | (0. 5 ? ) ? (l ? 0. 5 ) f ? (1 + f ) | 100% 1 2n | d ? 0. 5 | n where m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, and 256) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0, d = 0.5, and n = 372 in the above formula, the reception margin formula is as follows. m = (0.5 ? 1/2 372) 100% = 49.866% internal basic clock 372 clocks 186 clocks receive data (rxd) synchronization samplin g timin g d0 d1 data samplin g timin g 185 371 0 371 185 0 0 start bit figure 13.25 receive data sampling timing in smart card interface mode (using clock of 372 times bit rate) 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 455 of 882 rej09b0108-0400 13.7.5 initialization before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive m ode, or vice versa. 1. clear the rie, tie, teie, mpie , te, and re bits in scr to 0. 2. clear the error flags ers, per, and orer in ssr to 0. 3. set the gm, blk, o/ e , bcp1, bcp0, cks1, and cks0 bits in smr. set the pe bit to 1. 4. set the smif, dir, and sinv bits in sdcr. 5. set the value corresponding to the bit rate to brr. 6. set the cke1 and cke0 bits in scr. clear th e tie, rie, te, re, mpie, and teie bits to 0. 7. wait at least one bit interval, then set the tie and rie bits in scr. 8. make the pin function settings for the external pins (sck, txd, and rxd). 9. set the te and re bits in scr. except for self diagnosis, do not set the te bit and re bit at the same time. to switch from receive mode to transmit mode, afte r checking that the sci has finished reception, initialize the sci, and clear the re bit to 0 and set the te bit to 1. whether the sci has finished reception or not can be checked with the rdrf, per, or orer flag. to switch from transmit mode to receive mode, after checking that the sc i has finished transmissi on, initialize the sci, and clear the te bit to 0 and set the re bit to 1. whether the sci has finished transmission or not can be checked with the tend flag. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 456 of 882 rej09b0108-0400 13.7.6 serial data transmission (except for block transfer mode) as data transmission in smart card interface mode involves error signal sampling and retransmission processing, the operations are different from those in normal serial communication interface mode (except for block transfer mode). figure 13.26 illustrates the retransfer operation when the sci is in transmit mode. 1. if an error signal is sampled from the recei ving end after transmission of one frame is completed, the ers bit in ssr is set to 1. if the rie bit in scr is set at this time, an eri interrupt request is generated. the ers bit in ssr should be cleared to 0 by the time the next parity bit is sampled. 2. the tend flag in ssr is not set for a frame in which an error signal is received. data is retransferred from tdr to tsr, and retransmitted automatically. 3. if an error signal is not sent back from the receiving end, the ers bit in ssr is not set. transmission of one frame, including a retransfer, is decided to have been completed, and the tend flag in ssr is set to 1. if the tie bit in scr is set at this time, a txi interrupt request is generated. writing transmit data to tdr transmits the next data. figure 13.28 shows an example of a flowchart for transmission. a sequence of transmit operations can be perf ormed automatically by specifying the dmac or dtc to be activated with a txi interrupt source. in a transmit operation, the tdre flag is set to 1 at the same time as the tend flag in ssr is set, and a txi interrupt request will be generated if the tie bit in scr has been set to 1. if the txi request is designated beforehand as a dmac or dtc activation source, the dmac or dtc will be activated by the txi request, and tran sfer of the transmit data will be carried out. the tdre and tend flags are automatically cleared to 0 when data is transferred by the dmac or dtc. in the event of an error, the sc i retransmits the same data automatically. during this period, the tend flag remains cleared to 0 and the dmac or dtc is not activated. therefore, the sci and dmac or dtc will automatically transmit the specified number of bytes in the event of an error, including retransmission. however, the ers flag is not cleared automa tically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri interrupt request will be generated in the event of an error, and the ers flag will be cleared. when performing transfer using the dmac or dtc, it is essential to set and enable the dmac or dtc before carrying out sci setting. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 457 of 882 rej09b0108-0400 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame tdre tend fer/ers transfer to tsr from tdr transfer to tsr from tdr transfer to tsr from tdr figure 13.26 retransfer operation in sci transmit mode the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag generation timing is shown in figure 13.27. ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5etu txi (tend interrupt) 11.0etu de guard time when gm = 0 when gm = 1 start bit data bits parity bit error si g nal [le g end] ds: d0 to d7: dp: de: figure 13.27 tend flag generation timing in transmit operation 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 458 of 882 rej09b0108-0400 initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre fla g in ssr to 0 error processin g error processin g tend = 1? all data transmitted ? tend = 1? ers = 0? ers = 0? figure 13.28 example of transmit processing flow in smart card interface mode, data reception sh ould be performed in block transfer mode. for details, refer to section 13.4, operation in asynchronous mode. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 459 of 882 rej09b0108-0400 13.7.7 clock output control when the gm bit in smr is set to 1, the clock output level can be fixed with the cke1 and cke0 bits in scr. at this time, the minimum clock pulse width can be specified. figure 13.29 shows the timing for fixing the clock output level. in this example, the gm bit is set to 1, the cke1 bit is cleared to 0, and the cke0 bit is controlled. specified pulse width sck cke0 specified pulse width figure 13.29 timing for fixing clock output level 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 460 of 882 rej09b0108-0400 13.8 interrupt sources 13.8.1 interrupts in normal seri al communication interface mode table 13.12 shows the interrupt sources in no rmal serial communication interface mode. a different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in scr. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interr upt request is generated. a txi interrupt request can activate the dmac or dtc to perform data transfer. the tdre flag is cleared to 0 au tomatically when data transfer is performed by the dmac or dtc. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt request can activate the dmac or dtc to perform data transfer. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dmac or dtc. a tei interrupt is generated when the tend flag is set to 1 while the teie bit is set to 1. if a tei interrupt and a txi interrupt are generated simultaneously, the txi interrupt has priority for acceptance. however, note that if the tdre an d tend flags are cleared simultaneously by the txi interrupt routine, the sci cannot bran ch to the tei interrupt routine later. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 461 of 882 rej09b0108-0400 table 13.12 interrupt sources in s erial communication interface mode channel name interrupt source interrupt flag dmac or dtc activation eri_0 receive error orer, fer, per not possible rxi_0 receive data full rdrf possible txi_0 transmit data empty tdre possible 0 tei_0 transmission end tend not possible eri_1 receive error orer, fer, per not possible rxi_1 receive data full rdrf possible txi_1 transmit data empty tdre possible 1 tei_1 transmission end tend not possible eri_2 receive error orer, fer, per not possible rxi_2 receive data full rdrf possible txi_2 transmit data empty tdre possible 2 tei_2 transmission end tend not possible 3 eri_3 receive error orer, fer, per not possible rxi_3 receive data full rdrf possible txi_3 transmit data empty tdre possible tei_3 transmission end tend not possible 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 462 of 882 rej09b0108-0400 13.8.2 interrupts in smar t card interface mode table 13.13 shows the interrupt sources in smart card interface mo de. the transmit end interrupt (tei) request cannot be used in this mode. note: in block transfer mode, refer to section 13 .8.1, interrupts in norm al serial communication interface mode. table 13.13 interrupt sources in smart card interface mode channel name interrupt source inte rrupt flag dmac or dtc activation eri_0 receive error, error signal detection orer, per, ers not possible rxi_0 receive data full rdrf possible 0 txi_0 transmit data empty tend possible eri_1 receive error, error signal detection orer, per, ers not possible rxi_1 receive data full rdrf possible 1 txi_1 transmit data empty tend possible eri_2 receive error, error signal detection orer, per, ers not possible rxi_2 receive data full rdrf possible 2 txi_2 transmit data empty tend possible 3 eri_3 receive error, error signal detection orer, per, ers not possible rxi_3 receive data full rdrf possible txi_3 transmit data empty tend possible 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 463 of 882 rej09b0108-0400 13.9 usage notes 13.9.1 tdr write and tdre flag the tdre bit in the serial status register (ssr) is a status flag indicating transferring of transmit data from tdr into tsr. the sci sets the tdre bit to 1 when it transfers data from tdr to tsr. data can be written to tdr regardless of the tdre bit status. if new data is written in tdr when tdre is 0, however, the old data stored in tdr will be lost because the data has not yet been transferred to tsr. before writing transmit data to tdr, be sure to check that the tdre bit is set to 1. 13.9.2 module standby mode setting sci operation can be disabled or enabled using the module standby control register. the initial setting is for sci operation to be halted. regist er access is enabled by clearing module standby mode. for details, refer to section 24, power-down modes. 13.9.3 break detection and proces sing (asynchronous mode only) when framing error detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the per flag may also be set. note that, since the sc i continues the receive op eration after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. 13.9.4 sending break signal (asynchronous mode only) the txd pin becomes of the i/o port general i/o pin with the i/o direction and level determined by the port data register (dr) and the port i/o register (ior) of the pin function controller (pfc). these conditions allow break signals to be sent. the dr value is substituted for the marking status until the pfc is set. consequently, the output port is set to initially output a 1. to send a break in serial transmission, first clear the dr to 0, then establish the txd pin as an output port using the pfc. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 464 of 882 rej09b0108-0400 when the te bit is cleared to 0, the transmission section is initialized regardless of the present transmission status. 13.9.5 receive error flags and transmit op erations (clocked synchronous mode only) transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to cl ear the receive error flag s to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. 13.9.6 notes on dmac and dtc use 1. when using an external clock source for the se rial clock, update tdr with the dmac or the dtc, and then after the elapse of five peripheral clocks (p ) or more, input a transmit clock. if a transmit clock is input in the first four p clocks after tdr is wr itten, an error may occur (figure 13.30). 2. before reading the receive data register (rdr ) with the dmac or the dtc, select the receive- data-full (rxi) interrupt of the sci as a start-up source. d0 sck tdre d1 d2 d3 d4 d5 d6 d7 t note: durin g external clock operation, an error may occur if t is 4 p clocks or less. figure 13.30 example of clocked synchronous transmission with dmac/dtc 13.9.7 notes on clocked synchronous external clock mode 1. set te = re = 1 only when external clock sck is 1. 2. do not set te = re = 1 until at least four p clocks after external clock sck has changed from 0 to 1. 3. when receiving, rdrf is 1 when re is cleared to 0 after 2.5 to 3.5 p clocks from the rising edge of the rxd d7 bit sck input, but copying to rdr is not possible. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 465 of 882 rej09b0108-0400 13.9.8 note on clocked synchronous internal clock mode when receiving, rdrf is 1 when re is cleared to 0 after 1.5 p clocks from the rising edge of the rxd d7 bit sck output, but copying to rdr is not possible. 13. serial communication interface (sci) rev.4.00 mar. 27, 2008 page 466 of 882 rej09b0108-0400 14. i 2 c bus interface (iic) option ifiic60a_010020030800 rev.4.00 mar. 27, 2008 page 467 of 882 rej09b0108-0400 section 14 i 2 c bus interface (iic) option the i 2 c bus interface is an optional feature. when usi ng this optional feature, pay attention to the following point: ? a ?w? is added to the product-type name of a mask-rom product which includes an optional feature. this lsi incorporates a single-channel i 2 c bus interface. the i 2 c bus interface conforms to the philips i 2 c bus (inter-ic bus) interface system and pr ovides a subset of the functions. note, however, that the configuration of the registers that control the i 2 c bus differs on some points from that of phillips?. data transfer is carried out by the data lin e (sda0) and clock line (scl0). this makes the interface efficient in terms of the use of area for connectors and printed circuits. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 468 of 882 rej09b0108-0400 14.1 features ? selection of addressing or non-addressing format i 2 c bus format: addressing format with an ac knowledge bit, master and slave operation synchronous serial format: non-addressing format without an acknowledge bit, and with master operation only ? this i 2 c bus format complies with the i 2 c bus interface advocat ed by phillips. ? in the i 2 c bus format, two slave addresses ar e specifiable for a single device. ? automatic creation of start and stop conditions in master mode of the i 2 c bus format ? selectable acknowledge output level during reception in the i 2 c bus format ? automatic loading of the acknowledge bit is available during transmission in the i 2 c bus format. ? a wait function is available in the i 2 c bus format in the master mode. after all data other than the acknowledge bit has been transferred, the system can be placed in the wait state by setting scl low. the wait state can be cancelled by clearing the interrupt flag to 0. ? a wait function is available in the i 2 c bus format. after all data other than the acknowledge bit has been transferred, a request to enter the wait state can be issued by setting sc l low. the request to enter the wait state is cleared when the next transfer becomes possible. ? interrupt sources data transfer end (including when a transition to transmit mode is made in the i 2 c bus format, when data in icdr is transferred, or during a wait state) address match: when any slave address matches or the general call address is received in slave receive mode of the i 2 c bus format (including address reception after loss in master contention) loss of arbitration start condition detection (in master mode) stop condition detection (in slave mode) ? sixteen variants of the internal cloc k are selectable in the master mode. ? direct bus drive (scl/sda pin) pins scl0 and sda0 function as nmos open-drain output. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 469 of 882 rej09b0108-0400 figure 14.1 is a block diagram of the i 2 c bus interface. figure 14.2 shows an example of the connection of i 2 c bus interfaces. since the i/o pins are driven only by the nmos transistor, they operate in the same way as pins driven by an open-drain nmos transistor. the voltage that can be applied to the i/o pins depends on the supply voltage of the lsi. p scl ps noise canceller bus state detection circuit arbitration detection circuit output data control cricuit iccr clock control scrx icmr icsr icdrs address comparater sar, sarx sda noise canceller interrupt g eneration circuit interrupt request internal data bus [le g end] iccr: icmr: icsr: icdr: scrx: sar: sarx: ps: i 2 c control re g ister i 2 c mode re g ister i 2 c status re g ister i 2 c data re g ister serial control re g ister x slave address re g ister slave address re g ister x prescaler icdrr icdrt figure 14.1 a block diagram of the i 2 c bus interface 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 470 of 882 rej09b0108-0400 v cc vcc scl in scl out scl sda in sda out (master) this lsi sda scl sda scl in scl out scl sda in sda out (slave 1) sda scl in scl out scl sda in sda out (slave 2) sda figure 14.2 example of the connection of i 2 c bus interfaces (this lsi is the master device) 14.2 input/output pins the i/o pins of the i 2 c bus interface are listed in table 14.1. table 14.1 pin configuration channel pin name * i/o function 0 scl0 i/o serial clock i/o pin sda0 i/o serial data i/o pin note: * in this manual, these pin names are ab breviated to scl and sda, respectively. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 471 of 882 rej09b0108-0400 14.3 description of registers the i 2 c bus interface includes the following registers for each channel. for the addresses of these registers and the states of the registers in each st ate of processing, refer to section 25, list of registers. registers icdr and sarx and regist ers icmr and sar are al located to the same addresses, and accessible registers differ depending on the state of ice bit in iccr. when the ice bit is 0, sar and sarx can be accessed, and wh en the ice bit is 1, icmr and icdr can be accessed. ? i 2 c bus control register (iccr) ? i 2 c bus status register (icsr) ? i 2 c bus data register (icdr) ? i 2 c bus mode register (icmr) ? slave-address register (sar) ? second slave-address register (sarx) ? serial control register x (scrx) 14.3.1 i 2 c bus data register (icdr) icdr is an 8-bit readable/writable register that holds the data for transmission during transmission, and holds the received data during r eception. internally, icdr consists of a shift register (icdrs), receive buffer (icdrr), and transmission buffer (icdrt). data is automatically transferred between these th ree registers according to the bus state; this affects the states of flags, su ch as the icdrf flag in scrx and the internal flag icdre. in master transmit mode of the i 2 c bus format, writing transmit data to icdr should be performed after start condition is detected. when the star t condition is detected, previous write data is ignored. in slave transmit mode, writing should be performed after the slave addresses match and the trs bit is automatically changed to 1. when i 2 c is in transmit mode (trs = 1) and the next transmit data is in icdrt (the icdre flag is 0), data is transferred automatically from ic drt to icdrs after successful transmission of one frame of data using icdrs. when the icdre fl ag is 1 and the next transmit data writing is waited, data is transferred auto matically from icdrt to icdrs by writing to icdr. in receive mode (trs = 0), no data is transferred from icdrt to icdrs. note that data should not be written to icdr in receive mode. reading receive data from icdr is performed afte r data is transferred from icdrs to icdrr. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 472 of 882 rej09b0108-0400 when i 2 c is in receive mode and no previous data re mains in icdrr (the icdrf flag is 0), data is transferred automatically from icdrs to icd rr, following reception of one frame of data using icdrs. when additional data is received wh ile the icdrf flag is 1, data is transferred automatically from icdrs to icdrr by reading from icdr. in transmit mode, no data is transferred from icdrs to icdrr. always set i 2 c to receive mode before reading from icdr. when, excluding the acknowledge bit, there are fe wer than 8 bits in one frame, the alignment of the data for transmission and of received data varies according to the setting of the mls bit in icmr. data for transmission shoul d span the selected number of bits from the msb when mls = 0. when mls is 1, the data shou ld span the selected number of bits from th e lsb. received data is read from the lsb when mls is 0 and from the msb when mls is 1. icdr is only accessible when the ice bit in iccr is set to 1. the icdr is undefined at reset. 14.3.2 slave-address register (sar) sar sets the transfer format and stores th e slave address. in slave mode of the i 2 c bus format, if the fs bit is set to 0 and the upper seven bits of sar match the upper seven bits of the first frame received after a start condition, this module opera tes as the slave device sp ecified by the master device. sar can be accessed only when the ice bit in iccr is set to 0. bit bit name initial value r/w description 7 6 5 4 3 2 1 sva6 sva5 sva4 sva3 sva2 sva1 sva0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w slave address 6 to 0 set slave address. 0 fs 0 r/w format select in conjunction with the fsx bit in sarx, this bit selects the transfer format. see table 14.2. to identify the general call address, this bit should always be set to 0. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 473 of 882 rej09b0108-0400 14.3.3 second slave-address register (sarx) sarx sets the transfer format and stores the second slave addr ess. in slave mode of the i 2 c bus format, if the fs bit is set to 0 and the upper seven bits of sarx match the upper seven bits of the first frame received after a start condition, this module operates as the slave device specified by the master device. sarx can be accessed only when the ice bit in iccr is set to 0. bit bit name initial value r/w description 7 6 5 4 3 2 1 svax6 svax5 svax4 svax3 svax2 svax1 svax0 0 0 0 0 0 0 0 r/w r/w r/w r/w r/w r/w r/w second slave address 6 to 0 set second slave address. 0 fsx 1 r/w format select x in conjunction with the fs bit in sar, this bit selects the transfer format. see table 14.2. table 14.2 transfer format sar sarx fs fsx operating mode 0 0 i 2 c bus format ? enables the slave addresses in sar and sarx ? enables the general call address 1 i 2 c bus format ? enables the slave address in sar ? disables the slave address in sarx ? enables the general call address 1 0 i 2 c bus format ? disables the slave address in sar ? enables the slave address in sarx ? disables the general call address 1 synchronous serial format ? disables the slave addresses in sar and sarx ? disables the general call address 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 474 of 882 rej09b0108-0400 ? i 2 c bus format: addressing format with an acknowledge bit ? synchronous serial format: non-addressing format without an acknowledge bit, and with master operation only 14.3.4 i 2 c bus mode register (icmr) icmr sets the transfer format and transfer rate. icmr is only accessible when the ice bit in iccr is set to 1. bit bit name initial value r/w description 7 mls 0 r/w msb first/lsb first select 0: msb first 1: lsb first when this module is used in the i 2 c bus format, this bit should be set to 0. 6 wait 0 r/w wait insertion this bit is enabled only in master mode of the i 2 c bus format. 0: a wait state is not inserted, and data and the acknowledge bit are transferred consecutively. 1: after the clock for the final bit of the data (8th cycle) become low, the iric flag in iccr is set to 1, and a wait state is entered (wit h scl at the low level). clearing the iric flag in iccr to 0 cancels the wait state. the acknowledge bit is then transferred. for details, refer to secti on 14.4.7, timing for setting iric and the control of scl. 5 4 3 cks2 cks1 cks0 0 0 0 r/w r/w r/w transfer clock select 2 to 0 the cks2 to cks0 bits, together with the iicx0 bit in scrx, select the frequency of the transfer clock. this is used in the master m ode. see table 14.3. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 475 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 1 0 bc2 bc1 bc0 0 0 0 r/w r/w r/w bit counter these bits specify the number of bits to be transferred in the next transfer. set the bc2 to bc0 bits in the intervals between the transfer of frames. set the bc2 to bc0 bits to other than 000 when scl is low. the bit counter is initializ ed to 000 on detection of the start condition. in addition, this counter returns to 000 on completion of the transfer of all data. i2c bus format synchronous serial format 000: 9 bits 000: 8 bits 001: 2 bits 001: 1 bit 010: 3 bits 010: 2 bits 011: 4 bits 011: 3 bits 100: 5 bits 100: 4 bits 101: 6 bits 101: 5 bits 110: 7 bits 110: 6 bits 111: 8 bits 111: 7 bits 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 476 of 882 rej09b0108-0400 table 14.3 setting of the transfer rate scrx bit5 bit5 bit4 bit3 transfer rate iicx cks2 cks1 cks0 clock p = 10mhz p = 16mhz p = 20mhz p = 25mhz p = 33mhz p = 40mhz 0 0 0 0 p /28 357khz 571khz * 714khz * 893khz * 1.18mhz * 1.43mhz * 1 p /40 250khz 400khz 500khz * 625khz * 825khz * 1.00mhz * 1 0 p /48 208khz 333khz 417khz * 521khz * 688khz * 833khz * 1 p /64 156khz 250khz 313khz 391khz 516khz * 625khz * 1 0 0 p /80 125khz 200khz 250khz 313khz 413khz * 500khz * 1 p /100 100khz 160khz 200khz 250khz 330khz 400khz 1 0 p /112 89.3khz 143khz 179khz 223khz 295khz 357khz 1 p /128 78.1khz 125khz 156khz 195khz 258khz 313khz 1 0 0 0 p /56 179khz 286khz 357khz 446khz * 589khz * 714khz 1 p /80 125khz 200khz 250khz 313khz 413khz * 500khz * 1 0 p /96 104khz 167khz 208khz 260khz 344khz 417khz * 1 p /128 78.1khz 125khz 156khz 195khz 258khz 313khz 1 0 0 p /160 62.5khz 100khz 125khz 156khz 206khz 250khz 1 p /200 50.0khz 80.0khz 100khz 125khz 165khz 200khz 1 0 p /224 44.6khz 71.4khz 89.3k hz 112khz 147khz 177khz 1 p /256 39.1khz 62.5khz 78.1k hz 97.7khz 129khz 156khz note: * out of the i 2 c bus interface specification (normal mode: maximum100 khz, high speed mode: maximum 400 khz) due to factors such as load conditions, it may not be possible to obtain the designated transfer rate when the value of iicx is 0 and the peripheral clock frequency exceeds 16 mhz. set iicx to 1 when p is greater than 16 mhz. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 477 of 882 rej09b0108-0400 14.3.5 i 2 c bus control register (iccr) iccr controls i 2 c bus interface and confirms th e state of interrupt flag. bit bit name initial value r/w description 7 ice 0 r/w i 2 c bus interface enable 0: this module is not operating. the internal state of the i 2 c module is cleared. access to sar and sarx is enabled. 1: this module is in its transfer-enabled state 6 ieic 0 r/w i 2 c bus interface interrupt enable 0: disables the interrupt from the i 2 c bus interface to the cpu 1: enables the interrupt from the i 2 c bus interface to the cpu 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 478 of 882 rej09b0108-0400 bit bit name initial value r/w description 5 4 mst trs 0 0 r/w r/w master/slave select transmission/reception select 00: slave receive mode 01: slave transmit mode 10: master receive mode 11: master transmit mode both mst and trs bits will be cleared by hardware when they lose in a bus contenti on in master mode of the i 2 c bus format. the mode changes to slave receive mode. when the i 2 c bus format is used in the slave-receive mode, transmission or reception is automatically selected by the hardware, according to the setting of the r/ w bit of the first frame after the start condition has been satisfied. even if an attempt is made to change the trs bit during the transfer of data, the change is suspended until transmission of data has been completed; the bit is then changed. [mst clearing conditions] 1. writing of 0 to this bit by software 2. lose in a bus contention in master mode of the i 2 c bus format [mst setting conditions] 1. writing of 1 to this bit by software (mst clearing condition 1) 2. writing of 1 to this bit after reading mst = 0 (mst clearing condition 2) [trs clearing conditions] 1. writing of 0 to this bit by software (except trs setting condition 3) 2. writing of 0 to this bit after trs = 1 is read (trs setting condition 3) 3. lose in a bus contention in master mode of the i 2 c bus format [trs setting conditions] 1. writing of 1 to this bit by software (except trs clearing condition 3) 2. writing of 1 to this bit after reading trs = 0 (trs clearing condition 3) 3. when 1 is received as the r/ w bit of the first frame address matched in the i 2 c bus format in slave mode. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 479 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 acke 0 r/w enables/disables acknowledge bit 0: the value of the acknowledge bit is ignored to allow the continuous transfer of data. the received value of the acknowledge bits that are received do not affect the ackb bit; the value in the ackb bit in icsr remains at 0. 1: when the value of the acknowledge bits received in the i 2 c bus format is 1, transmission is suspended. the acknowledge bit is used in two different ways, depending on the situation. one case is that the acknowledge bit is used as a kind of flag to indicate whether or not processing fo r the reception of data has been completed. the other case is that acknowledge bit is fixed to 1. 2 0 bbsy scp 0 1 r/w w bus busy start/stop condition issuance disable master mode: ? write 0 to bbsy and scp: issuing stop condition ? write 1 to bbsy and 0 to scp: issuing start condition and re-transmitting start condition slave mode: ? writing to the bbsy flag is disabled [bbsy setting condition] ? when sda changes from high to low while scl is high, the system regards the start condition as having been set. [bbsy clearing condition] ? when sda changes from low to high while sda is high, the system regards the stop condition as having been set. the start and stop conditions are issued by using the mov instruction. the i 2 c bus interface must be set to master transmit mode before the start condition is issued. before writing 1 to bbsy and 0 to scp, set mst and trs to 1. the bbsy flag may be read to confirm whether or not the i 2 c bus (scl, sda) has been released. the scp bit is always read as 1. data is not stored even if 0 is written to the scp bit. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 480 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 iric 0 r/(w )* i 2 c bus interface interrupt request flag the iric flag indicates that the i 2 c bus interface has generated an interrupt request for the cpu. the timing with which the iric flag is set changes according to the combination of the values of the fs bit in sar, the fsx bit in sarx and the wait bit in icmr. refer to section 14.4. 7, timing for setting iric and the control of scl. in addition, the condition on which the iric flag is set changes according to the setting of the acke bit in iccr. [setting conditions] ? i 2 c bus format in master mode when the start condition is detected from the bus line state after the start condition has been set. (i.e., when the icdre flag is set to 1 for transmission of the first frame). when wait = 1, a wait is inserted between the data bits and the acknowledge bit. (i.e., at the falling edge of the 8th transmit/receive clock) when the transfer of data has been completed. (i.e., at the rising ed ge of the 9th cycle of transmit/receive clock with no wait inserted) when a slave address is received after bus conflict is lost. (i.e., first frame following start condition) when the acke bit is 1, and 1 is received as an acknowledge bit. (i.e., when the ackb bit is set to 1). when the al flag is set to 1 because of a bus conflict. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 481 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 iric 0 r/(w )* ? i 2 c bus format in the slave mode when a slave address (sva or svax) matches (i.e., when the aas or aasx flag is set to 1), and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection (i.e., at the risi ng edge of the 9th cycle of transmission or receive clock) when the general call address has been detected (i.e., when 0 is received for r/ w and the adz flag is set to 1) and at the end of data reception up to the subsequent retransmission start condition or stop condition detection (i.e., at the rising edge of the 9th cycle of receive clock) when the acke bit is 1, and 1 is received as an acknowledge bit (i.e., when the ackb bit is set to 1) when the stop condition is detected while the stopim bit is 0 (i.e., when the stop or the estp flag is set to 1) ? synchronous serial format when the transfer of data has been completed (i.e., at the rising edge of the 8th transmit/receive clock) when a start condition is detected with serial format ? when a condition occurs in which the icdre or icdrf flag is set to 1 in any operating mode. when a start condition is detected in transmit mode (i.e., when a start condition is detected and the icdre flag is set to 1 in transmit mode) when transmitting the data in the icdr register buffer (i.e., when data is transferred from icdrt to icddrs in transmit mode and the icdre flag is set to 1, or data is transferred from icdrs to icdrr in receive mode and the icdrf flag is set to 1.) [clearing conditions] ? when 0 is written in iric after reading iric = 1 ? when icdr is read or written to by dtc (this may not be a clearing condition. for details, see the following operation description on dtc.) note: * only 0 can be written to clear the flag. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 482 of 882 rej09b0108-0400 when the dtc is used, the iric flag is cleared automatically and tran sfer can be performed continuously without cpu intervention. when the interface is in the i 2 c bus format and an interrupt is generated so that iric becomes 1, other flags must be checked to locate the cause of the iric bit becoming 1. each possible cause has a corresponding flag. precautions must be taken when the data transfer has been completed. when the icdre or icdrf flag is set, the irtr flag may be set, but in some cases it will not be. in the i 2 c bus format in the slave mode, the irtr fl ag, which is the dtc-activation request flag, is not set during the period between the completi on of data transfer afte r a slave-address (sva) match or a general call address match and the detect ion of the stop condition or transmission of the next start condition. even when the iric or irtr flag has been set, the icdre or icdrf flag may not be set in some cases. when a continuous transfer is performed using the dtc, the iric or irtr flag is not cleared when the specified number of transfers is completed. on the other hand, since the specified number of read/write operations has been completed, the icdre or the icdrf flag will already have been cleared. the relationship between the flags and the various states of transfer is shown in table 14.4 and table 14.5. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 483 of 882 rej09b0108-0400 table 14.4 the relationship between fl ags and transfer states (master mode) mst trs bbsy estp stop irtr aasx al aas adz ackb icdrf icdre state 1 1 0 0 0 0 0 0 0 0 0 ? 0 idle state (flag clearing required) 1 1 1 0 0 1 0 0 0 0 0 ? 1 start condition detected 1 ? 1 0 0 ? 0 0 0 0 ? ? ? wait state 1 1 1 0 0 ? 0 0 0 0 1 ? ? transmission end (acke = 1 and ackb = 1) 1 1 1 0 0 1 0 0 0 0 0 ? 1 transmission end with icdre = 0 1 1 1 0 0 ? 0 0 0 0 0 ? 0 icdr write with the above state 1 1 1 0 0 ? 0 0 0 0 0 ? 1 transmission end with icdre = 1 1 1 1 0 0 ? 0 0 0 0 0 ? 0 icdr write with the above state or after start condition detected 1 1 1 0 0 1 0 0 0 0 0 ? 1 automatic data transfer from icdrt to icdrs with the above state 1 0 1 0 0 1 0 0 0 0 ? 1 ? reception end with icdrf = 0 1 0 1 0 0 ? 0 0 0 0 ? 0 ? icdr read with the above state 1 0 1 0 0 ? 0 0 0 0 ? 1 ? reception end with icdrf = 1 1 0 1 0 0 ? 0 0 0 0 ? 0 ? icdr read with the above state 1 0 1 0 0 1 0 0 0 0 ? 1 ? automatic data transfer from icdrs to icdrr with the above state 0 0 1 0 0 ? 0 1 0 0 ? ? ? arbitration lost 1 ? 0 0 0 ? 0 0 0 0 ? ? 0 stop condition detected [legend] 0: 0-state retained 1: 1-state retained ? : previous state retained 0 : cleared to 0 1 : set to 1 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 484 of 882 rej09b0108-0400 table 14.5 the relationship between flags and transfer states (slave mode) mst trs bbsy estp stop irtr aasx al aas adz ackb icdrf icdre state 0 0 0 0 0 0 0 0 0 0 0 ? 0 idle state (flag clearing required) 0 0 1 0 0 0 0 0 0 0 0 ? 1 start condition detected 0 1 /0 ( * 1 ) 1 0 0 0 0 ? 1 0 0 1 1 sar match in the first frame (sarx sar) 0 0 1 0 0 0 0 ? 1 1 0 1 1 general call address match in the first frame (sarx h'00) 0 1 /0 ( * 1 ) 1 0 0 1 1 ? 0 0 0 1 1 sarx match in the first frame (sar sarx) 0 1 1 0 0 ? ? ? ? 0 1 ? ? transmission end (acke = 1 and ackb = 1) 0 1 1 0 0 1 /0 ( * 2 ) ? ? ? 0 0 ? 1 transmission end with icdre = 0 0 1 1 0 0 ? ? 0 0 0 0 ? 0 icdr write with the above state 0 1 1 0 0 ? ? ? ? 0 0 ? 1 transmission end with icdre = 1 0 1 1 0 0 ? ? 0 0 0 0 ? 0 icdr write with the above state 0 1 1 0 0 1 /0 ( * 2 ) ? 0 0 0 0 ? 1 automatic data transfer from icdrt to icdrs in the above state 0 0 1 0 0 1 /0 ( * 2 ) ? ? ? ? ? 1 ? reception end with icdrf = 0 0 0 1 0 0 ? ? 0 0 0 ? 0 ? icdr read with the above state 0 0 1 0 0 ? ? ? ? ? ? 1 ? reception end with icdrf = 1 0 0 1 0 0 ? ? 0 0 0 ? 0 ? icdr read with the above state 0 0 1 0 0 1 /0 ( * 2 ) ? 0 0 0 ? 1 ? automatic data transfer from icdrs to icdrr with the above state 0 ? 0 1 /0 ( * 3 ) 0/1 ( * 3 ) ? ? ? ? ? ? ? 0 stop condition detected 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 485 of 882 rej09b0108-0400 [legend] 0: 0-state retained 1: 1-state retained ? : previous state retained 0: cleared to 0 1: set to 1 notes: 1. set to 1 when 1 is received as a r/ w bit following an address. 2. set to 1 when the aasx bit is set to 1. 3. stop is 0 when estp = 1, or estp is 0 when stop = 1. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 486 of 882 rej09b0108-0400 14.3.6 i 2 c bus status register (icsr) icsr includes flags that indicate bus stat es. see also table 14 .4 and table 14.5. bit bit name initial value r/w description 7 estp 0 r/(w) * erroneous stop condition detection flag this bit is enabled in the i 2 c bus format in the slave mode. [setting condition] ? detection of the stop condit ion during the transfer of one frame [clearing conditions] ? writing of 0 to this bit after reading estp = 1 ? clearing of the iric flag to 0 6 stop 0 r/(w) * normal stop condition detection flag this bit is enabled in the i 2 c bus format in the slave mode. [setting condition] ? detection of the stop conditio n after the transfer of one frame [clearing conditions] ? writing of 0 to this bit after reading stop = 1 ? clearing of the iric flag to 0 5 irtr 0 r/(w) * i 2 c bus interface continuous transfer interrupt request flag the irtr flag indicates that the i 2 c bus interface has generated an interrupt for the cpu at the end of transmission and reception one frame of data. the iric flag is set to 1 at the same time as the irtr flag is set to 1. [setting conditions] ? setting of the icdre or icdrf flag to 1 while aasx is 1 in the i 2 c bus interface in the slave mode. ? setting of the icdre or icdrf flag to 1, when in master mode in i2c bus interface or synchronous serial format [clearing conditions] ? writing of 0 to this bi t after reading irtr = 1 ? clearing of the iric flag to 0 with ice = 0 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 487 of 882 rej09b0108-0400 bit bit name initial value r/w description 4 aasx 0 r/(w) * second slave address detection flag in the i 2 c bus format in the slave mode, this bit indicates that the first frame after the start condition matches bits svax6 to svax0 in sarx. [setting condition] ? detection of the second slave address in the slave receive mode while fsx = 0. [clearing conditions] ? writing of 0 to this bit after reading aasx = 1 ? detection of the start condition. ? entering master mode 3 al 0 r/(w) * arbitration lost flag the al flag indicates that the device, in master mode, has failed to acquire bus-master status. [setting conditions] ? when the interface is in ma ster transmit mode, the sda value it is generating internally and the value on the sda pin do not match on the rising edge of scl. ? when the start condition instru ction has been executed in master transmit mode, then the sda is driven to low by another device before drives the pin to low. [clearing conditions] ? writing of data to icdr (during transmission) or reading of data from icdr (during reception). ? writing a 0 to this bit after reading it as 1 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 488 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 aas 0 r/(w) * slave address detection flag when the first frame after the st art condition matches the sva6 to sva0 bits of sar or when the general-call address (h'00) is detected in the i 2 c bus format in the slave receive mode. [setting condition] ? detection of the slave address or general call address (one frame, including the r/ w bit, is h'00) while in the slave- receive mode and fs = 0. [clearing conditions] ? writing of data to icdr (during transmission) or reading of data from icdr (during reception) ? writing of 0 to this bit after reading it as 1 ? entering the master mode 1 adz 0 r/(w) * general call address detection flag in the i 2 c bus format in the slave-reception mode, the general-call address (h'00) is detected in the first frame after the start condition. [setting condition] ? detection of the general call address (one frame, including r/ w bit, is h'00) in the slave-receive mode (fsx = 0 or fs = 0). [clearing conditions] ? writing of data to icdr (dur ing transmission) or reading of data from icdr (during reception). ? writing 0 to this bit after reading it as 1 ? entering the master mode when the general call address is detected while fs = 1 and fsx = 0, the adz flag is set to 1 but the general call address is not identified (the aas flag is not set to 1). 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 489 of 882 rej09b0108-0400 bit bit name initial value r/w description 0 ackb 0 r/w acknowledge this bit stores the acknowledgements. transmit mode: [setting condition] ? reception of 1 as an acknowledge bit when acke is 1 in transmit mode. [clearing conditions] ? reception of 0 as an acknowledge bit when acke is 1 in transmit mode. ? writing 0 to the acke bit receive mode: 0: after reception of data, 0 is output as acknowledge data 1: after reception of data, 1 is output as acknowledge data when this bit is read, the value that was loaded here (the value returned from the receiving device) is read during transmission (trs = 1). during receive operations (trs = 0), the value that was set is read. when this bit is written, acknowledge data that is returned after receiving is rewritten re gardless of the trs value. if the icsr register flag is written using bit-manipulation instructions, the acknowledge data should be set again since the acknowledge data se tting is rewritten by the reading value of ackb bit. write the acke bit to 0 to clear the ackb flag to 0, before transmission is ended and a stop condition is issued in master mode, or before transmission is ended and sda is released to issue a stop condition by a master device. note: * only 0 can be written to clear the flag. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 490 of 882 rej09b0108-0400 14.3.7 serial control register x (scrx) scrx enables or disables i 2 c bus interface interrupts and conf irms the state of reception and transmission. bit bit name initial value r/w description 7, 6 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 5 iicx 0 r/w i 2 c transfer rate select along with bits cks2 to cks0 in the i 2 c bus mode register (icmr), this bit selects the transfer rate in the master mode. for details on setting the transfer rate, see table 14.3. 4 iice 0 r/w i 2 c master enable this bit controls access by the cpu to the i 2 c bus interface registers (iccr, icsr, icdr/sarx, and icmr/sar) of the i 2 c bus interface. 0: disables cpu access to the registers of the i 2 c bus interface. 1: enables cpu access to the registers of the i 2 c bus interface. 3 hnds 0 r/w hand-shake receive select this bit enables/disables continuous reception in receive mode. when the hnds bit is cleared to 0, receive operation is performed continuously after data has been received successfully while icdrf flag is 0. when the hnds bit is set to 1, scl is fixed to the low level thus disabling the next data to be transferred. the bus line is released and next frame receive operation is enabled by reading the receive data in icdr. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 491 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 icdrf0 0 r receive data read request flag indicates the icdr (icdrr) state in receive mode. 0: indicates that the data has already been read from icdr (icdrr) or icdr is initialized. 1: indicates that data has been received successfully and transferred from icdrs to icdrr, and the data is not read yet. [setting condition] ? when data is received successfully and transferred from icdrs to icdrr. a. when data is received successfully while icdrf = 0 (at the rising edge of the 9th cycle of the clock). b. when icdr is read in receive mode after data was received while icdrf = 1. [clearing conditions] ? when icdr (icdrr) is read. ? when 0 is written to the ice bit. due to the condition b above, icdrf is temporarily cleared to 0 when icdr (icdrr) is read; however, since data is transferred from icdrs to icdrr immediately, icdrf is set to 1 again. note that icdr cannot be read successfully in transmit mode (trs = 1) because data is not transferred from icdrs to icdrr. read data from icdr in receive mode (trs = 0) to read data in icdr. 0 stopim 0 r/w stop condition detected interrupt mask this bit enables/disables the issuing of stop-condition- detected interrupt requests in the i 2 c bus format in the slave mode. 0: this setting enables the iric flag setting and the stop-condition-detected interrupt requests (stop = 1 or estp = 1) in the i 2 c bus format in slave mode. 1: this setting disables the iric flag setting or the stop-condition-detected inte rrupt requests in the i 2 c bus format in slave mode. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 492 of 882 rej09b0108-0400 14.3.8 icdre flag (internal flag) the icdre flag is set and cleared under the conditions as shown below. since the icdre flag is an internal flag, it cannot be accessed. bit name initial value description icdre 0 transmit data write request flag this flag is an internal flag that indicates the icdr (icdrt) state in transmission mode. 0: indicates that the data to be transmitted has been already written to icdr (icdrt) or icdr is initialized. 1: indicates that data has been transferred from icdrt to icdrs and is being transmitted, or the start condition has been detected or transmission has been completed, thus allowing the next data to be written to. [setting conditions] ? when the start condition is detect ed from the bus line state in i 2 c bus format or serial format. ? when data is transferred from icdrt to icdrs. a. when data transmission is completed while icdre =0 (at the rising edge of the 9th cycle of the clock). b. when icdr is written to in transmit mode after data transmission is completed while icdre = 1. [clearing conditions] ? when transmit data is written to icdr (icdrt). ? when the stop condition is detected in i 2 c bus format or serial format. ? when 0 is written to the ice bit. note that if the acke bit is set to 1 in i 2 c bus format thus enabling acknowledge bit decision, icdre is not set when data transmission is completed while the acknowledge bit is 1. due to the set condition b above, icdre is temporarily cleared to 0 when data is written to icdr (i cdrt); however, since data is transferred from icdrt to icdrs immediately, icdre is set to 1 again. do not write data to icdr when trs = 0 because the icdre flag value is invalid during the time. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 493 of 882 rej09b0108-0400 14.4 operation the i 2 c bus interface is capable of transferring da ta in either the serial format or the i 2 c bus format. 14.4.1 i 2 c bus data formats the i 2 c bus format is referred to as an addressing fo rmat. the transfer of da ta in this addressing format includes the transfer of acknowledge bits. this is shown in figure 14.3. the first frame after the start condition always consists of nine bits. the serial format is referred to as a ?non-addressing format?. th e transfer of data in this non- addressing format does not include the transfer of an acknowledge bit. this is shown in figure 14.4. the i 2 c bus timing is shown in figure 14.5. the symbols used in figures 14.3 to 14.5 are described in table 14.6. sa sla 7n r/ w data a 1 1m 11 1 a/ a 1 p 1 s sla 7n1 7 r/ w a data 11 1m1 1 a/ a 1 s 1 sla r/ w 1 1m2 a 1 data n2 a/ a 1 p 1 (a) fs=0 or fsx=0 upper: number of bits bein g transferred (n=1, n2=1 to 8) lower: number of frames bein g transferred (m=1, m2=1 or above) (b) when the start condition is re-transmitted, fs=0 or fsx=0 number of bits bein g transferred (n=1 to 8) number of frames bein g transferred (m=1 or above) figure 14.3 i 2 c bus data format (i 2 c bus format) s data 8n data fs=1 and fsx=1 number of bits bein g transferred (n=1 to 8) number of frames bein g transferred (m=1 or above) 1 1m p 1 figure 14.4 i 2 c bus data format (serial format) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 494 of 882 rej09b0108-0400 sda scl s sla r/w a 9 8 1-7 9 8 1-7 9 8 1-7 data a data a/a p figure 14.5 i 2 c bus timing table 14.6 i 2 c bus data format: description of symbols s this represents the start condition. t he master device changes the level on sda from high to low while scl is high. sla this represents the slave address. the ma ster device sends this to select the slave device. r/w this represents the direction of transmissi on/reception. when the r/ w bit is 1, data is transferred from the slave to the master device. when the r/w bit is 0, data is transferred from the master to the slave device. a this represents an acknowledgement. the receiving device sends this acknowledge bit by setting the level on sda to low (dur ing master transmission, the slave returns the acknowledge bits; during master recept ion, the master returns the acknowledge bits). data this represents the transfer of data. the amount of bits to be transferred in each such operation is set by the bc2 to bc 0 bits of icmr. the mls bit in icmr determines whether the data is transferred msb first or lsb first. p this represents the stop condition. t he master device changes the level on sda from low to high while scl is high. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 495 of 882 rej09b0108-0400 14.4.2 initialization initialize the iic following the procedure shown be low before starting the data transmission or reception. initialization start < 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 496 of 882 rej09b0108-0400 note: the icmr register should be modifi ed after transmit/receive operation has been completed. if the icmr regist er is modified during transm it/receive operation, bit counter bc2 to bc0 will be modified illegally, thus causing malfunction. 14.4.3 operations in master transmission in i 2 c bus format in the master transmit mode, th e master device outputs the transmit clock and data for transmission, and the slave devi ce acknowledges its reception of data. figure 14.7 is a flowchart that gives an example of operatio ns in master transmit mode. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 497 of 882 rej09b0108-0400 start end initial settin g read the bbsy fla g in iccr read the iric fla g in iccr read the iric fla g in iccr read the ackb bit in icsr write transmit data to icdr clear the iric fla g in iccr read the ackb bit in icsr clear the iric fla g in iccr clear the iric fla g in iccr read the iric fla g in iccr write data for transmission to icdr master receive mode set mst = 1 and trs = 1 (iccr) write bbsy = 0 and scp = 0 (iccr) write 0 to the acke bit in iccr write bbsy= 1 and scp = 0 (iccr) bbsy = 0? no iric = 1? ackb = 0? no no yes yes iric = 1? no yes yes transmit mode? iric = 1? transmission completed? (ackb = 1?) no no no yes yes yes [2] determine the states of the scl and sda lines. [3] set master transmit mode [4] start condition issuance [6] set transmit data for the first byte (slave address + r/ w) (after writin g to icdr, clear iric sequentially) [1] initial settin g [8] determine the acknowled g e bit transferred from the specified slave device. [5] wait for the start condition g eneration [7] wait for 1 byte to be transmitted. [10] wait for 1 byte to be transmitted. [11] determine the end of transfer [12] stop condition issua [9] set transmit data for the second and subsequent bytes. (after writin g to icdr, clear iric sequentially) figure 14.7 example: flowchart of op erations in the master transmit mode 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 498 of 882 rej09b0108-0400 the following description gives the procedures to transmit data serially in synchronization with icdr (icdrt) writing operation. 1. perform initialization according to the procedure described in section 14.4.2, initialization. 2. confirm that the bus is free by reading the bbsy flag in iccr. 3. set the mst and trs bits in iccr to 1 to select the master transmit mode. 4. then write 1 to bbsy and 0 to scp. this changes the level on sda from high to low while scl is high, and is thus the generation of the start condition. 5. with the generation of the start condition, the iric and irtr flags are set to 1. when the ieic bit in iccr has been set to 1, an interrupt request is generated for the cpu. 6. write the data (slave address + r/ w ) to icdr after the start condition is detected. in the i 2 c bus format (when the fs bit in sar or the fsx bit in sarx is 0), the first frame data following the start condition indicates the 7-bit slave addres s and transmit/receive direction (r/ w ). to determine the end of the transfer, the iric flag is cleared to 0. after writing to icdr, clear iric continuously in order that no other interrupt processing is executed. if the time for transmi ssion of one frame of data has passed before the iric flag clearing, the end of transmission cannot be determined. the master device transmits the transmit clock signal and the data written in the icdr. to acknowledge its selection, the sl ave device that has been sel ected (that matches the slave address) sets the level on sda low in the 9th cycle of the transmit clock. 7. when the transmission of one frame has been co mpleted, the iric flag is set to 1 on the rising edge of the 9th cycle of the transmit clock. th e level on scl is automatically fixed low in synchronization with the internal clock until the next data for transmission has been written to icdr. 8. read the ackb bit in icsr to confirm ackb = 0. when the slave device does not return acknowle dgement and ackb = 1, execute transmit end processing in step 12 and carry out transmission again. 9. write the transmit data to icdr. the iric flag is cleared to 0 to determine the end of the transfer. perform the icdr writing and the iric flag clearing sequentially as in step 6. transmission of the next frame is performed in synchronization with the internal clock. 10. when the transmission of one frame has been co mpleted, the iric flag is set to 1 on the rising edge of the 9th cycle of the transmit clock. th e level on scl is automatically fixed low in synchronization with the internal clock until the next data for transmission has been written to icdr. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 499 of 882 rej09b0108-0400 11. read the ackb bit in icsr. confirm that the slave device returns acknowledgement (ackb bit is 0). when there is still data to be transmitted, go to step 9 to conti nue the next transmission. when the slave device does not return acknowledgement (ackb bit is set to 1), follow step 12 to end transmission. 12. clear the iric flag to 0. write 0 to the acke bit in iccr, to clear the received ackb bit to 0. write 0 to bbsy and scp in iccr. this changes sda from low to high when scl is high, and generates the stop condition. sda (master output) sda (slave output) 2 1 r/w 4 36 58 7 12 9 a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 icdre irtr icdrt scl (master output) start condition g eneration slave address data 1 data 1 data 1 [9] icdr write [9] iric clear [6] icdr write [6] iric clear [4] write 1 to bbsy and 0 to scp (start condition issuance) user processin g interrupt request g eneration interrupt request g eneration address + r/ w iric [ 7 ] [ 5 ] icdrs address + r/ w note: data should not be written to icdr. figure 14.8 an example of the timing of operations in ma ster transmit mode (mls = wait = 0) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 500 of 882 rej09b0108-0400 sda (master output) sda (slave output) 2 14 36 58 79 89 a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 icdre irtr icdr scl (master output) stop condition g eneration data 2 [9] icdr write [9] iric clear [12] iric clear [11] ackb read [12] write 1 to bbsy and 0 to scp (stop condition issuance) iric a [10] [7] data 1 data 1 data 2 user processin g figure 14.9 an example of the stop condit ion issuance timing in master transmit mode (mls = wait = 0) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 501 of 882 rej09b0108-0400 14.4.4 operations in master reception in master receive mode, the mast er device outputs the receive clock, receives data, and returns acknowledgements of reception. the slave device transmits the data. the master device transmits data of the slave address + r/ w (1: read) in the first frame after start condition issuance in master transmit mode. after the slave device is selected, operation is changed to reception. reception with hnds f unction (hnds = 1): figure 14.10 is a flowchart that gives an exampl e of operations in mast er receive mode (hnds = 1). 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 502 of 882 rej09b0108-0400 end set trs = 0 (iccr) set ackb = 1 (icsr) read the iric fla g in iccr clear the iric fla g in iccr clear the iric fla g in iccr clear the iric fla g in iccr set hnds = 1 (scrx) write 0 to bbsy and scp (iccr) iric = 1? no yes yes read icdr no [4] clear iric fla g . [1] set receive mode [2] dummy read for startin g reception (first read) [5] read the receive data (second and subsequent read) [3] wait for 1 byte of data to be received. (set iric at the risin g ed g e of the 9th cycle of the clock for the receive frame.) [6] set acknowled g e data for the final reception. [10] read the receive data. [9] clear iric fla g [7] read the receive data. dummy read for startin g reception when the first frame is the final receive data. [11] set stop condition issuance. generate stop condition. master receive mode read the iric fla g in iccr iric = 1? no yes [8] wait for 1 byte of data to be received. set ackb = 0 (icsr) final reception? read icdr read icdr set trs = 1 (iccr) figure 14.10 example: flowchart of operat ions in the master receive mode (hnds = 1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 503 of 882 rej09b0108-0400 the following description gives th e procedures for and operations of receiving data in one byte units by fixing scl low for every data reception using the hnds bit function. 1. clear the trs bit in iccr to 0 to change from the transmit mode to the receive mode. clear the ackb bit in icsr to 0 (setting of the acknowledge data). set the hnds bit in scrx to 1. clear the iric flag to 0 to confirm that reception has been completed. when the first frame is the final receive data, pe rform end processing in step 6 and subsequent steps. 2. when icdr is read (a dummy read operation), the receiving of data starts; the receive clock is output in synchronization with the internal clock, and the first da tum is then received. (data of the sda pin is stored in icdrs in synchroniza tion with the rising ed ge of receive clock.) 3. the master device sets sda to low on the 9th cycle of th e receive clock and returns the acknowledge bit. the receive data is transferred from icdrs to icdrr at the rising edge of the 9th cycle of the receive clock, and the icdrf, iric, and irtr flags are set to 1. when the ieic bit in iccr has been set to 1, an interrupt request is generated for the cpu. the master devise fixes scl low between at the falling edge of 9th cycle of the receive clock and read of icdr data. 4. to identify the next interrupt, the iric flag is cleared to 0. when the next frame is the final receive data, pe rform end processing in step 6 and subsequent steps. 5. read the receive data of icdr. this clears th e icdrf flag to 0, and the master devise outputs the receive clock continuously for the reception of the next data. data can be received by repeating the steps 3 to 5. 6. set the ackb bit to 1 (setting of acknowledge data for the final reception). 7. read icdr receive data. this clears the ic drf flag to 0. the master device outputs the receive clock to receive data. 8. when one frame of data has been received, the icdrf, iric, and irtr flags are set to 1 at the rising edge of the 9th cycle of receive clock. 9. clear the iric flag to 0. 10. read icdr receives data after setting the trs bit to 1. this clears the icdrf flag to 0. 11. write 0 to bbsy and scp in iccr to generate the stop condition. this changes sda from low to high when scl is high, and generates the stop condition. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 504 of 882 rej09b0108-0400 sda (master output) sda (slave output) 2 1 4 3 6 5 8 7 1 2 9 9 a a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 irtr icdrf icdrr scl (master output) master transmit mode master receive mode data 1 data 1 data 2 [1] clear trs to 0 [2] icdr read (dummy read) [1] iric clear scl is fixed low until icdr is read scl is fixed low until icdr is read [4] iric clear user processin g iric [3] [5] icdr read (data 1) undefined figure 14.11 an example of the timing of operations in master receive mode (mls = wait = 0, hnds = 1) sda (master output) sda (slave output) 2 1 4 3 6 5 8 7 9 9 78 a a bit 7 bit 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 iric icdrf icdrr scl (master output) data 3 data 2 data 1 data 2 data 3 [9] iric clear user processin g irtr [ 8 ] [ 3 ] bit 0 [11] write 0 to bbsy and scp (stop condition instruction issuance) [4] iric clear [7] icdr read (data 2) [10] icdr read (data 3) [6] set ackb to 1 bit 0 stop condition g eneration scl is fixed low until icdr is read scl is fixed low until stop condition is issued figure 14.12 an example of the stop condition issuance timi ng in master receive mode (mls = wait = 0, hnds = 1) receive operation with wait: figure 14.13 and figure 14.14 are flowcharts that give examples of operations (wait = 1) in master receive mode. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 505 of 882 rej09b0108-0400 set trs = 0 (iccr) set ackb = 0 (icsr) set wait = 1 (icmr) yes yes yes clear the iric fla g in iccr clear the iric fla g in iccr read the iric fla g in iccr final reception? iric = 1? irtr = 1? yes irtr = 1? no no no no read the iric fla g in iccr iric = 1? no yes read icdr [4] determine the end of data reception. [13] determine the end of data reception. [1] set receive mode. [2] start receivin g . dummy read. [3] wait for a receive wait (set iric at the fallin g ed g e of the 8th cycle) or, wait for 1 byte to be received (set iric at the risin g ed g e of the 9th cycle). [12] wait for a receive wait (set iric at the fallin g ed g e of the 8th cycle) or, wait for 1 byte to be received (set iric at the risin g ed g e of the 9th cycle). [5] read the receive data. [6] clear the iric fla g (to cancel wait). [15] cancel wait mode. clear the iric fla g . (iric should be cleared to 0 after settin g wait = 0) [17] issue stop condition. master receive mode [14] clear the iric fla g (to cancel wait). [16] read final receive data. [7] set acknowled g e data for the final reception. [8] wait for trs settin g . [9] set trs for stop condition issuance. [10] read the receive data. [11] clear the iric fla g (to cancel wait). read icdr clear the iric fla g in iccr set hnds = 0 (scrx) wait for 1 cycle set ackb = 1 (icsr) set trs = 1 (iccr) end set wait = 0 (icmr) write 0 to bbsy and scp (iccr) clear the iric fla g in iccr read icdr clear the iric fla g in iccr read icdr figure 14.13 example: flowchart of operations in master receive mode (multiple bytes reception) (wait = 1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 506 of 882 rej09b0108-0400 end set hnds = 0 (scrx) set wait = 1 (icmr) set wait = 0 (icmr) set ackb = 0 (icsr) set ackb = 1 (icsr) read icdr clear the iric fla g in iccr clear the iric fla g in iccr clear the iric fla g in iccr read the iric fla g in iccr read icdr read the iric fla g in iccr iric = 1? yes no no iric = 1? yes [1] set receive mode. [2] start receivin g . dummy read. [15] cancel wait mode. clear the iric fla g . (iric should be cleared to 0 after settin g wait = 0) [11] clear the iric fla g (to cancel wait). [3] wait for a receive wait (set iric at the fallin g ed g e of the 8th cycle). [12] wait for 1 byte to be received (set iric at the risin g ed g e of the 9th cycle). [9] set trs for stop condition issuance. [7] set acknowled g e data for the final reception. [16] read the final receive data. master receive mode set trs = 0 (iccr) set trs = 1 (iccr) [17] issue stop condition write 0 to bbsy and scp (iccr) figure 14.14 example: flowchart of operations in master receive mode (one byte reception) (wait = 1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 507 of 882 rej09b0108-0400 the following description gives th e procedures to receive data se rially in synchr onization with icdr (icdrr) reading operation using wait operation (wait bit). the following description gives the procedures to receive multiple bytes. fo r the operation of receiving only one byte, see the flowchart in figure 14.14, since some procedur es are omitted in the following description. 1. clear the trs bit in iccr to 0 to change from the transmit mode to the receive mode. clear the ackb bit in icsr to 0 (setting of the acknowledge data). clear the hnds bit in scrx to 0 (canceling of the hand-shake function). clear the iric flag to 0, and then set the wait bit to 1. 2. when icdr is read (a dummy read operation), the receiving of data starts; the receive clock is output in synchronization with the internal clock, and the fi rst datum is then received. 3. the iric flag is set to 1 according to the following two. in this case, if the ieic bit in iccr is set to 1, an interrupt request is generated to the cpu. a. the iric flag is set to 1 at the falling edge of the 8th cycle of one frame of the receive clock. the scl is automatically fixed low in synchronization with the internal clock until the iric flag is cleared. b. the iric flag is set to 1 at the rising e dge of the 9th cycle of one frame of the receive clock. the irtr and icdrf flags are set to 1, in dicating that one frame of data has been completely received . the master device continues outpu tting the receive clock for the next receive data. 4. read the irtr flag in icsr. when the irtr flag is 0, cancel the wait operat ion by clearing the iric flag as described in step 6. when the irtr flag is 1 and the next data to be received is the final data, perform the end operation described in step 7. 5. when the irtr flag is 1, read the receive data in icdr. 6. clear the iric flag to 0. in the case of step 3 a, the master devise outputs the 9th cycle of the receive clock, drives the sda to low, and returns acknowledgement. data can be received by repeating steps 3 to 6. 7. set the ackb bit in icsr to 1 and set the acknowledge data fo r the final reception. 8. wait for at least one cycle of clock and the first cycle of the next receive data rises since the iric flag is set to 1. 9. change the mode from receive to transmit by setting the trs bit in iccr to 1. the set value of the trs bit becomes valid after the rising e dge of the 9th cycle of the clock is input. 10. read the receive data in icdr. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 508 of 882 rej09b0108-0400 11. clear the iric flag to 0. 12. the iric flag is set to 1 according to the following two conditions. a. the iric flag is set to 1 at the falling edge of the 8th cycle of one frame of the receive clock. scl is automatically fixed low in synchronization with the internal clock until the iric flag is cleared. b. the iric flag is set to 1 at the rising e dge of the 9th cycle of one frame of the receive clock. the irtr and icdrf flags are set to 1, indi cating that one frame of data have been completely received . the master devise continues outputting the receive clock for the next receive data. 13. read the irtr flag in icsr. when the irtr flag is 0, cancel wait mode by clearing the iric flag as described in step 14. when the irtr flag is 1 and the receive ope ration has been comple ted, issue the stop condition as described in step 15. 14. when the irtr flag is 0, clear the iric flag to 0 to cancel the wait operation. to detect the completion of receive operation, go back to step 12 and read the iric flag. 15. clear the wait bit in icmr to 0 to cancel th e wait mode, and then clear the iric flag to 0. clear the iric flag while wait is 0. (if the stop condition issuance inst ruction is executed by clearing the wait bit to 0 after clearing the ir ic flag to 0, the stop condition may not be output normally.) 16. read the final receive data in icdr. 17. write bbsy = 0 and scp = 0 to iccr. when scl is high, sda is driven from low to high, and the stop condition is generated. sda (master output) sda (slave output) 2 1 4 3 6 5 8 7 1 2345 9 9 a a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 iric irtr icdr scl (master output) master transmit mode master receive mode data 1 data 1 data 2 [2] icdr read (dummy read) [1] clear trs and iric to 0 [6] iric clear [6] iric clear (wait cancelled) user processin g [3] [ 4 ] irtr=1 [ 4 ] irtr=0 [3] [5] icdr read (data 1) figure 14.15 an example of the timing of operations in master receive mode (mls = ackb = 0, wait = 1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 509 of 882 rej09b0108-0400 sda (master output) sda (slave data output) 2 1 4 3 6 5 8 7 9 9 8 a a iric irtr icdr scl (master output) data 2 data 1 data 2 data 3 [6] iric clear [8] wait time for one cycle [11] iric clear [14] iric clear [16] icdr read (data 3) user processin g [12] [12] [3] [3] [10] icdr read (data 2) [9] set trs to 1 [7] set ackb to 1 [17] stop condition issuance stop condition g eneration [ 13 ] irtr=1 [ 4 ] irtr=1 [ 4 ] irtr=0 [15] clear wait to 0, iric clear data 3 [ 13 ] irtr=0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 figure 14.16 an example of the stop condition issuance timi ng in master receive mode (mls = ackb = 0, wait = 1) 14.4.5 operations in slave reception in the slave receive mode of the i 2 c bus format, the master device tr ansmits the transmit clock and data, and the slave device returns acknowledgement s of reception. the slave device compares the address of the slave address and the slave address of the firs t frame issued after the start condition issuance by the master device. if the addresses match, the slave device operates as a slave device specified by the master device. reception with hnds f unction (hnds = 1): figure 14.17 is a flowchart that gives an exampl e of operations in slav e receive mode (hnds = 1). 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 510 of 882 rej09b0108-0400 start end read the iric fla g in iccr clear the iric fla g in iccr clear the iric fla g in iccr read aasx, aas, and adz fla g s in icsr read the trs bit in iccr read the iric fla g in iccr clear the iric fla g in iccr clear the iric fla g in iccr read icdr read icdr set ackb = 0 (icsr) and hnds = 1 (scrx) general call address processin g * description omitted set mst = 0 and trs = 0 (iccr) iric = 1? no yes read the iric fla g in iccr set ackb = 1 (icsr) iric = 1? no yes trs = 1? iric = 1? yes yes no yes no aas = 1 and adz = 1? [1] initial settin g . set slave receive mode. [2] read remained receive data. [3] to [7] wait for one byte to be received (slave address + r/w). [10] read receive data. the first read is a dummy read. [12] clear the iric fla g . [9] set acknowled g e data for the final reception. [8] clear the iric fla g . [8] clear the iric fla g . [10] read receive data. [5] to [7] wait for completion of reception. [11] detect stop condition. slave transmit mode final reception? no no yes read icdr and clear iric no yes set initial value icdrf = 1? figure 14.17 example: flowchart of operat ions in the slave receive mode (hnds = 1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 511 of 882 rej09b0108-0400 the following description gives th e procedures for and operations of receiving data in one byte units by fixing scl low for every data reception using the hnds bit function. 1. perform initialization according to the procedure described in section 14.4.2, initialization. set slave receive mode by clearing the mst and tr s bits to 0. set the hnds bit to 1 and the ackb bit to 0. to confirm the receive comp letion, clear the iric flag in iccr to 0. 2. confirm that the icdrf flag is 0. if the icdrf flag is set to 1, read icdr and then clear the iric flag to 0. 3. when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. the master device then outputs the 7-b it slave address and transmit/receive direction (r/ w ) data in synchronization with the transmit clock pulses. 4. when the slave address matches the address in the first frame following the start condition generation, the slave device operates as the slav e devise specified by the master device. when the 8th bit of data (r/ w ) is 0, the trs bit remains 0 and sl ave receive operation is performed. when the 8th bit of data (r/ w ) is 1, the trs bit is set to 1 and slave transmit operation is performed. when addresses do not match, data receive op eration is not performe d until the next start condition is detected. 5. the slave devise returns the data set in the ackb bit as an acknowledg ement at the 9th cycle of the receive frame of the clock. 6. the iric flag is set to 1 at the 9th cycle of the cl ock. at this time, if the ieic bit is set to 1, an interrupt request is generated for the cpu. if the aasx bit is also set to 1, the irtr flag is set to 1. 7. at the rising edge of the 9th cycle of the clock, the receive da ta is transferred from icdrs to icdrr and the icdrf flag is set to 1. the sl ave device keeps scl low from the falling edge of the 9th cycle of the receive cl ock until data in icdr is read. 8. confirm that the stop bit is cleared to 0, and then clear the iric flag to 0. 9. when the next frame is the final r eceive flame, clear the ackb bit to 1. 10. after icdr has been read, the icdrf flag is cleared to 0 and the scl bus line is released. this enables master device to transfer the next data. receive operation can be continue d by repeating steps 5 to 10. 11. after the stop condition (when scl is high, the sda is changed from low to high) is detected, the bbsy flag is cleared to 0 and the stop bit is set to 1. at this time, if the stopim bit is cleared to 0, the iric flag is set to 1. 12. confirm that the stop bit is set to 1, and then clear the iric flag to 0. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 512 of 882 rej09b0108-0400 sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 icdrf iric icdrs icdrr scl (master output) scl (slave output) interrupt request g eneration address + r/ w undefined value [8] iric clear [10] icdr read (dummy read) user processin g 2 1 2 1 4 36 58 79 scl (pin waveform) start condition g eneration slave address data 1 [ 6 ] a r/ w [2] icdr read [7] scl is fixed low until icdr is read address + r/ w bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 14.18 an example of the timing of operations in slave receive mode 1 (mls = 0, hnds = 1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 513 of 882 rej09b0108-0400 sda (master output) sda (slave output) 2 14 36 58 79 89 icdrf icdrs icdrr iric scl (master output) scl (slave output) [8] iric clear [8] iric clear [12] iric clear [9] set ackb to 1 [10] icdr read (data (n -1)) [10] icdr read (data (n)) user processin g data (n) data (n) data (n -1) data (n -1) data (n -1) data (n -1) data (n -2) [6] [6] [11] a a stop condition g eneration [7] scl is fixed low until icdr is read [7] scl is fixed low until icdr is read bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 figure 14.19 an example of the timing of operations in slave receive mode 2 (mls = 0, hnds = 1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 514 of 882 rej09b0108-0400 continuous receive operation: figure 14.20 is a flowchart that gives an exampl e of operations in slav e receive mode (hnds = 0). start end read the iric fla g in iccr clear the iric fla g in iccr clear the iric fla g in iccr read aasx, aas, and adz fla g s in icsr read the trs bit in iccr read the iric fla g in iccr clear the iric fla g in iccr clear the iric fla g in iccr read icdr wait for one frame read icdr set ackb = 0 (icsr) initial settin g set ackb = 1 (icsr) set hnds = 0 (scrx) general call address processin g * description omitted * n: address + all receive byte set mst = 0 and trs = 0 (iccr) iric = 1? no yes icdrf = 1? yes trs = 1? iric = 1? icdrf = 1? yes yes yes yes no no yes no aas = 1 and adz =1? no no [1] initial settin g . set slave receive mode. [2] read remained receive data. [3] to [7] wait for one byte to be received (slave address + r/w) (iric is set at the 9th cycle of the clock). [9] wait for ackb settin g and set acknowled g e data for the final reception (after the rise of the 9th cycle of (n-1)th byte data). [15] clear the iric fla g . [14] read final receive data. [8] clear the iric fla g . [13] clear the iric fla g . [10] read receive data. the first read is a dummy read. [11] wait for one byte to be received (iric is set at the 9 th cycle of the clock) [12] stop condition is detected slave transmit mode yes no no read icdr no yes icdrf = 1? receive (n -2)th byte? estp = 1 or stop = 1? figure 14.20 example: flowchart of operations in slave transmit mode (hnds = 0) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 515 of 882 rej09b0108-0400 the following description gives the procedures fo r and operations of receiving data in slave receive mode. 1. perform initialization according to the procedure described in section 14.4.2, initialization. set slave receive mode by clearing the mst and trs bits to 0. set the hnds and ackb bits to 0. to confirm the receive completion, clear the iric flag in iccr to 0. 2. confirm that the icdrf flag is 0. if the icdrf flag is set to 1, read icdr and then clear the iric flag to 0. 3. when the start condition output by the master device is detected, the bbsy flag in iccr is set to 1. the master device then outputs the 7-b it slave address and transmit/receive direction (r/ w ) data in synchronization with the transmit clock pulses. 4. when the slave address matches the address in the first frame following the start condition generation, the slave device operates as the slav e devise specified by the master device. when the 8th bit of data (r/ w ) is 0, the trs bit remains 0 and sl ave receive operation is performed. when the 8th bit of data (r/ w ) is 1, the trs bit is set to 1 and slave transmit operation is performed. when addresses do not match, data receive op eration is not performe d until the next start condition is detected. 5. the slave devise returns the data set in the ackb bit as an acknowledg ement at the 9th cycle of the receive frame of the clock. 6. the iric flag is set to 1 at the 9th cycle of the cl ock. at this time, if the ieic bit is set to 1, an interrupt request is generated for the cpu. if the aasx bit is also set to 1, the irtr flag is set to 1. 7. at the rising edge of the 9th cycle of the clock, the receive da ta is transferred from icdrs to icdrr and the icdrf flag is set to 1. 8. confirm that the stop bit is cleared to 0, and then clear the iric flag to 0. 9. when the data to be read next is in two fram es before the final receive frame, ensure at least one frame of wait time. set the ackb bit to 1 after the 9th cycle of the receive frame preceding the final receive frame. 10. confirm that the icdrf flag is set to 1, and then read icdr. after icdr has been read, the icdrf flag is cleared to 0. 11. if the receive data is transferred from icdrs to icdrr at the rising ed ge of the 9th cycle of the clock or icdr read, iric and icdrf flags are set to 1. 12. after the stop condition (when scl is high, the sda is changed from low to high) is detected, the bbsy flag is cleared to 0 and the stop or es tp flag is set to 1. at this time, if the stopim bit is cleared to 0, the iric flag is set to 1. in this case, read the final receive data as described in step 14. 13. clear iric flag to 0. receive operation can be conti nued by repeating steps 9 to 13 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 516 of 882 rej09b0108-0400 14. confirm that the icdrf flag is set to 1, and then read icdr. 15. clear the iric flag to 0. sda (master output) sda (slave output) 2 14 32 14 3 6 58 7 9 bit 7 bit 6 bit 7 bit 6 bit 5 bit 4 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icdrf icdrs icdrr iric scl (master output) start condition issuance address + r/ w data 1 address + r/ w [8] iric clear [10] icdr read user processin g slave address data 1 [ 6 ] [ 7 ] a r/ w figure 14.21 an example of the timing of operations in slave receive mode 1 (mls = ackb = 0, hnds = 0) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 517 of 882 rej09b0108-0400 stop condition detection sda (master output) sda (slave output) 2 14 36 5 2 14 36 5 8 79 8 79 89 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 0 icdrf icdrs icdrr iric scl (master output) [9] set 1 to ackb [13] iric clear [10] icdr read (data (n -2)) [10] icdr read (data (n -1)) [13] iric clear [9] wait time for one frame user processin g bit 7 bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 data (n) data (n-1) data (n-1) data (n-1) data (n-2) data (n-2) data (n) data (n) data (n-2) [11] [11] [11] [12] a aa [13] iric clear [14] icdr read (data (n)) [15] iric clear figure 14.22 an example of the timing of operations in slave receive mode 2 (mls = ackb = 0, hnds = 0) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 518 of 882 rej09b0108-0400 14.4.6 operations in slave transmission when the address of the slave device matches the address which the master device transfers in the first frame (address receive frame) after start condition detection in slav e receive mode, and the 8th bit of data (r/ w ) is 1 (read), the trs bit in iccr is automatically set to 1 and slave transmit mode is entered. figure 14.23 is a flowchart that gives as ex ample of operations in slave transmit mode. end write transmit data to icdr clear the iric fla g in iccr clear the iric fla g in iccr set acke to 0 (iccr) (clear ackb to 0) clear the iric fla g in iccr read the iric fla g in iccr read the ackb bit in icsr set trs to 0 (iccr) read icdr read the iric fla g in iccr iric = 1? yes yes no no iric = 1? yes no [1], [2] if the slave address matches the address in the first frame followin g the start condition detection and the r/w bit is 1 in slave receive mode, the mode chan g es to slave transmit mode. [8] set slave receive mode. [6] clear the iric fla g . [7] clear acknowled g e bit data. [9] dummy read (to release the scl line). [10] wait for stop condition [3], [5] set transmit data for the second and subsequent frames. [3], [4] wait for 1 byte to be transmitted. [4] determine end of transfer. slave transmit mode transmission completed? (ackb = 1?) clear the iric fla g in iccr figure 14.23 example: flowchart of operations in slave transmit mode 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 519 of 882 rej09b0108-0400 in the slave transmit mode, the slave device tran smits data while the master device outputs the receive clock and returns acknow ledgements of reception. the fo llowing description gives the procedures for and operations of transmitting in slave transmit mode. 1. perform initialization of slave receive mode and wait for slave address reception. 2. when the slave address matches the address in the first frame following the start condition detection, the slave device drives sda to lo w at the 9th cycle of the clock and returns acknowledgement. when th e 8th bit of data (r/ w ) is 1, the trs bit is set to 1 and slave transmit mode is automatically entered. the iric flag is set to 1 at the rising edge of the 9th cycle of the clock. at this time, if the ieic bit is set to 1, an interrupt request is generated for the cpu. the icdre flag is set to 1. the sl ave device keeps scl low to prevent the master device from outputting the next transmit clock from the falling edge of the 9th cycle of the transmit clock until data is written to icdr. 3. after the iric flag is cleared to 0, the tran smit data is written to icdr. in this case, the icdre flag is cleared to 0. the written data is transferred to icdrs, and the icdre and iric flags are again set to 1. the slave device sequen tially transmits the data transferred to icdrs, on the basis of the clock from the master device. to detect the completion of transmission, clear the iric flag to 0. after writing the icdr register, sequentially clear th e iric flag so that no other process is inserted. 4. the master device drives sda to low at the 9th cycle of the transfer frame and returns the acknowledgement. since the acknowledgement is stored in the ackb bit in icsr, it can be checked whether transfer operation is performed normally. on e frame of data transmission is completed and the iric flag is set to 1 at the rising edge of the 9th cycle of the transmit clock. when the icdre flag is 0, data written to the icdr is transferred to icdrs and one frame of data transmission is started, and then the ic dre and iric flags are ag ain set to 1. if the icdre flag is set to 1, scl is kept low from the falling edge of the 9th cycle of the transmit clock until the data is written to the icdr. 5. to continue with the transmission, write the next data for transmission to icdr. in this case, the icdre flag is cleared to 0. to detect the co mpletion of transmission, clear the iric flag to 0. perform the icdr register writing and the iric flag clearing sequentially so that no other process is inserted. transmission can be continued by repeating steps 4 and 5. 6. clear the iric flag to 0. 7. to end the transmission, clear the acke bit in iccr and the acknowledge bit stored in the ackb bit to 0. 8. for the next address recep tion, clear the trs bit to 0 and enter slave receive mode. 9. to release sda on the sl ave side, dummy read icdr. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 520 of 882 rej09b0108-0400 10. when scl is high and the stop condition is detected due to the change of sda from low to high, the bbsy flag in iccr is cleared to 0 and the stop flag in icsr is set to 1. when the stopim bit in icxr is 0, the iric flag is set to 1. when the iric flag is set to 1, clear the flag to 0. sda (master output) sda (slave output) 2 1 2 1 4 36 58 79 9 8 bit 7 bit 6 bit 5 bit 7 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 icdre icdr iric scl (master output) slave receive mode slave transmit mode [3] iric clear [5] iric clear [3] icdr write [3] iric clear [5] icdr write user processin g data 1 data 1 data 2 data 2 a r/ w a [ 4 ] [ 2 ] figure 14.24 an example of the timing of operations in slave transmit mode (mls = 0) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 521 of 882 rej09b0108-0400 14.4.7 timing for setting ir ic and the control of scl the timing with which the interrupt-request flag (ir ic) is set varies according to the settings of the wait bit in icmr, fs bit in sar, and the fsx bit in sarx. when the icdre and icdrf flags are set to 1, the level on scl is automatically set low in synchronization with the internal clock after the transfer of one frame of data. figures 14.25 to 14.27 show the timing with which iric is set and the control of scl. scl sda iric 23 1 a 8 7 3 2 1 9 8 7 when wait = 0, and fs = 0 or fsx = 0 (i 2 c bus format, no wait) (a) when data transfer ends with icdre = 0 at transmission, or icdrf = 0 at reception. (b) when data transfer ends with icdre = 1 at transmission, or icdrf = 1 at reception scl sda iric user processin g user processin g iric clear iric clear iric clear icdr write (durin g transmission) or icdr read (durin g reception) 1 a 8 7 1 9 8 7 figure 14.25 iric flag set timing and the control of scl (1) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 522 of 882 rej09b0108-0400 scl sda iric 2 13 a 8 123 9 8 when wait = 1, and fs = 0 or fsx = 0 (i 2 c bus format, wait inserted) scl sda iric icdr write (durin g transmission) or icdr read (durin g reception) 1 a 8 1 9 8 (a) when data transfer ends with icdre = 0 at transmission, or icdrf = 0 at reception. (b) when data transfer ends with icdre = 1 at transmission, or icdrf = 1 at reception. user processin g user processin g iric clear iric clear iric clear iric clear figure 14.26 iric flag set timing and the control of scl (2) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 523 of 882 rej09b0108-0400 scl sda iric 1 8 7 4 123 8 7 when fs = 1 and fsx = 1 (synchronous serial format) (a) when data transfer ends with icdre = 0 at transmission, or icdrf = 0 at reception. scl sda iric icdr write (durin g transmission) or icdr read (durin g reception) 8 72 14 3 1 8 7 (b) when data transfer ends with icdre = 1 at transmission, or icdrf = 1 at reception. user processin g user processin g iric clear iric clear iric clear figure 14.27 iric flag set timing and the control of scl (3) 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 524 of 882 rej09b0108-0400 14.4.8 dtc operation this lsi provides the dtc to allow continuous da ta transfer. the dtc is initiated when the irtr flag is set to 1, which is one of the two interrupt flags (iric and irtr). when the acke bit is 0, the icdre, iric, and irtr flags are set at th e end of data transmission regardless of the acknowledge bit value. when the acke bit is 1, the icdre, iric, and irtr flags are set if data transmission is completed with the acknowledge bit va lue of 0, or only the iric flag is set if data transmission is completed with the acknowledge bit value of 1. when initiated, dtc transfers specified number of bytes, clears the icdre, iric, and irtr flags to 0. therefore, no interrupt is generated during continuous data transfer; however, if data transmission is completed with the acknowledge b it value of 1 when the acke bit is 1, dtc is not initiated, thus allowing an interrupt to be generated if enabled. the acknowledge bit may indicate specific events such as comple tion of receive processing for some receiving device, and for other receiving de vice, the acknowledge bit may be held to 1, indicating no specific event. in the i 2 c bus format, since the slave device or the dir ection of transfer is selected by the slave address or the r/ w bit, and the acknowledge bit may indicate the end of reception or reception of the final frame, the continuous transfer of data by the dtc must be combined with interrupt- driven processing by the cpu. table 14.7 shows examples of processes in which the dtc is used. for the slave-mode processes, it is assumed that the amount of data to be transferred is defined in advance. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 525 of 882 rej09b0108-0400 table 14.7 examples of operati ons in which the dtc is used item master transmit mode master receive mode slave transmit mode slave receive mode slave address + r/ w bit transmission/recep tion dtc transmission (icdr write) cpu transmission (icdr write) cpu reception (icdr read) cpu reception (icdr read) dummy data read ? cpu processing (icdr read) ? ? main unit data transmission/recep tion dtc transmission (icdr write) dtc reception (icdr read) dtc transmission (icdr write) dtc reception (icdr read) final frame processing unnecessary cpu reception (icdr read) unnecessary cpu reception (icdr read) setting the number of frames of data to be transferred in dtc transmission: number of actual frames of data + 1 (+1 represents the frame for slave address + r/w bits) reception: number of actual frames of data transmission: number of actual frames of data reception: number of actual frames of data 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 526 of 882 rej09b0108-0400 14.4.9 noise canceller the states on the scl and sda pins are fetched inte rnally via the noise can celler. figure 14.28 is a block diagram of the noise canceller. the noise canceller consists of a 2-stage latch circuit and match-detection circuit, which are connected in series. the input signal on the scl pi n (or on the sda pin) is sampled on the system clock; when the two latch outputs match, the given level is then sent to the next stage. if the two values do not match, the existing value is maintained. c q d c q d samplin g clock samplin g clock scl input si g nal or sda input si g nal latch latch match-detection circuit system clock period internal scl si g nal or internal sda si g nal figure 14.28 block diagra m of the noise canceller 14.4.10 initialization of internal state this iic module has a function for forcible initialization of its internal state if a deadlock occurs during communication. initialization is executed by clearing ice bit. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 527 of 882 rej09b0108-0400 scope of initialization: the initialization executed by this function covers the following items: ? icdre and icdrf internal flags ? transmit/receive sequencer and inte rnal operating clock counter ? internal latches for retaining the output state of the scl and sda pins (wait, clock, data output, etc.) the following items are not initialized: ? actual register values (icdr, sar, sarx , icmr, iccr, icsr, scrx (except for the icdre and icdrf flags) ? internal latches used to retain register read information for setting/clearing flags in the icmr, iccr, and icsr registers ? the value of the icmr register bit counter (bc2 to bc0) ? generated interrupt sources (interrupt sources transferred to the interrupt controller) notes on initialization: ? interrupt flags and interrupt sour ces are not cleared; therefore, fl ag clearing measures must be taken as necessary. ? basically, other register flags are not cleared eith er; therefore, flag clear ing measures must be taken as necessary. ? if a flag clearing setting is made during tr ansmission/reception, the iic module will stop transmitting/receiving at that point and the scl and sda pins will be released. when transmission/reception is started again, register initialization, etc., mu st be carried out as necessary to enable correct communication as a system. the value of the bbsy bit cannot be modified directly by this module clear function, but since pin waveforms with stop condition may be generated depending on the state and release timing of the scl and sda pins, causing the bbsy bit to be cleared. similarly, switching of the state may influence other bits and flags. to prevent problems caused by these factors, the following procedure should be used when initializing the iic state. 1. execute initialization of the internal state by clearing the ice bit. 2. execute a stop condition issue instruction (write 0 to bbsy and scp) to clear the bbsy bit to 0, and wait for two transfer rate clock cycles. 3. re-execute initialization of the internal state by clearing the ice bit. 4. initialize (reset) the iic registers. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 528 of 882 rej09b0108-0400 14.5 usage notes 1. in master mode, when the instruction that generates the start condition is issued immediately after the instruction that generates the stop condition, neither the start condition nor the stop condition will be correctly output. for the consecutive output of the start condition and stop condition, read the port after issuing the instruction that generates the start condition, and make sure that the levels on both scl and sda are lo w. then issue the instruction that generates the stop condition. note that scl may not have completely reached its low level when bbsy becomes 1. 2. the following two conditions apply to the start of the next transfer: take note when reading from/writing to icdr. ? ice = 1, trs = 1, and data is written to icdr (including automatic transfer from icdrt to icdrs) ? ice = 1, trs = 0, and data is read from icdr (including automatic transfer from icdrs to icdrr) 3. in synchronization with the internal clock, scl and sda are output with the timing shown in table 14.8. the timing on the bus is determined by the rise/fall times of the signals, and these are affected by the bus-load?s capacitance, series resistan ce, and parallel resistance. table 14.8 i 2 c bus timing (output of scl and sda) item symbol output timing unit remarks scl-output cycle time t sclo 28 t pcyc to 256 t pcyc ns scl-output high-pulse width t sclho 0.5 t sclo ns scl-output low-pulse width t scllo 0.5 t sclo ns sda-output bus-free time t bufo 0.5 t sclo ? 1 t pcyc ns start-condition-output hold time t staho 0.5 t sclo ? 1 t pcyc ns output setup time for re-transmission of start condition t staso 1 t sclo ns setup time for output of the stop condition t stoso 0.5 t sclo +2 t pcyc ns setup time for the output of data (master) 1 t scllo ? 3 t pcyc ns setup time for the output of data (slave) t sdaso 1 t scll ? (6 t pcyc or 12 t pcyc * ) ns data-output hold time t sdaho 3 t pcyc ns note: * when the iicx is 0, 6 t pcyc . when iicx is 1, 12 t pcyc . 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 529 of 882 rej09b0108-0400 4. the scl and sda inputs are sampled in synchronization with p . therefore, the ac timing depends on the period of p cycle t pcyc . when the p frequency does not reach 5 mhz, the ac timing specifications of the i 2 c bus interface are not satisfied. 5. the scl rising time t sr is defined as being within 1,000 ns (300 ns in the high-speed mode). the i 2 c bus interface monitors scl in the master mode, and commun ication is synchronized in a bit-by-bit basis. when the rise time t sr (the time required to reach v ih from an initially low level) of scl exceeds the time determ ined by the input clock of the i 2 c bus interface, the high- level period of scl is extended. the time scl takes to rise is determined by the pull-up resistance and the load capacitance. therefore, to operate at the specified transfer rate, set the pull-up resistance and load cap acitance so that each time is within the corresponding value given in table 14.9. table 14.9 tolerance of the scl rise time (t sr ) time [ns] iicx t pcyc i 2 c bus specification (max.) p = 10mhz p = 16mhz p = 20mhz p = 25mhz p = 33mhz p = 40mhz standard mode 1000 750 468 375 300 227 188 0 7.5 t pcyc high-speed mode 300 227 188 1 17.5 t pcyc standard mode 1000 875 700 530 438 high-speed mode 300 6. the rise and fall times of scl and sda are re spectively prescribed as being 1000 ns or less and 300 ns or less by the i 2 c bus specification. the output timing of scl and sda for the i 2 c bus interface of this lsi are described by t pcyc as shown in table 14.8. however, due to the effect of the rise and fall times, the i 2 c bus interface specifications may not be satisfied at the maximum transfer rate. table 14.10 shows the results of calculating the output timing for each available operating frequency, by considering the worst-case rise and fall times. t bufo does not satisfy the specifications of the i 2 c bus interface specifications. ta ke either of the following countermeasures agains t this problem: a. ensure that your program provides the required interval (approximately 1 s) between issuing of the stop condition and of the next start condition. b. select a slave device with an input timing that permits use with this output timing for connection to the i 2 c bus. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 530 of 882 rej09b0108-0400 for t scllo in high-speed mode and t staso in standard mode, the i 2 c bus interface specification is not satisfied when the worst case for t sr /t sf is assumed. take one of the following steps: a. adjust the rise and fall times by changing the pull-up resistors an d load capacitance. b. reduce the transfer rate until the specification is satisfied. c. for connection to the i 2 c bus, select a slave device with an input timing that permits use with this output timing. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 531 of 882 rej09b0108-0400 table 14.10 i 2 c bus timing (when the effect of t sr /t sf is at its maximum) time (at maximum transfer rate) [ns] item t pcyc effect of t sr /t sf (max) i 2 c bus specification (min) p = 10mhz p = 16mhz p = 20mhz p = 25mhz p = 33mhz p = 40mhz standard mode -1000 4000 4000 4000 4000 4000 4000 4000 t sclho 0.5 t sclo ( ? t sr ) high-speed mode -300 600 950 950 950 950 950 950 standard mode -250 4700 4750 4750 4750 4750 4750 4750 t scllo 0.5 t sclo ( ? t sf ) high-speed mode -250 1300 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 1000 * 1 standard mode -1000 4700 3900 * 1 3938 * 1 3950 * 1 3960 * 1 3970 * 1 3975 * 1 t bufo 0.5 t sclo ? 1 t pcyc ( ? t sr ) high-speed mode -300 1300 850 * 1 888 * 1 900 * 1 910 * 1 920 * 1 925 * 1 standard mode -250 4000 4650 4688 4700 4710 4720 4725 t staho 0.5 t sclo ? 1 t pcyc ( ? t sf ) high-speed mode -250 600 900 938 950 960 970 975 standard mode -1000 4700 9000 9000 9000 9000 9000 9000 t staso 1 t sclo ( ? t sr ) high-speed mode -300 600 2200 2200 2200 2200 2200 2200 standard mode -1000 4000 4200 4125 4100 4080 4061 4050 t stoso 0.5 t sclo +2 t pcyc ( ? t sr ) high-speed mode -300 600 1150 1075 1050 1030 1011 1000 standard mode -1000 250 3400 3513 3550 3580 3609 3625 t sdaso as master 1 t scllo * 3 ? 3 t pcyc ( ? t sr ) high-speed mode -300 100 700 813 850 880 909 925 standard mode -1000 250 2500 2950 3100 3220 3336 3400 t sdaso as slave 1 t scll * 3 ? 12 t pcyc * 2 ( ? t sr ) high-speed mode -300 100 -200 * 1 250 400 520 636 700 t sdaho 3 t pcyc standard mode 0 0 300 188 150 120 91 75 high-speed mode 0 0 300 188 150 120 91 75 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 532 of 882 rej09b0108-0400 notes: 1. apply one or more of t he following measures to satisfy the i 2 c bus interface specification. ? ensure that the interval between the setti ng of the start condition and of the stop condition is sufficient. ? adjust the rise and fall times by changing the values of the pull-up resistors and load capacitance. ? adjust the system by decreasing the transfer rate. ? select a slave device with an input timing that permits the i/o timing. the values in the above table are changed by the setting of the iicx bit and the cks2 to cks0 bits. since the maximum transfer rate may not be achievable, depending on the frequency, check whether or not the i 2 c bus interface specification is satisfied under the actual conditions that are set. 2. when the iicx bit is 1. when the iicx bit is 0, (t scll ? 6t pcyc ). 3. calculated from the i 2 c bus specifications (standard 4700 ns/min, high-speed: 1300 ns/min.) 7. points for caution wh en reading icdr at the end of master reception to halt the reception of data after a receive operation in the master receive mode has been completed, set the trs bit to 1 and write 0 to bbsy and scp. by doing so, the level on sda will be changed from low to high while scl is high, that is, the stop condition will be generated. the received data can be read by reading icdr. if there is data in the buffer, however, the data received in icdrs cannot be transferred to icdr (icdrr). therefore, the second-byte of data cannot be read. when reading of the second-byte of data is required, set the stop condition in the master receive mode (with the trs bit being 0). when read ing the received data, confirm that the bbsy bit in iccr is 0, the stop condition has been generated, and the bus is released. after that, read the icdr register while trs is 0. in this case, if an attempt is made to read th e received data (data in icdr) during the period from the execution of the instruction (write 0 to bbsy and scp of iccr) that sets the stop condition and the actual generation of the stop condition, it is not possible to generate the clock correctly for a the subseque nt master transmission. rewriting of the i 2 c control bit to change the mode of operation or setting of transmission/reception, such as clearing of the mst bit after the completion of transmission/reception by the mast er, must not take place in any period other than period (a) (after confirming that the bbsy bit in iccr has been cleared to 0) in figure 14.29. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 533 of 882 rej09b0108-0400 sda scl a 8 9 bit 0 internal clock bbsy bit stop condition start condition master-reception mode icdr read-disabled period execution of the instruction that sets the stop condition (writin g 0 to bbsy and scp) confirmation of stop-condition (readin g 0 from bbsy) start condition set (a) figure 14.29 points for caution in reading data r eceived by master reception 8. points for caution in setting th e start condition for re-transmission figure 14.30 shows the timing and flowchart of the setting of the start condition for re- transmission, and the timing with which the data is continuously written to icdr. write the transmit data to icdr after the start condition fo r re-transmission is issued and then the start condition is actually generated. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 534 of 882 rej09b0108-0400 yes yes yes yes no no no no sda ack bit7 iric scl iric=1? scl=low? iric = 1? clear iric in iccr set the start condition? read the scl pin other processin g write 1 to bbsy and 0 to scp of icsr write the data for transmission to icdr [1] wait for completion of one-byte transfer. [2] decide whether or not scl is low. [3] execuse the instruction that sets the start condition for re-transmission. [4] confirm the start condition g eneration [5] set the data for transmission (slave address+r/ w ) [1] tastin g of iric [2] testin g of scl=low [3] start condition instruction issuance (re-transmission) [4] testin g of iric start condition (re-transmission) [5] write to icdr (transfer data) note: pro g ram so that steps 3 to 5 above are executed continuously. figure 14.30 flowchart and timing of the execution of the instruction that sets the start condition for re-transmission 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 535 of 882 rej09b0108-0400 9. points for caution in the execution of the instruction that sets the i 2 c bus interface stop condition if the rise time in the 9th cycle of scl exceeds the specified value du e to a high bus-load capacitance, or if a slave device inserts a wait by setting the level on scl low, read scl after the rise of 9th cycle of the clock to confirm that the level is low, and then execute the instruction that sets the stop condition. sda iric scl vih 9 th cycle period for securin g the hi g h-level period scl is detected as low since this waveform takes a lon g time to rise. stop condition [1] decision on whether or not scl is low [2] stop condition instruction g eneration figure 14.31 timing for the setting of the stop condition 10. notes on wait function ? conditions to cause this phenomenon when both of the following conditions are satis fied, the clock pulse of the 9th clock could be outputted continuously in master mode using the wait function due to the failure of the wait insertion after the 8th clock fall. (1) setting the wait bit of the icmr register to 1 and operating wait, in master mode (2) if the iric bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock and the fall of the 8th clock. ? error phenomenon normally, wait state will be cancelled by clearing the iric flag bit from 1 to 0 after the fall of the 8th clock in wait state. in this ca se, if the iric flag bit is cleared between the 7th clock fall and the 8th clock fall, the iric fl ag clear- data will be retained internally. therefore, the wait state will be cancelled ri ght after wait insertion on 8th clock fall. ? restrictions please clear the iric flag before the rise of the 7th clock (the counter value of bc2 through bc0 should be 2 or greater), after the iric flag is set to 1 on the rise of the 9th clock. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 536 of 882 rej09b0108-0400 if the iric flag-clear is delayed due to the interrupt or other processes and the value of bc counter is turned to 1 or 0, please confirm th e scl pins are in l? state after the counter value of bc2 through bc0 is turned to 0, and clear the iric flag. (see figure 14.32.) scl bc2?bc0 transmit/receive data a asd 7 6 5 4 3 2 1 0 7 6 5 1 2 3 4 5 6 7 8 9 1 2 3 0 iric fla g clear unavailable iric fla g clear available iric fla g clear available 9 a iric (operation example) scl = ?l? confirm iric clear when bc2-0 2 iric clear transmit/receive data figure 14.32 iric flag clea r timing on wait operation 11. points for caution of clearing the iric flag when the wait function is used while the wait function is used in i 2 c bus interface master mode, if the rise time of scl exceeds the specified value or if a slave device in which a wait can be inserted by driving scl low is used, read scl in the following way to confirm that scl has become low, and then clear the iric flag. if the iric flag is cleared to 0 with wait = 1 while scl is extending the high level period, the sda level may change before scl becomes low, generate a start or stop condition erroneously. scl iric [1] decision on whether or not scl is low scl is detected as low vih secure period in which scl is hi g h [2] iric clear sda figure 14.33 timing for clea ring iric flag when wait = 1 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 537 of 882 rej09b0108-0400 12. points for caution when reading icdr an d accessing iccr in slave transmit mode in i 2 c bus interface slave transmit mode, do not re ad icdr or do not read/write to iccr during the period shaded in figure 14.34. however, in interrupt handling processing that is generated in synchronization with the rising edge of the 9th cycle of the clock, reading icdr or reading/writing to iccr causes no error b ecause the shaded period has passed before making the transition to interrupt handling. to handle interrupts securely, be sure to keep either of the following conditions. ? before starting the receive operatio n of the next slave address, fi nish the read of icdr data that has been received so far or the read/write of iccr. ? monitor the bc2 to bc0 counter in icmr; when the count is 000 (8th or 9th cycle of the clock), wait for at least two transfer clocks to let the shaded period pass. then, read icdr or read/write to iccr. sda scl trs bit r/w a bit 7 data transmission 89 address reception write to icdr period in which read from icdr and read from or write to iccr are prohibited (6 peripheral clocks) detection of rise of 9th transmit/receive clock erroneous waveforms figure 14.34 timing for reading icdr a nd accessing iccr in slave transmit mode 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 538 of 882 rej09b0108-0400 13. points for cautions when setting trs bit in slave mode in i 2 c bus interface slave mode, th e value set to the trs bit in iccr immediately becomes valid if it is set from the time when the rising edge of the 9th cycle or the stop condition is detected until the time when the next rising edge on the scl pin is detected (the period indicated as (a) in figure 14.35). however, if the trs bit is set outside the period mentioned above (the period indicated as (b) in figure 14.35), the bit value does not become valid immediately because it is suspended until the rising edge of the 9th cycle or the stop condition is detected. therefore, when the address is received after the re-trans mission start condition in put without the stop condition, the effective trs bit value remains 1 (transmit mode) intern ally and thus the acknowledge bit is not transmitted after the address has been r eceived at the 9th cycle of the clock. to receive the address in slave mode, clear the trs bit to 0 duri ng the time indicated as (a) in figure 14.35. to release scl low-level fixation that is held by means of the wait function in slave mode, clear the trs bit to 0 and then dummy-read icdr. resumption condition data transmission address reception scl trs period in which trs bit settin g is retained icdr dummy read trs bit settin g (a) (b) 8 a 9 123 456 789 detection of rise of 9th cycle sda detection of rise of 9th cycle figure 14.35 timing for setting trs bit in slave mode 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 539 of 882 rej09b0108-0400 14. points for cautions wh en reading icdr in transmit mode an d writing to icdr in receive mode when icdr is read in transmit mode (trs = 1) or icdr is written to in receive mode (trs = 0), the scl pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the scl bus line before icdr is accessed correctly. to access icdr correc tly, read the icdr after setting to receive mode or write to the icdr after setting to transmit mode. 15. points for cautions on acke and trs bits in slave mode in the i 2 c bus interface, if 1 is received as the ackno wledge bit value (ackb = 1) in transmit mode (trs = 1) and then the address is received in slave mode without performing appropriate processing, interrupt handling may start at the rising edge of the 9th cycle of the clock even when the address does not match. similarly, in slave mode, if the start condition or address is transmitted from the master device in transmit mode (trs = 1), the iric flag may be set as a result of the icdre flag set or receiving 1 as the acknowledge bit value (ackb = 1), thus causi ng an interrupt source to occur even when the address does not match. to use the i 2 c bus interface module in slave mode, be su re to follow the procedures below. ? when 1 is received as the ackno wledge bit value for the final transmit data at the end of a series of transmit operations, clear the acke bit in iccr once to initialize the ackb bit to 0. ? set to receive mode (trs = 0) before the next start condition is input in slave mode. complete transmit operation by the procedure shown in figure 14.23, in order to switch from slave transmit mode to slave receive mode. 14.5.1 module stop mode setting iic is enabled or disabled using the module stop control register. iic is disabled with the initial value. cancelling module stop mo de allows the register to be acce ssed. for details, see section 24, power-down modes. 14. i 2 c bus interface (iic) option rev.4.00 mar. 27, 2008 page 540 of 882 rej09b0108-0400 15. a/d converter adcms20b_010020020700 rev.4.00 mar. 27, 2008 page 541 of 882 rej09b0108-0400 section 15 a/d converter this lsi includes a successive approximation type 10-bit a/d converter. the block diagram of the a/d converter is shown in figure 15.1. 15.1 features ? 10-bit resolution ? input channels ? 8 channels (two independent a/d conversion modules) ? conversion time: 5.4 s per channel (at p = 25-mhz operation), 6.7s per channel (at p = 20-mhz operation) ? three operating modes ? single mode: single-channel a/d conversion ? continuous scan mode: continuous a/d conversion on 1 to 4 channels ? single-cycle scan mode: single-cycle a/d conversion on 1 to 4 channels ? data registers ? conversion results are held in a 16- bit data register for each channel ? sample and hold function ? three methods for conversion start ? software ? conversion start trigger from mu ltifunction timer pulse unit (mtu) ? external trigger signal ? interrupt request ? an a/d conversion end interrupt request (adi) can be generated ? module standby mode can be set 15. a/d converter rev.4.00 mar. 27, 2008 page 542 of 882 rej09b0108-0400 control circuit control circuit + p /8 adtrg mtu tri gg er an0 an1 an2 an3 p /4 p /16 av cc av ref av ss addr0 adcsr_0 adcr_0 addr1 addr2 adtsr addr3 adi0(dtc) interrupt si g nal p /32 p /8 p /4 p /16 p /32 (only for sh7145) (only for sh7145) 10-bit d/a a/d0 a/d1 + an4 an5 an6 an7 av cc av ref av ss addr4 adcsr_1 adcr_1 addr5 addr6 addr7 adi1 (dmac/dtc) interrupt si g nal adcr_0: adcsr_0: addr0: addr1: addr2: addr3: a/d0 control re g ister a/d0 control/status re g ister a/d0 data re g ister 0 a/d0 data re g ister 1 a/d0 data re g ister 2 a/d0 data re g ister 3 a/d1 control re g ister a/d1 control/status re g ister a/d1 data re g ister 4 a/d1 data re g ister 5 a/d1 data re g ister 6 a/d1 data re g ister 7 adcr_1: adcsr_1: addr4: addr5: addr6: addr7: bus interface bus interface [le g end] sample-and-hold circuit comparator comparator analo g multiplexer analo g multiplexer sample-and-hold circuit successive approximations re g ister 10-bit d/a successive approximations re g ister module data bus module data bus figure 15.1 block di agram of a/d converter 15. a/d converter rev.4.00 mar. 27, 2008 page 543 of 882 rej09b0108-0400 15.2 input/output pins table 15.1 summarizes the input pins used by the a/d converter. this lsi has two a/d conversion modules, each of which can be operated independently. the input channels are divided into four channel sets. the analog input pins are as shown in table 15.1. table 15.1 pin configuration module type pin name i/o function common av cc input analog block power supply and reference voltage av ref input a/d conversion reference voltage (only for sh7145) av ss input analog block ground and reference voltage adtrg input a/d external trigger input pin an0 input analog input pin 0 a/d module 0 (a/d0) an1 input analog input pin 1 an2 input analog input pin 2 an3 input analog input pin 3 an4 input analog input pin 4 a/d module 1 (a/d1) an5 input analog input pin 5 an6 input analog input pin 6 an7 input analog input pin 7 note: the connected a/d module differs for each pi n. the control registers of each must be set each module. the av ref pin is internally connected to the av cc pin in the sh7144. 15. a/d converter rev.4.00 mar. 27, 2008 page 544 of 882 rej09b0108-0400 15.3 register descriptions the a/d converter has the following registers. for details on register addresses and register states in each processing state, refer to section 25, list of registers. ? a/d data register 0 (addr0) ? a/d data register 1 (addr1) ? a/d data register 2 (addr2) ? a/d data register 3 (addr3) ? a/d data register 4 (addr4) ? a/d data register 5 (addr5) ? a/d data register 6 (addr6) ? a/d data register 7 (addr7) ? a/d control/status register_0 (adcsr_0) ? a/d control/status register_1 (adcsr_1) ? a/d control register_0 (adcr_0) ? a/d control register_1 (adcr_1) ? a/d trigger select register (adtsr) 15.3.1 a/d data registers 0 to 7 (addr0 to addr7) addrs are 16-bit read-only registers. the conversion result for each analog input channel is stored in addr with the corresponding number. (for example, the conversion result of an4 is stored in addr4.) the converted 10-bit data is stored in bits 6 to 15. the lower 6 bits are always read as 0. the data bus between the cpu and the a/d converter is 8 bits wide. the upper byte can be read directly from the cpu, however the lower byte should be read via a temporary register. the temporary register cont ents are transferred from the addr when the upper byte data is read. when reading the addr, read the upper byte before the lower byte, or read in word unit. the initial value of addr is h'0000. 15. a/d converter rev.4.00 mar. 27, 2008 page 545 of 882 rej09b0108-0400 15.3.2 a/d control/status register_0, 1 (adcsr_0, adcsr_1) adcsr for each module controls a/d conversion operations. bit bit name initial value r/w description 7 adf 0 r/(w) * a/d end flag a status flag that indicates the end of a/d conversion. [setting conditions] ? when a/d conversion ends in single mode ? when a/d conversion ends on all specified channels in scan mode [clearing conditions] ? when 0 is written after reading adf = 1 ? when the dmac or the dtc is activated by an adi interrupt and data is read from addr while the dtmr bit in the dtc is cleared to 0 6 adie 0 r/w a/d interrupt enable the a/d conversion end interrupt (adi) request is enabled when 1 is set when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. 5 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 4 adm 0 r/w a/d operating mode select selects the a/d conversion mode. 0: single mode 1: scan mode when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. 3 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 2 ? 0 r reserved this bit is always read as 0. the write value should always be 0. 15. a/d converter rev.4.00 mar. 27, 2008 page 546 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 0 ch1 ch0 0 0 r/w r/w channel select 1, 0 select analog input channels. see table 15.2. when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. note: * only 0 can be written to clear the flag. table 15.2 channel select list bit 1 bit 0 analog input channels single mode scan mode ch1 ch0 a/d0 a/d1 a/d0 a/d1 0 0 an0 an4 an0 an4 1 an1 an5 an0, an1 an4, an5 1 0 an2 an6 an0 to an2 an4 to an6 1 an3 an7 an0 to an3 an4 to an7 15. a/d converter rev.4.00 mar. 27, 2008 page 547 of 882 rej09b0108-0400 15.3.3 a/d control register_0, 1 (adcr_0, adcr_1) adcr for each module controls a/d conversion starte d by an external trigger signal and selects the operating clock. bit bit name initial value r/w description 7 trge 0 r/w trigger enable enables or disables triggering of a/d conversion by adtrg or an mtu trigger. 0: a/d conversion triggering is disabled 1: a/d conversion triggering is enabled 6 5 cks1 cks0 0 0 r/w r/w clock select 1, 0 select the a/d conversion time. 00: p /32 01: p /16 10: p /8 11: p /4 when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. cks[1,0] = b'11 can be set while p 25 mhz. 4 adst 0 r/w a/d start starts or stops a/d conversion. when this bit is set to 1, a/d conversion is started. when this bit is cleared to 0, a/d conversion is stopped and the a/d converter enters the idle state. in single or single- cycle scan mode, this bit is automatically cleared to 0 when a/d conversion ends on the selected single channel. in continuous scan mode, a/d conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode, or module standby mode. 3 adcs 0 r/w a/d continuous scan selects either single-cycle sc an or continuous scan in scan mode. this bit is valid only when scan mode is selected. 0: single-cycle scan 1: continuous scan when changing the operating mode, first clear the adst bit in the a/d control registers (adcr) to 0. 15. a/d converter rev.4.00 mar. 27, 2008 page 548 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 to 0 ? all 1 r reserved these bits are always read as 1. the write value should always be 1. 15.3.4 a/d trigger select register (adtsr) the adtsr enables an a/d conversion st arted by an external trigger signal. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 2 trg1s1 trg1s0 0 0 r/w r/w ad trigger 1 select 1 and 0 enable the start of a/d conversion by a/d1 with a trigger signal. 00: a/d conversion start by external trigger pin ( adtrg ) or mtu trigger is enabled 01: a/d conversion start by external trigger pin ( adtrg ) is enabled 10: a/d conversion start by mtu trigger is enabled 11: setting prohibited when changing the operating mode, first clear the adst and trge bit in the a/d control registers (adcr) to 0. 1 0 trg0s1 trg0s0 0 0 r/w r/w ad trigger 0 select 1 and 0 enable the start of a/d conversion by a/d0 with a trigger signal. 00: a/d conversion start by external trigger pin ( adtrg ) or mtu trigger is enabled 01: a/d conversion start by external trigger pin ( adtrg ) is enabled 10: a/d conversion start by mtu trigger is enabled 11: setting prohibited when changing the operating mode, first clear the adst and trge bit in the a/d control registers (adcr) to 0. 15. a/d converter rev.4.00 mar. 27, 2008 page 549 of 882 rej09b0108-0400 15.4 operation the a/d converter operates by successive appr oximation with 10-bit re solution. it has two operating modes; single mode and scan mode. there are two kinds of scan mode: continuous mode and single-cycle mode. when changing the operating mode or analog input channel, in order to prevent incorrect operation, firs t clear the adst bit to 0 in ad cr. the adst bit can be set at the same time when the operating mode or analog input channel is changed. 15.4.1 single mode in single mode, a/d conversion is to be performed only once on the specified single channel. the operations are as follows. 1. a/d conversion is started when the adst bit in adcr is set to 1, according to software, mtu, or external trigger input. 2. when a/d conversion is completed, the re sult is transferred to the a/d data register corresponding to the channel. 3. on completion of conversion, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. 4. the adst bit remains set to 1 during a/d conversion. when a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the idle state. 15.4.2 continuous scan mode in continuous scan mode, a/d conversion is to be performed sequentially on the specified channels. the operations are as follows. 1. when the adst bit in adcr is set to 1 by software, mtu, or external trigger input, a/d conversion starts on the channel with the lo west number in the group (an0, an1, ..., an3). 2. when a/d conversion for each channel is completed, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. conversion of the first channe l in the group starts again. 4. steps 2 to 3 are repeated as long as the ads t bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops and th e a/d converter enters the idle state. 15. a/d converter rev.4.00 mar. 27, 2008 page 550 of 882 rej09b0108-0400 15.4.3 single-cycle scan mode in single-cycle scan mode , a/d conversion is to be performed once on the specified channels. operations are as follows. 1. when the adst bit in adcr is set to 1 by a software, mtu, or external trigger input, a/d conversion starts on the channel with the lo west number in the group (an0, an1, ..., an3). 2. when a/d conversion for each channel is comple ted, the result is sequentially transferred to the a/d data register corresponding to each channel. 3. when conversion of all the selected channels is completed, the adf bit in adcsr is set to 1. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. 4. after a/d conversion ends, the adst bit is automatically cleared to 0 and the a/d converter enters the idle state. when the adst bit is cleared to 0 during a/d conversion, a/d conversion stops and the a/d converter enters the idle state. 15.4.4 input signal sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit for each module. the a/d converter samples the analog input when the a/d conversion start delay time (t d ) has passed after the adst bit in adcr is set to 1, then starts conversion. figure 15.2 shows the a/d conversion timing. table 15.3 shows the a/d conversion time. as indicated in figure 15.2, the a/d conversion time (t conv ) includes t d and the input sampling time (t spl ). the length of t d varies depending on the timing of the write access to adcr. the total conversion time therefore varies within the ranges indicated in table 15.3. in scan mode, the values given in table 15.3 apply to the first conversion time. the values given in table 15.4 apply to the second and subsequent conversions. 15. a/d converter rev.4.00 mar. 27, 2008 page 551 of 882 rej09b0108-0400 p a/d converter a/d conversion a/d conversion start delay time (t d ) a/d conversion time (t conv ) analo g input samplin g time (t spl ) adst write timin g end of a/d conversion adf address adcsr write cycle internal write si g nal analo g input samplin g time idle state sample-and-hold figure 15.2 a/d conversion timing table 15.3 a/d conversio n time (single mode) cks1 = 0 cks1 = 1 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min typ max min typ max min typ max min typ max a/d conversion start delay t d 31 ? 62 15 ? 30 7 ? 14 3 ? 6 input sampling time t spl ? 256 ? ? 128 ? ? 64 ? ? 32 ? a/d conversion time t conv 1024 ? 1055 515 ? 530 259 ? 266 131 ? 134 note: all values represent the number of states for p . 15. a/d converter rev.4.00 mar. 27, 2008 page 552 of 882 rej09b0108-0400 table 15.4 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 1024 (fixed) 0 1 512 (fixed) 1 0 256 (fixed) 1 128 (fixed) 15.4.5 a/d converter activation by mtu the a/d converter can be independently activated by an a/d conversion request from the interval timer of the mtu. to activate the a/d converter by th e mtu, set the a/d trigger select register (adtsr). after this register setting has been made, the adst bit in adcr is automatically set to 1 when an a/d conversion request from the interval timer of the mtu occurs. the timing from setting of the adst bit until the start of a/d conversion is the same as when 1 is written to the adst bit by software. 15.4.6 external tr igger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to 00 or 01 in adtsr, external trigger input is enabled at the adtrg pin. a falling edge of the adtrg pin sets the adst bit to 1 in adcr, starting a/d conversion. other operations, in both single and scan modes, are the same as when the adst bit ha s been set to 1 by software. figure 15.3 shows the timing. ck adtrg external tri gg er si g nal adst a/d conversion figure 15.3 external trigger input timing 15. a/d converter rev.4.00 mar. 27, 2008 page 553 of 882 rej09b0108-0400 15.5 interrupt sources and dtc, dmac transfer requests the a/d converter generates an a/d conversion end interrupt (adi) upon the completion of a/d conversion. adi interrupt requests are enabled when the adie bit is set to 1 while the adf bit in adcsr is set to 1 after a/d conversion is comple ted. the data transfer controller (dtc) or the direct memory access controller (dmac) can be activated by an adi interrupt. having the converted data read by the dtc or the dmac in response to an adi interrupt enables continuous conversion to be achieved without imposing a load on software. when the dtc or the dmac is activated by an adi interrupt, the adf bit in adcsr is automatically cleared when data is transferred by the dtc or the dmac. table 15.5 a/d converter interrupt sources name interrupt source interrupt sour ce flag dtc activation dmac activation adi0 a/d0 conversion completed adf in adcsr_0 possible impossible adi1 a/d1 conversion completed adf in adcsr_1 possible possible 15. a/d converter rev.4.00 mar. 27, 2008 page 554 of 882 rej09b0108-0400 15.6 definitions of a/d conversion accuracy this lsi's a/d conversion accuracy definitions are given below. ? resolution the number of a/d converter digital output codes ? quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 15.4). ? offset error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'00) to b'0000000001 (h'01) (see figure 15.5). ? full-scale error the deviation of the analog input voltage valu e from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 15.5). ? nonlinearity error the error with respect to the ideal a/d convers ion characteristic between zero voltage and full- scale voltage. does not include offset error, full-scale error, or quantization error (see figure 15.5). ? absolute accuracy the deviation between the digital value and the analog input value. includes offset error, full- scale error, quantization erro r, and nonlinearity error. 15. a/d converter rev.4.00 mar. 27, 2008 page 555 of 882 rej09b0108-0400 111 110 101 100 011 010 001 000 1 1024 2 1024 1022 1024 1023 1024 fs quantization error di g ital output ideal a/d conversion characteristic analo g input volta g e figure 15.4 definitions of a/d conversion accuracy fs di g ital output ideal a/d conversion characteristic nonlinearity error analo g input volta g e offset error actual a/d conversion characteristic full-scale error figure 15.5 definitions of a/d conversion accuracy 15. a/d converter rev.4.00 mar. 27, 2008 page 556 of 882 rej09b0108-0400 15.7 usage notes 15.7.1 module standby mode setting operation of the a/d converter can be disabled or enabled using the module standby control register. the initial setting is for operation of th e a/d converter to be halted. register access is enabled by clearing module standby mode. for details, refer to section 24, power-down modes. 15.7.2 permissible si gnal source impedance this lsi's analog input is designed such that conv ersion accuracy is guarant eed for an input signal for which the signal source impedance is 1 k or less. this specification is provided to enable the a/d converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k , charging may be insufficient and it may not be possible to guarantee a/d conver sion accuracy. with a large capac itance provided externally for a/d conversion in single mode, the input impedance will essentially comprise only the internal input resistance of 10 k , and the signal source impedance is ignored. however, as a low-pass filter effect is obtained in this case, it may not be possible to follow a high speed switching analog signal (e.g., 5 mv/ s or greater) (see figure 15.6). when converting a high-speed analog signal or performing conversion in scan mode, a low-impedance buffer should be inserted. 15.7.3 influences on absolute accuracy adding capacitance results in coupling with gn d, and therefore noise in gnd may adversely affect absolute accuracy. be sure to make the connection to an electrically stable gnd such as avss. care is also required to insure that filter circu its do not interfere in the accuracy by the digital signals on the printed circuit board (i.e, acting as antennas). 20 pf 10 k c in = 20 pf sensor output impedance of up to 1 k this lsi low-pass filter c = 0.1 f sensor input a/d converter equivalent circuit figure 15.6 example of analog input circuit 15. a/d converter rev.4.00 mar. 27, 2008 page 557 of 882 rej09b0108-0400 15.7.4 range of analog power supply and other pin settings if the conditions below are not met, the reliability of the device may be adversely affected. ? analog input voltage range the voltage applied to analog input pin ann (vann) during a/d conversion should be in the range avss vann avcc. ? relationship between avcc, avss and vcc, vss the relationship between avcc, avss and vcc, vss should be avcc = vcc 0.3v and avss = vss. if the a/d converter is not used, this relationship should be avcc = vcc and avss = vss. ? setting range of avref input voltage (only for sh7145) set the avref pin input voltage as avref avcc. if the a/d converter is not used, set the avref pin as avref = avcc. 15.7.5 notes on board design in board design, digital circuitry and analog circu itry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to in ductance, adversely affecting a/d conversion values. also, digital circuitry must be isolated from the analog input signals (an0 to an7), and analog power supply (avcc) by the analog ground (a vss). also, the analog ground (av ss) should be connected at one point to a stable digital ground (vss) on the board. 15.7.6 notes on no ise countermeasures a protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the an alog input pins (an0 to an7), to avcc and avss, as shown in figure 15.7. also, the bypass capacitors connected to avcc and the filter capacitor connected to an0 to an7 must be connected to avss. if a filter capacitor is connected, the input curren ts at the analog input pins (an0 to an7) are averaged, and so an error may arise. also, when a/d conversion is perform ed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter excee ds the current input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideratio n is therefore required when deciding circuit constants. 15. a/d converter rev.4.00 mar. 27, 2008 page 558 of 882 rej09b0108-0400 avcc avref * 1 an0 to an7 avss * 1 r in * 2 100 0.1 f 0.01 f 10 f notes: values are reference values. 1. 2. r in : input impedance figure 15.7 example of analog input protection circuit table 15.6 analog pin specifications item min max unit analog input capacitance ? 20 pf permissible signal source impedance ? 1 k 16. compare match timer (cmt) timcmt0a_000220020700 rev.4.00 mar. 27, 2008 page 559 of 882 rej09b0108-0400 section 16 compare match timer (cmt) this lsi has an on-chip compare match timer (c mt) comprising two 16-bit timer channels. the cmt has 16-bit counters and can genera te interrupts at specified intervals. 16.1 features the cmt has the following features: ? four kinds of counter input clock can be selected ? one of four internal clocks (p /8, p /32, p /128, p /512) can be selected independently for each channel. ? interrupt sources ? a compare match interrupt can be requ ested independently for each channel. ? module standby mode can be set figure 16.1 shows a block diagram of the cmt. control circuit clock selection module bus control circuit clock selection cmi0 cmi1 p /8 p /32 p /128 p /512 p /8 p /32 p /128 p /512 bus interface internal bus [le g end] cmstr: compare match timer start re g ister cmcsr: compare match timer control/status re g ister cmcor: compare match timer constant re g ister cmcnt: compare match timer counter cmi: compare match interrupt comparator cmstr cmt cmcsr_0 cmcor_0 comparator cmcnt_0 cmcsr_1 cmcor_1 cmcnt_1 figure 16.1 cmt block diagram 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 560 of 882 rej09b0108-0400 16.2 register descriptions the cmt has the following registers. for details on register addresses and register states during each processing, refer to sect ion 25, list of registers. ? compare match timer start register (cmstr) ? compare match timer control/status register_0 (cmcsr_0) ? compare match timer counter_0 (cmcnt_0) ? compare match timer constant register_0 (cmcor_0) ? compare match timer control/status register_1 (cmcsr_1) ? compare match timer counter_1 (cmcnt_1) ? compare match timer constant register_1 (cmcor_1) 16.2.1 compare match tim er start register (cmstr) the compare match timer start register (cmstr) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (cmcnt). bit bit name initial value r/w description 15 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 str1 0 r/w count start 1 this bit selects whether to operate or halt compare match timer counter_1. (cmcnt_1) 0: cmcnt_1 count operation halted 1: cmcnt_1 count operation 0 str0 0 r/w count start 0 this bit selects whether to operate or halt compare match timer counter_0. (cmcnt_0) 0: cmcnt_0 count operation halted 1: cmcnt_0 count operation 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 561 of 882 rej09b0108-0400 16.2.2 compare match timer control/sta tus register_0, 1 (cmcsr_0, cmcsr_1) the compare match timer control/status register (c mcsr) is a 16-bit register that indicates the occurrence of compare matches, se ts the enable/disable status of interrupts, and establishes the clock used for incrementation. bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 cmf 0 r/(w) * compare match flag this flag indicates whether or not the cmcnt and cmcor values have matched. 0: cmcnt and cmcor values have not matched 1: cmcnt and cmcor values have matched [clearing condition] ? write 0 to cmf after reading 1 from it ? when the dtc is activated by an cmi interrupt and data is transferred with the disel bit in dtmr of dtc = 0 6 cmie 0 r/w compare match interrupt enable this bit selects whether to enable or disable a compare match interrupt (cmi) when the cmcnt and cmcor values have matched (cmf = 1). 0: compare match interrupt (cmi) disabled 1: compare match interrupt (cmi) enabled 5 to 2 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 1 0 cks1 cks0 0 0 r/w r/w these bits select the clock input to cmcnt from among the four internal clocks obtained by dividing the peripheral clock (p ). when the str bit of cmstr is set to 1, cmcnt begins incrementing with the clock selected by cks1 and cks0. 00: p /8 01: p /32 10: p /128 11: p /512 note: * only 0 can be written for flag clearing. 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 562 of 882 rej09b0108-0400 16.2.3 compare match timer counter_0, 1 (cmcnt_0, cmcnt_1) the compare match timer counter (cmcnt) is a 16-bit register used as an up-counter for generating interrupt requests. the initial value of cmcnt is h'0000. 16.2.4 compare match timer constant register_0, 1 (cmcor_0, cmcor_1) the compare match timer constant register (cmcor) is a 16-bit regi ster that sets the period for compare match with cmcnt. the initial value of cmcor is h'ffff. 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 563 of 882 rej09b0108-0400 16.3 operation 16.3.1 compare matc h counter operation when an internal clock is selected with the ck s1, cks0 bits of the cmcsr register and the str bit of cmstr is set to 1, cmcnt begins incrementing with the selected clock. when the cmcnt counter value matches that of the comp are match constant register (cmcor), the cmcnt counter is cleared to h'0000 and the cmf flag of the cmcsr register is set to 1. if the cmie bit of the cmcsr register is set to 1 at this time, a compare match interrupt (cmi) is requested. the cmcnt counter begins counting up again from h'0000. figure 16.2 shows the compare match counter operation. cmcnt value cmcor h'0000 counter cleared by cmcor compare match time figure 16.2 counter operation 16.3.2 cmcnt count timing one of four clocks (p /8, p /32, p /128, p /512) obtained by dividing the peripheral clock (p ) can be selected by the cks1 and cks0 bits of cmcsr. figure 16.3 shows the cmcnt count timing. p internal clock cmcnt input clock cmcnt n-1 n n+1 figure 16.3 count timing 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 564 of 882 rej09b0108-0400 16.4 interrupts 16.4.1 interrupt sources and dtc activation the cmt has a compare match inte rrupt for each channel, with independent vector addresses allocated to each of them. the corresponding interrupt request is output when interrupt request flag cmf is set to 1 and interrupt enable bit cmie has also been set to 1. when activating cpu interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. see section 6, interrupt controller (intc), for details. the data transfer controller (dtc) can be activate d by an interrupt request. in this case, the priority between channels is fixed. see section 8, data transfer controller (dtc), for details. 16.4.2 compare match flag set timing the cmf bit of the cmcsr register is set to 1 by the compare match signal generated when the cmcor register and the cmcnt counter match. the compare match signal is generated upon the final state of the match (timing at which the cmcnt counter matching count value is updated). consequently, after the cmcor register and the cmcnt counter match, a compare match signal will not be generated until a cmcnt counter input clock occurs. figure 16.4 shows the cmf bit set timing. cmcnt input clock cmcnt cmcor n0 n compare match si g nal cmf cmi p figure 16.4 cmf set timing 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 565 of 882 rej09b0108-0400 16.4.3 compare match flag clear timing the cmf bit of the cmcsr register is cleared by writing a 0 to it after reading a 1 or the clearing signal after the dtc transfer. figure 16.5 shows the timing when the cmf bit is cleared by the cpu. t1 t2 cmcsr write cycle p cmf figure 16.5 timing of cmf clear by cpu 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 566 of 882 rej09b0108-0400 16.5 usage notes 16.5.1 contention between cm cnt write and compare match if a compare match signal is generated during the t2 state of the cmcnt co unter write cycle, the cmcnt counter clear has priority, so the write to the cmcnt counter is not performed. figure 16.6 shows the timing. p t1 t2 address cmcnt internal write si g nal cmcnt n h' 0000 compare match si g nal cmcnt write cycle figure 16.6 cmcnt write an d compare match contention 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 567 of 882 rej09b0108-0400 16.5.2 contention betw een cmcnt word write an d counter incrementation if an increment occurs during the t2 state of th e cmcnt counter word wr ite cycle, the counter write has priority, so no increment occurs. figure 16.7 shows the timing. p t1 t2 address cmcnt internal write si g nal cmcnt nm cmcnt write data cmcnt input clock cmcnt write cycle figure 16.7 cmcnt word wr ite and increment contention 16. compare match timer (cmt) rev.4.00 mar. 27, 2008 page 568 of 882 rej09b0108-0400 16.5.3 contention between cmcnt by te write and counter incrementation if an increment occurs during the t2 state of th e cmcnt byte write cycle, the counter write has priority, so no increment of the write data resu lts on the side on which the write was performed. the byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. figure 16.8 shows the timing when an increm ent occurs during the t2 state of the cmcnt (upper byte) write cycle. p t1 t2 address cmcnt (upper byte) internal write si g nal cmcnt (upper byte) n m cmcnt (lower byte) xx cmcnt write data cmcnt input clock cmcnt write cycle figure 16.8 cmcnt byte wr ite and increment contention 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 569 of 882 rej09b0108-0400 section 17 pin function controller (pfc) the pin function controller (pfc) is composed of registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. tables 17.1 to 17.12 list the multiplexed pins of this lsi. tables 17.13 and 17.14 list the pin functions in each operating mode. table 17.1 sh7144 multiplexed pins (port a) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) a pa0 i/o (port) rxd0 input (sci) ? ? pa1 i/o (port) txd0 output (sci) ? ? pa2 i/o (port) sck0 i/o (sci) dreq0 input (dmac) irq0 input (intc) pa3 i/o (port) rxd1 input (sci) ? ? pa4 i/o (port) txd1 output (sci) ? ? pa5 i/o (port) sck1 i/o (sci) dreq1 input (dmac) irq1 input (intc) pa6 i/o (port) tclka input (mtu) cs2 output (bsc) ? pa7 i/o (port) tclkb input (mtu) cs3 output (bsc) ? pa8 i/o (port) tclkc input (mtu) irq2 input (intc) ? pa9 i/o (port) tclkd input (mtu) irq3 input (intc) ? pa10 i/o (port) cs0 output (bsc) ? ? pa11 i/o (port) cs1 output (bsc) ? ? pa12 i/o (port) wrl output (bsc) ? ? pa13 i/o (port) wrh output (bsc) ? ? pa14 i/o (port) rd output (bsc) ? ? pa15 i/o (port) ck output (cpg) ? ? 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 570 of 882 rej09b0108-0400 table 17.2 sh7144 multiplexed pins (port b) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) function 5 (related module) b pb0 i/o (port) a16 output (bsc) ? ? ? pb1 i/o (port) a17 output (bsc) ? ? ? pb2 i/o (port) irq0 input (intc) poe0 input (port) ? scl0 i/o (iic) pb3 i/o (port) irq1 input (intc) poe1 input (port) ? sda0 i/o (iic) pb4 i/o (port) irq2 input (intc) poe2 input (port) cs6 output (bsc) * ? pb5 i/o (port) irq3 input (intc) poe3 input (port) cs7 output (bsc) * ? pb6 i/o (port) irq4 input (intc) a18 output (bsc) back output (bsc) ? pb7 i/o (port) irq5 input (intc) a19 output (bsc) breq input (bsc) ? pb8 i/o (port) irq6 input (intc) a20 output (bsc) wait input (bsc) ? pb9 i/o (port) irq7 input (intc) a21 output (bsc) adtrg input (a/d) ? note: ? masked rom version and rom less version only table 17.3 sh7144 multiplexed pins (port c) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) c pc0 i/o (port) a0 output (bsc) ? ? pc1 i/o (port) a1 output (bsc) ? ? pc2 i/o (port) a2 output (bsc) ? ? pc3 i/o (port) a3 output (bsc) ? ? pc4 i/o (port) a4 output (bsc) ? ? pc5 i/o (port) a5 output (bsc) ? ? pc6 i/o (port) a6 output (bsc) ? ? pc7 i/o (port) a7 output (bsc) ? ? pc8 i/o (port) a8 output (bsc) ? ? pc9 i/o (port) a9 output (bsc) ? ? pc10 i/o (port) a10 output (bsc) ? ? pc11 i/o (port) a11 output (bsc) ? ? pc12 i/o (port) a12 output (bsc) ? ? pc13 i/o (port) a13 output (bsc) ? ? pc14 i/o (port) a14 output (bsc) ? ? pc15 i/o (port) a15 output (bsc) ? ? 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 571 of 882 rej09b0108-0400 table 17.4 sh7144 multiplexed pins (port d) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) d pd0 i/o (port) d0 i/o (bsc) ? ? pd1 i/o (port) d1 i/o (bsc) ? ? pd2 i/o (port) d2 i/o (bsc) ? ? pd3 i/o (port) d3 i/o (bsc) ? ? pd4 i/o (port) d4 i/o (bsc) ? ? pd5 i/o (port) d5 i/o (bsc) ? ? pd6 i/o (port) d6 i/o (bsc) ? ? pd7 i/o (port) d7 i/o (bsc) ? ? pd8 i/o (port) d8 i/o (bsc) audata0 i/o (aud) * ? pd9 i/o (port) d9 i/o (bsc) audata1 i/o (aud) * ? pd10 i/o (port) d10 i/o (bsc) audata2 i/o (aud) * ? pd11 i/o (port) d11 i/o (bsc) audata3 i/o (aud) * ? pd12 i/o (port) d12 i/o (bsc) audrst input (aud) * ? pd13 i/o (port) d13 i/o (bsc) audmd input (aud) * ? pd14 i/o (port) d14 i/o (bsc) audck i/o (aud) * ? pd15 i/o (port) d15 i/o (bsc) audsync i/o (aud) * ? note: * f-ztat version only 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 572 of 882 rej09b0108-0400 table 17.5 sh7144 multiplexed pins (port e) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) e pe0 i/o port tioc0a i/o (mtu) dreq0 input (dmac) tms input (h-udi) * pe1 i/o port tioc0b i/o (mtu) drak0 output (dmac) trst input (h-udi) * pe2 i/o port tioc0c i/o (mtu) dreq1 input (dmac) tdi input (h-udi) * pe3 i/o port tioc0d i/o (mtu) drak1 output (dmac) tdo output (h-udi) * pe4 i/o port tioc1a i/o (mtu) rxd3 input (sci) tck input (h-udi) * pe5 i/o port tioc1b i/o (mtu) txd3 output (sci) ? pe6 i/o port tioc2a i/o (mtu) sck3 i/o (sci) ? pe7 i/o port tioc2b i/o (mtu) rxd2 input (sci) ? pe8 i/o port tioc3a i/o (mtu) sck2 i/o (sci) ? pe9 i/o port tioc3b i/o (mtu) ? sck3 i/o (sci) pe10 i/o port tioc3c i/o (mtu) txd2 output (sci) ? pe11 i/o port tioc3d i/o (mtu) ? rxd3 input (sci) pe12 i/o port tioc4a i/o (mtu) ? txd3 output (sci) pe13 i/o port tioc4b i/o (mtu) mres input (intc) ? pe14 i/o port tioc4c i/o (mtu) dack0 output (dmac) ? pe15 i/o port tioc4d i/o (mtu) dack1 output (dmac) irqout output (intc) note: * f-ztat version only table 17.6 sh7144 multiplexed pins (port f) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) f pf0 input (port) an0 input (a/d) ? ? pf1 input (port) an1 input (a/d) ? ? pf2input (port) an2 input (a/d) ? ? pf3 input (port) an3 input (a/d) ? ? pf4 input (port) an4 input (a/d) ? ? pf5 input (port) an5 input (a/d) ? ? pf6 input (port) an6 input (a/d) ? ? pf7 input (port) an7 input (a/d) ? ? 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 573 of 882 rej09b0108-0400 table 17.7 sh7145 multiplexed pins (port a) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) a pa0 i/o (port) rxd0 input (sci) ? ? pa1 i/o (port) txd0 output (sci) ? ? pa2 i/o (port) sck0 i/o (sci) dreq0 input (dmac) irq0 input (intc) pa3 i/o (port) rxd1 input (sci) ? ? pa4 i/o (port) txd1 output (sci) ? ? pa5 i/o (port) sck1 i/o (sci) dreq1 input (dmac) irq1 input (intc) pa6 i/o (port) tclka input (mtu) cs2 output (bsc) ? pa7 i/o (port) tclkb input (mtu) cs3 output (bsc) ? pa8 i/o (port) tclkc input (mtu) irq2 input (intc) ? pa9 i/o (port) tclkd input (mtu) irq3 input (intc) ? pa10 i/o (port) cs0 output (bsc) ? ? pa11 i/o (port) cs1 output (bsc) ? ? pa12 i/o (port) wrl output (bsc) ? ? pa13 i/o (port) wrh output (bsc) ? ? pa14 i/o (port) rd output (bsc) ? ? pa15 i/o (port) ck output (cpg) ? ? pa16 i/o (port) ? ? audsync i/o (aud) * 1 pa17 i/o (port) wait input (bsc) ? ? pa18 i/o (port) breq input (bsc) drak0 output (dmac) ? pa19 i/o (port) back output (bsc) drak1 output (dmac) ? pa20 i/o (port) cs4 output (bsc) * 2 ? ? pa21 i/o (port) cs5 output (bsc) * 2 ? ? pa22 i/o (port) wrhl output (bsc) ? ? pa23 i/o (port) wrhh output (bsc) ? ? notes: 1. f-ztat version only 2. masked rom version and rom less version only 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 574 of 882 rej09b0108-0400 table 17.8 sh7145 multiplexed pins (port b) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) function 5 (related module) b pb0 i/o (port) a16 output (bsc) ? ? ? pb1 i/o (port) a17 output (bsc) ? ? ? pb2 i/o (port) irq0 input (intc) poe0 input (port) ? scl0 i/o (iic) pb3 i/o (port) irq1 input (intc) poe1 input (port) ? sda0 i/o (iic) pb4 i/o (port) irq2 input (intc) poe2 input (port) cs6 output (bsc) * ? pb5 i/o (port) irq3 input (intc) poe3 input (port) cs7 output (bsc) * ? pb6 i/o (port) irq4 input (intc) a18 output (bsc) back output (bsc) ? pb7 i/o (port) irq5 input (intc) a19 output (bsc) breq input (bsc) ? pb8 i/o (port) irq6 input (intc) a20 output (bsc) wait input (bsc) ? pb9 i/o (port) irq7 input (intc) a21 output (bsc) adtrg input (a/d) ? note ? masked rom version and rom less version only table 17.9 sh7145 multiplexed pins (port c) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) c pc0 i/o (port) a0 output (bsc) ? ? pc1 i/o (port) a1 output (bsc) ? ? pc2 i/o (port) a2 output (bsc) ? ? pc3 i/o (port) a3 output (bsc) ? ? pc4 i/o (port) a4 output (bsc) ? ? pc5 i/o (port) a5 output (bsc) ? ? pc6 i/o (port) a6 output (bsc) ? ? pc7 i/o (port) a7 output (bsc) ? ? pc8 i/o (port) a8 output (bsc) ? ? pc9 i/o (port) a9 output (bsc) ? ? pc10 i/o (port) a10 output (bsc) ? ? pc11 i/o (port) a11 output (bsc) ? ? pc12 i/o (port) a12 output (bsc) ? ? pc13 i/o (port) a13 output (bsc) ? ? pc14 i/o (port) a14 output (bsc) ? ? pc15 i/o (port) a15 output (bsc) ? ? 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 575 of 882 rej09b0108-0400 table 17.10 sh7145 multiplexed pins (port d) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) d pd0 i/o (port) d0 i/o (bsc) ? ? pd1 i/o (port) d1 i/o (bsc) ? ? pd2 i/o (port) d2 i/o (bsc) ? ? pd3 i/o (port) d3 i/o (bsc) ? ? pd4 i/o (port) d4 i/o (bsc) ? ? pd5 i/o (port) d5 i/o (bsc) ? ? pd6 i/o (port) d6 i/o (bsc) ? ? pd7 i/o (port) d7 i/o (bsc) ? ? pd8 i/o (port) d8 i/o (bsc) ? ? pd9 i/o (port) d9 i/o (bsc) ? ? pd10 i/o (port) d10 i/o (bsc) ? ? pd11 i/o (port) d11 i/o (bsc) ? ? pd12 i/o (port) d12 i/o (bsc) ? ? pd13 i/o (port) d13 i/o (bsc) ? ? pd14 i/o (port) d14 i/o (bsc) ? ? pd15 i/o (port) d15 i/o (bsc) ? ? pd16 i/o (port) d16 i/o (bsc) irq0 input (intc) audata0 i/o (aud) * pd17 i/o (port) d17 i/o (bsc) irq1 input (intc) audata1 i/o (aud) * pd18 i/o (port) d18 i/o (bsc) irq2 input (intc) audata2 i/o (aud) * pd19 i/o (port) d19 i/o (bsc) irq3 input (intc) audata3 i/o (aud) * pd20 i/o (port) d20 i/o (bsc) irq4 input (intc) audrst input (aud) * pd21 i/o (port) d21 i/o (bsc) irq5 input (intc) audmd input (aud) * pd22 i/o (port) d22 i/o (bsc) irq6 input (intc) audck i/o (aud) * pd23 i/o (port) d23 i/o (bsc) irq7 input (intc) audsync i/o (aud) * pd24 i/o (port) d24 i/o (bsc) dreq0 input (dmac) ? pd25 i/o (port) d25 i/o (bsc) dreq1 input (dmac) ? pd26 i/o (port) d26 i/o (bsc) dack0 output (dmac) ? pd27 i/o (port) d27 i/o (bsc) dack1 output (dmac) ? pd28 i/o (port) d28 i/o (bsc) cs2 output (bsc) ? pd29 i/o (port) d29 i/o (bsc) cs3 output (bsc) ? pd30 i/o (port) d30 i/o (bsc) irqout output (intc) ? pd31 i/o (port) d31 i/o (bsc) adtrg input (a/d) ? note: * f-ztat version only 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 576 of 882 rej09b0108-0400 table 17.11 sh7145 multiplexed pins (port e) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) e pe0 i/o (port) tioc0a i/o (mtu) dreq0 input (dmac) audck i/o (aud) * pe1 i/o (port) tioc0b i/o (mtu) dack0 output (dmac) audmd input (aud) * pe2 i/o (port) tioc0c i/o (mtu) dreq1 input (dmac) audrst input (aud) * pe3 i/o (port) tioc0d i/o (mtu) dack1 output (dmac) audata3 i/o (aud) * pe4 i/o (port) tioc1a i/o (mtu) rxd3 input (sci) audata2 i/o (aud) * pe5 i/o (port) tioc1b i/o (mtu) txd3 output (sci) audata1 i/o (aud) * pe6 i/o (port) tioc2a i/o (mtu) sck3 i/o (sci) audata0 i/o (aud) * pe7 i/o (port) tioc2b i/o (mtu) rxd2 input (sci) ? pe8 i/o (port) tioc3a i/o (mtu) sck2 i/o (sci) tms input (h-udi) * pe9 i/o (port) tioc3b i/o (mtu) trst input (h-udi) * sck3 i/o (sci) pe10 i/o (port) tioc3c i/o (mtu) txd2 output (sci) tdi input (h-udi) * pe11 i/o (port) tioc3d i/o (mtu) tdo output (h-udi) * rxd3 input (sci) pe12 i/o (port) tioc4a i/o (mtu) tck input (h-udi) * txd3 output (sci) pe13 i/o (port) tioc4b i/o (mtu) mres input (intc) ? pe14 i/o (port) tioc4c i/o (mtu) dack0 output (dmac) ? pe15 i/o (port) tioc4d i/o (mtu) dack1 output (dmac) irqout output (intc) note: * f-ztat version only table 17.12 sh7145 multiplexed pins (port f) port function 1 (related module) function 2 (related module) function 3 (related module) function 4 (related module) f pf0 input (port) an0 input (a/d) ? ? pf1 input (port) an1 input (a/d) ? ? pf2 input (port) an2 input (a/d) ? ? pf3 input (port) an3 input (a/d) ? ? pf4 input (port) an4 input (a/d) ? ? pf5 input (port) an5 input (a/d) ? ? pf6 input (port) an6 input (a/d) ? ? pf7 input (port) an7 input (a/d) ? ? 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 577 of 882 rej09b0108-0400 table 17.13 sh7144 pin functions in each mode (1) pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 21, 37, 65, 103 vcc vcc vcc vcc 3, 23, 39, 55, 61, 71, 90, 101, 109 vss vss vss vss 100 avcc avcc avcc avcc 97 avss avss avss avss 80 pllvcc pllvcc pllvcc pllvcc 81 pllcap pllcap pllcap pllcap 82 pllvss pllvss pllvss pllvss 1 pe14 pe14/tioc4c/dack0 pe14 pe14/tioc4c/dack0 2 pe15 pe15/tioc4d/dack1/ irqout pe15 pe15/tioc4d/dack1/ irqout 4 a0 pc0/a0 a0 pc0/a0 5 a1 pc1/a1 a1 pc1/a1 6 a2 pc2/a2 a2 pc2/a2 7 a3 pc3/a3 a3 pc3/a3 8 a4 pc4/a4 a4 pc4/a4 9 a5 pc5/a5 a5 pc5/a5 10 a6 pc6/a6 a6 pc6/a6 11 a7 pc7/a7 a7 pc7/a7 12 a8 pc8/a8 a8 pc8/a8 13 a9 pc9/a9 a9 pc9/a9 14 a10 pc10/a10 a10 pc10/a10 15 a11 pc11/a11 a11 pc11/a11 16 a12 pc12/a12 a12 pc12/a12 17 a13 pc13/a13 a13 pc13/a13 18 a14 pc14/a14 a14 pc14/a14 19 a15 pc15/a15 a15 pc15/a15 20 a16 pb0/a16 a16 pb0/a16 22 a17 pb1/a17 a17 pb1/a17 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 578 of 882 rej09b0108-0400 pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 24 pb2 pb2/ irq0 / poe0 /scl0 pb2 pb2/ irq0 / poe0 /scl0 25 pb3 pb3/ irq1 / poe1 /sda0 pb3 pb3/ irq1 / poe1 /sda0 26 pb4 pb4/ irq2 / poe2 / cs6 * 3 pb4 pb4/ irq2 / poe2 / cs6 * 3 27 asebrkak * 1 asebrkak * 1 asebrkak * 1 asebrkak * 1 28 pb5 pb5/ irq3 / poe3 / cs7 * 3 pb5 pb5/ irq3 / poe3 / cs7 * 3 29 pb6 pb6/ irq4 /a18/ back pb6 pb6/ irq4 /a18/ back 30 pb7 pb7/ irq5 /a19/ breq pb7 pb7/ irq5 /a19/ breq 31 pb8 pb8/ irq6 /a20/ wait pb8 pb8/ irq6 /a20/ wait 32 pb9 pb9/ irq7 /a21/ adtrg pb9 pb9/ irq7 /a21/ adtrg 33 dbgmd * 1 dbgmd * 1 dbgmd * 1 dbgmd * 1 34 rd pa14/ rd rd pa14/ rd 35 wdtovf wdtovf wdtovf wdtovf 36 wrh pa13/ wrh wrh pa13/ wrh 38 wrl pa12/ wrl wrl pa12/ wrl 40 cs1 pa11/ cs1 cs1 pa11/ cs1 41 cs0 pa10/ cs0 cs0 pa10/ cs0 42 pa9 pa9/tclkd/ irq3 pa9 pa9/tclkd/ irq3 43 pa8 pa8/tclkc/ irq2 pa8 pa8/tclkc/ irq2 44 pa7 pa7/tclkb/ cs3 pa7 pa7/tclkb/ cs3 45 pa6 pa6/tclka/ cs2 pa6 pa6/tclka/ cs2 46 pa5 pa5/sck1/ dreq1 / irq1 pa5 pa5/sck1/ dreq1 / irq1 47 pa4 pa4/txd1 pa4 pa4/txd1 48 pa3 pa3/rxd1 pa3 pa3/rxd1 49 pa2 pa2/sck0/ dreq0 / irq0 pa2 pa2/sck0/ dreq0 / irq0 50 pa1 pa1/txd0 pa1 pa1/txd0 51 pa0 pa0/rxd0 pa0 pa0/rxd0 52 pd15 pd15/d15/ audsync * 1 d15 pd15/d15/ audsync * 1 53 pd14 pd14/d14/audck * 1 d14 pd14/d14/audck * 1 54 pd13 pd13/d13/audmd * 1 d13 pd13/d13/audmd * 1 56 pd12 pd12/d12/ audrst * 1 d12 pd12/d12/ audrst * 1 57 pd11 pd11/d11/audata3 * 1 d11 pd11/d11/audata3 * 1 58 pd10 pd10/d10/audata2 * 1 d10 pd10/d10/audata2 * 1 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 579 of 882 rej09b0108-0400 pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 59 pd9 pd9/d9/audata1 * 1 d9 pd9/d9/audata1 * 1 60 pd8 pd8/d8/audata0 * 1 d8 pd8/d8/audata0 * 1 62 d7 pd7/d7 d7 pd7/d7 63 d6 pd6/d6 d6 pd6/d6 64 d5 pd5/d5 d5 pd5/d5 66 d4 pd4/d4 d4 pd4/d4 67 d3 pd3/d3 d3 pd3/d3 68 d2 pd2/d2 d2 pd2/d2 69 d1 pd1/d1 d1 pd1/d1 70 d0 pd0/d0 d0 pd0/d0 72 xtal xtal xtal xtal 73 md3 md3 md3 md3 74 extal extal extal extal 75 md2 md2 md2 md2 76 nmi nmi nmi nmi 77 fwp * 1 fwp * 1 fwp * 1 fwp * 1 78 md1 md1 md1 md1 79 md0 md0 md0 md0 83 ck pa15/ck ck pa15/ck 84 res res res res 85 pe0/(tms * 1 * 2 ) pe0/tioc0a/ dreq0 pe0/(tms * 1 * 2 ) pe0/tioc0a/ dreq0 86 pe1/( trst * 1 * 2 ) pe1/tioc0b/drak0 pe1/( trst * 1 * 2 ) pe1/tioc0b/drak0 87 pe2/(tdi * 1 * 2 ) pe2/tioc0c/ dreq1 pe2/(tdi * 1 * 2 ) pe2/tioc0c/ dreq1 88 pe3/(tdo * 1 * 2 ) pe3/tioc0d/drak1 pe3/(tdo * 1 * 2 ) pe3/tioc0d/drak1 89 pe4/(tck * 1 * 2 ) pe4/tioc1a/rxd3 pe4/(tck * 1 * 2 ) pe4/tioc1a/rxd3 91 pf0/an0 pf0/an0 pf0/an0 pf0/an0 92 pf1/an1 pf1/an1 pf1/an1 pf1/an1 93 pf2/an2 pf2/an2 pf2/an2 pf2/an2 94 pf3/an3 pf3/an3 pf3/an3 pf3/an3 95 pf4/an4 pf4/an4 pf4/an4 pf4/an4 96 pf5/an5 pf5/an5 pf5/an5 pf5/an5 98 pf6/an6 pf6/an6 pf6/an6 pf6/an6 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 580 of 882 rej09b0108-0400 pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 99 pf7/an7 pf7/an7 pf7/an7 pf7/an7 102 pe5 pe5/tioc1b/txd3 pe5 pe5/tioc1b/txd3 104 pe6 pe6/tioc2a/sck3 pe6 pe6/tioc2a/sck3 105 pe7 pe7/tioc2b/rxd2 pe7 pe7/tioc2b/rxd2 106 pe8 pe8/tioc3a/ sck2 pe8 pe8/tioc3a/sck2 107 pe9 pe9/tioc3b/ sck3 pe9 pe9/tioc3b/sck3 108 pe10 pe10/tioc3c/txd2 pe10 pe10/tioc3c/txd2 110 pe11 pe11/tioc3d/rxd3 pe11 pe11/tioc3d/rxd3 111 pe12 pe12/tioc4a/txd3 pe12 pe12/tioc4a/txd3 112 pe13 pe13/tioc4b/ mres pe13 pe13/tioc4b/ mres notes: 1. f-ztat version only 2. fixed to tms, trst, tdi, tdo, and tck when using the e10a (in dbgmd = high). 3. masked rom version and rom less version only 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 581 of 882 rej09b0108-0400 table 17.13 sh7144 pin functions in each mode (2) pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 21, 37, 65, 103 vcc vcc vcc vcc 3, 23, 39, 55, 61, 71, 90, 101, 109 vss vss vss vss 100 avcc avcc avcc avcc 97 avss avss avss avss 80 pllvcc pllvcc pllvcc pllvcc 81 pllcap pllcap pllcap pllcap 82 pllvss pllvss pllvss pllvss 1 pe14 pe14/tioc4c/dack0 pe14 pe14/tioc4c/dack0 2 pe15 pe15/tioc4d/dack1/ irqout pe15 pe15/tioc4d/dack1/ irqout 4 pc0 pc0/a0 pc0 pc0/a0 5 pc1 pc1/a1 pc1 pc1/a1 6 pc2 pc2/a2 pc2 pc2/a2 7 pc3 pc3/a3 pc3 pc3/a3 8 pc4 pc4/a4 pc4 pc4/a4 9 pc5 pc5/a5 pc5 pc5/a5 10 pc6 pc6/a6 pc6 pc6/a6 11 pc7 pc7/a7 pc7 pc7/a7 12 pc8 pc8/a8 pc8 pc8/a8 13 pc9 pc9/a9 pc9 pc9/a9 14 pc10 pc10/a10 pc10 pc10/a10 15 pc11 pc11/a11 pc11 pc11/a11 16 pc12 pc12/a12 pc12 pc12/a12 17 pc13 pc13/a13 pc13 pc13/a13 18 pc14 pc14/a14 pc14 pc14/a14 19 pc15 pc15/a15 pc15 pc15/a15 20 pb0 pb0/a16 pb0 pb0/a16 22 pb1 pb1/a17 pb1 pb1/a17 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 582 of 882 rej09b0108-0400 pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 24 pb2 pb2/ irq0 / poe0 /scl0 pb2 pb2/ irq0 / poe0 /scl0 25 pb3 pb3/ irq1 / poe1 /sda0 pb3 pb3/ irq1 / poe1 /sda0 26 pb4 pb4/ irq2 / poe2 / cs6 * 3 pb4 pb4/ irq2 / poe2 / cs6 * 3 27 asebrkak * 1 asebrkak * 1 asebrkak * 1 asebrkak * 1 28 pb5 pb5/ irq3 / poe3 / cs7 * 3 pb5 pb5/ irq3 / poe3 / cs7 * 3 29 pb6 pb6/ irq4 /a18/ back pb6 pb6/ irq4 /a18/ back 30 pb7 pb7/ irq5 /a19/ breq pb7 pb7/ irq5 /a19/ breq 31 pb8 pb8/ irq6 /a20/ wait pb8 pb8/ irq6 /a20/ wait 32 pb9 pb9/ irq7 /a21/ adtrg pb9 pb9/ irq7 /a21/ adtrg 33 dbgmd * 1 dbgmd * 1 dbgmd * 1 dbgmd * 1 34 pa14 pa14/ rd pa14 pa14/ rd 35 wdtovf wdtovf wdtovf wdtovf 36 pa13 pa13/ wrh pa13 pa13/ wrh 38 pa12 pa12/ wrl pa12 pa12/ wrl 40 pa11 pa11/ cs1 pa11 pa11/ cs1 41 pa10 pa10/ cs0 pa10 pa10/ cs0 42 pa9 pa9/tclkd/ irq3 pa9 pa9/tclkd/ irq3 43 pa8 pa8/tclkc/ irq2 pa8 pa8/tclkc/ irq2 44 pa7 pa7/tclkb/ cs3 pa7 pa7/tclkb/ cs3 45 pa6 pa6/tclka/ cs2 pa6 pa6/tclka/ cs2 46 pa5 pa5/sck1/ dreq1 / irq1 pa5 pa5/sck1/ dreq1 / irq1 47 pa4 pa4/txd1 pa4 pa4/txd1 48 pa3 pa3/rxd1 pa3 pa3/rxd1 49 pa2 pa2/sck0/ dreq0 / irq0 pa2 pa2/sck0/ dreq0 / irq0 50 pa1 pa1/txd0 pa1 pa1/txd0 51 pa0 pa0/rxd0 pa0 pa0/rxd0 52 pd15 pd15/d15/ audsync * 1 pd15 pd15/d15/ audsync * 1 53 pd14 pd14/d14/audack * 1 pd14 pd14/d14/audack * 1 54 pd13 pd13/d13/audmd * 1 pd13 pd13/d13/audmd * 1 56 pd12 pd12/d12/ audrst * 1 pd12 pd12/d12/ audrst * 1 57 pd11 pd11/d11/audata3 * 1 pd11 pd11/d11/audata3 * 1 58 pd10 pd10/d10/audata2 * 1 pd10 pd10/d10/audata2 * 1 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 583 of 882 rej09b0108-0400 pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 59 pd9 pd9/d9/audata1 * 1 pd9 pd9/d9/audata1 * 1 60 pd8 pd8/d8/audata0 * 1 pd8 pd8/d8/audata0 * 1 62 pd7 pd7/d7 pd7 pd7/d7 63 pd6 pd6/d6 pd6 pd6/d6 64 pd5 pd5/d5 pd5 pd5/d5 66 pd4 pd4/d4 pd4 pd4/d4 67 pd3 pd3/d3 pd3 pd3/d3 68 pd2 pd2/d2 pd2 pd2/d2 69 pd1 pd1/d1 pd1 pd1/d1 70 pd0 pd0/d0 pd0 pd0/d0 72 xtal xtal xtal xtal 73 md3 md3 md3 md3 74 extal extal extal extal 75 md2 md2 md2 md2 76 nmi nmi nmi nmi 77 fwp * 1 fwp * 1 fwp * 1 fwp * 1 78 md1 md1 md1 md1 79 md0 md0 md0 md0 83 ck pa15/ck pa15 pa15/ck 84 res res res res 85 pe0/(tms * 1 * 2 ) pe0/tioc0a/ dreq0 pe0/(tms * 1 * 2 ) pe0/tioc0a/ dreq0 86 pe1/( trst * 1 * 2 ) pe1/tioc0b/drak0 pe1/( trst * 1 * 2 ) pe1/tioc0b/drak0 87 pe2/(tdi * 1 * 2 ) pe2/tioc0c/ dreq1 pe2/(tdi * 1 * 2 ) pe2/tioc0c/ dreq1 88 pe3/(tdo * 1 * 2 ) pe3/tioc0d/drak1 pe3/(tdo * 1 * 2 ) pe3/tioc0d/drak1 89 pe4/(tck * 1 * 2 ) pe4/tioc1a/rxd3 pe4/(tck * 1 * 2 ) pe4/tioc1a/rxd3 91 pf0/an0 pf0/an0 pf0/an0 pf0/an0 92 pf1/an1 pf1/an1 pf1/an1 pf1/an1 93 pf2/an2 pf2/an2 pf2/an2 pf2/an2 94 pf3/an3 pf3/an3 pf3/an3 pf3/an3 95 pf4/an4 pf4/an4 pf4/an4 pf4/an4 96 pf5/an5 pf5/an5 pf5/an5 pf5/an5 98 pf6/an6 pf6/an6 pf6/an6 pf6/an6 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 584 of 882 rej09b0108-0400 pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7144 initial function pfc selected function possibilities initial function pfc selected function possibilities 99 pf7/an7 pf7/an7 pf7/an7 pf7/an7 102 pe5 pe5/tioc1b/txd3 pe5 pe5/tioc1b/txd3 104 pe6 pe6/tioc2a/sck3 pe6 pe6/tioc2a/sck3 105 pe7 pe7/tioc2b/rxd2 pe7 pe7/tioc2b/rxd2 106 pe8 pe8/tioc3a/ sck2 pe8 pe8/tioc3a/sck2 107 pe9 pe9/tioc3b/ sck3 pe9 pe9/tioc3b/sck3 108 pe10 pe10/tioc3c/txd2 pe10 pe10/tioc3c/txd2 110 pe11 pe11/tioc3d/rxd3 pe11 pe11/tioc3d/rxd3 111 pe12 pe12/tioc4a/txd3 pe12 pe12/tioc4a/txd3 112 pe13 pe13/tioc4b/ mres pe13 pe13/tioc4b/ mres notes: 1. f-ztat version only 2. fixed to tms, trst , tdi, tdo, and tck when using the e10a (in dbgmd = high). 3. masked rom version and rom less version only 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 585 of 882 rej09b0108-0400 table 17.14 sh7145 pin functions in each mode (1) pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 12, 26, 40, 63, 77, 85, 112, 135 vcc vcc vcc vcc 6, 14, 28, 55, 61, 71, 79, 87, 93, 117, 129, 141 vss vss vss vss 128 avcc avcc avcc avcc 127 avref avref avref avref 124 avss avss avss avss 104 pllvcc pllvcc pllvcc pllvcc 105 pllcap pllcap pllcap pllcap 106 pllvss pllvss pllvss pllvss 1 pa23 pa23/ wrhh wrhh pa23/ wrhh 2 pe14 pe14/tioc4c/dack0 pe14 pe14/tioc4c/dack0 3 pa22 pa22/ wrhl wrhl pa22/ wrhl 4 pa21 pa21/ cs5 * 3 pa21 pa21/ cs5 * 3 5 pe15 pe15/tioc4d/dack1/ irqout pe15 pe15/tioc4d/dack1/ irqout 7 a0 pc0/a0 a0 pc0/a0 8 a1 pc1/a1 a1 pc1/a1 9 a2 pc2/a2 a2 pc2/a2 10 a3 pc3/a3 a3 pc3/a3 11 a4 pc4/a4 a4 pc4/a4 13 a5 pc5/a5 a5 pc5/a5 15 a6 pc6/a6 a6 pc6/a6 16 a7 pc7/a7 a7 pc7/a7 17 a8 pc8/a8 a8 pc8/a8 18 a9 pc9/a9 a9 pc9/a9 19 a10 pc10/a10 a10 pc10/a10 20 a11 pc11/a11 a11 pc11/a11 21 a12 pc12/a12 a12 pc12/a12 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 586 of 882 rej09b0108-0400 pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 22 a13 pc13/a13 a13 pc13/a13 23 a14 pc14/a14 a14 pc14/a14 24 a15 pc15/a15 a15 pc15/a15 25 a16 pb0/a16 a16 pb0/a16 27 a17 pb1/a17 a17 pb1/a17 29 pa20 pa20/ cs4 * 3 pa20 pa20/ cs4 * 3 30 pa19 pa19/ back /drak1 pa19 pa19/ back /drak1 31 pb2 pb2/ irq0 / poe0 /scl0 pb2 pb2/ irq0 / poe0 /scl0 32 pb3 pb3/ irq1 / poe1 /sda0 pb3 pb3/ irq1 / poe1 /sda0 33 pa18 pa18/ breq /drak0 pa18 pa18/ breq /drak0 34 pb4 pb4/ irq2 / poe2 / cs6 * 3 pb4 pb4/ irq2 / poe2 / cs6 * 3 35 asebrkak * 1 asebrkak * 1 asebrkak * 1 asebrkak * 1 36 pb5 pb5/ irq3 / poe3 / cs7 * 3 pb5 pb5/ irq3 / poe3 / cs7 * 3 37 pb6 pb6/ irq4 /a18/ back pb6 pb6/ irq4 /a18/ back 38 pb7 pb7/ irq5 /a19/ breq pb7 pb7/ irq5 /a19/ breq 39 pb8 pb8/ irq6 /a20/ wait pb8 pb8/ irq6 /a20/ wait 41 pb9 pb9/ irq7 /a21/ adtrg pb9 pb9/ irq7 /a21/ adtrg 42 dbgmd * 1 dbgmd * 1 dbgmd * 1 dbgmd * 1 43 rd pa14/ rd rd pa14/ rd 44 wdtovf wdtovf wdtovf wdtovf 45 pd31 pd31/d31/ adtrg d31 pd31/d31/ adtrg 46 pd30 pd30/d30/ irqout d30 pd30/d30/ irqout 47 wrh pa13/ wrh wrh pa13/ wrh 48 wrl pa12/ wrl wrl pa12/ wrl 49 cs1 pa11/ cs1 cs1 pa11/ cs1 50 cs0 pa10/ cs0 cs0 pa10/ cs0 51 pa9 pa9/tclkd/ irq3 pa9 pa9/tclkd/ irq3 52 pa8 pa8/tclkc/ irq2 pa8 pa8/tclkc/ irq2 53 pa7 pa7/tclkb/ cs3 pa7 pa7/tclkb/ cs3 54 pa6 pa6/tclka/ cs2 pa6 pa6/tclka/ cs2 56 pd29 pd29/d29/ cs3 d29 pd29/d29/ cs3 57 pd28 pd28/d28/ cs2 d28 pd28/d28/ cs2 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 587 of 882 rej09b0108-0400 pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 58 pd27 pd27/d27/dack1 d27 pd27/d27/dack1 59 pd26 pd26/d26/dack0 d26 pd26/d26/dack0 60 pd25 pd25/d25/ dreq1 d25 pd25/d25/ dreq1 62 pd24 pd24/d24/ dreq0 d24 pd24/d24/ dreq0 64 pd23 pd23/d23/ irq7 / audsync * 1 d23 pd23/d23/ irq7 / audsync * 1 65 pd22 pd22/d22/ irq6 /audck * 1 d22 pd22/d22/ irq6 /audck * 1 66 pd21 pd21/d21/ irq5 /audmd * 1 d21 pd21/d21/ irq5 /audmd * 1 67 pd20 pd20/d20/ irq4 / audrst * 1 d20 pd20/d20/ irq4 / audrst * 1 68 pd19 pd19/d19/ irq3 / audata3 * 1 d19 pd19/d19/ irq3 / audata3 * 1 69 pd18 pd18/d18/ irq2 / audata2 * 1 d18 pd18/d18/ irq2 / audata2 * 1 70 pd17 pd17/d17/ irq1 / audata1 * 1 d17 pd17/d17/ irq1 / audata1 * 1 72 pd16 pd16/d16/ irq0 / audata0 * 1 d16 pd16/d16/ irq0 / audata0 * 1 73 d15 pd15/d15 d15 pd15/d15 74 d14 pd14/d14 d14 pd14/d14 75 d13 pd13/d13 d13 pd13/d13 76 d12 pd12/d12 d12 pd12/d12 78 d11 pd11/d11 d11 pd11/d11 80 d10 pd10/d10 d10 pd10/d10 81 d9 pd9/d9 d9 pd9/d9 82 d8 pd8/d8 d8 pd8/d8 83 d7 pd7/d7 d7 pd7/d7 84 d6 pd6/d6 d6 pd6/d6 86 d5 pd5/d5 d5 pd5/d5 88 d4 pd4/d4 d4 pd4/d4 89 d3 pd3/d3 d3 pd3/d3 90 d2 pd2/d2 d2 pd2/d2 91 d1 pd1/d1 d1 pd1/d1 92 d0 pd0/d0 d0 pd0/d0 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 588 of 882 rej09b0108-0400 pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 94 xtal xtal xtal xtal 95 md3 md3 md3 md3 96 extal extal extal extal 97 md2 md2 md2 md2 98 nmi nmi nmi nmi 99 fwp * 1 fwp * 1 fwp * 1 fwp * 1 100 pa16 pa16/ audsync * 1 pa16 pa16/ audsync * 1 101 pa17 pa17/ wait pa17 pa17/ wait 102 md1 md1 md1 md1 103 md0 md0 md0 md0 107 ck pa15/ck ck pa15/ck 108 res res res res 109 pe0 pe0/tioc0a/ dreq0 / audck * 1 pe0 pe0/tioc0a/ dreq0 / audck * 1 110 pe1 pe1/tioc0b/drak0/ audmd * 1 pe1 pe1/tioc0b/drak0/ audmd * 1 111 pe2 pe2/tioc0c/ dreq1 / audrst * 1 pe2 pe2/tioc0c/ dreq1 / audrst * 1 113 pe3 pe3/tioc0d/drak1/ audata3 * 1 pe3 pe3/tioc0d/drak1/ audata3 * 1 114 pe4 pe4/tioc1a/rxd3/ audata2 * 1 pe4 pe4/tioc1a/rxd3/ audata2 * 1 115 pe5 pe5/tioc1b/txd3/ audata1 * 1 pe5 pe5/tioc1b/txd3 /audata1 * 1 116 pe6 pe6/tioc2a/sck3/ audata0 * 1 pe6 pe6/tioc2a/sck3 /audata0 * 1 118 pf0/an0 pf0/an0 pf0/an0 pf0/an0 119 pf1/an1 pf1/an1 pf1/an1 pf1/an1 120 pf2/an2 pf2/an2 pf2/an2 pf2/an2 121 pf3/an3 pf3/an3 pf3/an3 pf3/an3 122 pf4/an4 pf4/an4 pf4/an4 pf4/an4 123 pf5/an5 pf5/an5 pf5/an5 pf5/an5 125 pf6/an6 pf6/an6 pf6/an6 pf6/an6 126 pf7/an7 pf7/an7 pf7/an7 pf7/an7 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 589 of 882 rej09b0108-0400 pin name pin no. on-chip rom disabled (mcu mode 0) on-chip rom disabled (mcu mode 1) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 130 pa0 pa0/rxd0 pa0 pa0/rxd0 131 pa1 pa1/txd0 pa1 pa1/txd0 132 pa2 pa2/sck0/ dreq0 / irq0 pa2 pa2/sck0/ dreq0 / irq0 133 pa3 pa3/rxd1 pa3 pa3/rxd1 134 pa4 pa4/txd1 pa4 pa4/txd1 136 pa5 pa5/sck1/ dreq1 / irq1 pa5 pa5/sck1/ dreq1 / irq1 137 pe7 pe7/tioc2b/rxd2 pe7 pe7/tioc2b/rxd2 138 pe8/(tms * 1 * 2 ) pe8/tioc3a/sck2 pe8/(tms * 1 * 2 ) pe8/tioc3a/sck2 139 pe9/( trst * 1 * 2 ) pe9/tioc3b/sck3 pe9/( trst * 1 * 2 ) pe9/tioc3b/sck3 140 pe10/(tdi * 1 * 2 ) pe10/tioc3c/txd2 pe10/(tdi * 1 * 2 ) pe10/tioc3c/txd2 142 pe11/(tdo * 1 * 2 ) pe11/tioc3d/rxd3 pe11/(tdo * 1 * 2 ) pe11/tioc3d/rxd3 143 pe12/(tck * 1 * 2 ) pe12/tioc4a/txd3 pe12/(tck * 1 * 2 ) pe12/tioc4a/txd3 144 pe13 pe13/tioc4b/ mres pe13 pe13/tioc4b/ mres notes: 1. f-ztat version only 2. fixed to tms, trst , tdi, tdo, and tck when using the e10a (in dbgmd = high). 3. masked rom version and rom less version only 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 590 of 882 rej09b0108-0400 table 17.14 sh7145 pin functions in each mode (2) pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 12, 26, 40, 63, 77, 85, 112, 135 vcc vcc vcc vcc 6, 14, 28, 55, 61, 71, 79, 87, 93, 117, 129, 141 vss vss vss vss 128 avcc avcc avcc avcc 127 avref avref avref avref 124 avss avss avss avss 104 pllvcc pllvcc pllvcc pllvcc 105 pllcap pllcap pllcap pllcap 106 pllvss pllvss pllvss pllvss 1 pa23 pa23/ wrhh pa23 pa23/ wrhh 2 pe14 pe14/tioc4c/dack0 pe14 pe14/tioc4c/dack0 3 pa22 pa22/ wrhl pa22 pa22/ wrhl 4 pa21 pa21/ cs5 * 3 pa21 pa21/ cs5 * 3 5 pe15 pe15/tioc4d/dack1/ irqout pe15 pe15/tioc4d/dack1/ irqout 7 pc0 pc0/a0 pc0 pc0/a0 8 pc1 pc1/a1 pc1 pc1/a1 9 pc2 pc2/a2 pc2 pc2/a2 10 pc3 pc3/a3 pc3 pc3/a3 11 pc4 pc4/a4 pc4 pc4/a4 13 pc5 pc5/a5 pc5 pc5/a5 15 pc6 pc6/a6 pc6 pc6/a6 16 pc7 pc7/a7 pc7 pc7/a7 17 pc8 pc8/a8 pc8 pc8/a8 18 pc9 pc9/a9 pc9 pc9/a9 19 pc10 pc10/a10 pc10 pc10/a10 20 pc11 pc11/a11 pc11 pc11/a11 21 pc12 pc12/a12 pc12 pc12/a12 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 591 of 882 rej09b0108-0400 pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 22 pc13 pc13/a13 pc13 pc13/a13 23 pc14 pc14/a14 pc14 pc14/a14 24 pc15 pc15/a15 pc15 pc15/a15 25 pb0 pb0/a16 pb0 pb0/a16 27 pb1 pb1/a17 pb1 pb1/a17 29 pa20 pa20/ cs4 * 3 pa20 pa20/ cs4 * 3 30 pa19 pa19/ back /drak1 pa19 pa19/ back /drak1 31 pb2 pb2/ irq0 / poe0 /scl0 pb2 pb2/ irq0 / poe0 /scl0 32 pb3 pb3/ irq1 / poe1 /sda0 pb3 pb3/ irq1 / poe1 /sda0 33 pa18 pa18/ breq /drak0 pa18 pa18/ breq /drak0 34 pb4 pb4/ irq2 / poe2 / cs6 * 3 pb4 pb4/ irq2 / poe2 / cs6 * 3 35 asebrkak * 1 asebrkak * 1 asebrkak * 1 asebrkak * 1 36 pb5 pb5/ irq3 / poe3 / cs7 * 3 pb5 pb5/ irq3 / poe3 / cs7 * 3 37 pb6 pb6/ irq4 /a18/ back pb6 pb6/ irq4 /a18/ back 38 pb7 pb7/ irq5 /a19/ breq pb7 pb7/ irq5 /a19/ breq 39 pb8 pb8/ irq6 /a20/ wait pb8 pb8/ irq6 /a20/ wait 41 pb9 pb9/ irq7 /a21/ adtrg pb9 pb9/ irq7 /a21/ adtrg 42 dbgmd * 1 dbgmd * 1 dbgmd * 1 dbgmd * 1 43 pa14 pa14/ rd pa14 pa14/ rd 44 wdtovf wdtovf wdtovf wdtovf 45 pd31 pd31/d31/ adtrg pd31 pd31/d31/ adtrg 46 pd30 pd30/d30/ irqout pd30 pd30/d30/ irqout 47 pa13 pa13/ wrh pa13 pa13/ wrh 48 pa12 pa12/ wrl pa12 pa12/ wrl 49 pa11 pa11/ cs1 pa11 pa11/ cs1 50 pa10 pa10/ cs0 pa10 pa10/ cs0 51 pa9 pa9/tclkd/ irq3 pa9 pa9/tclkd/ irq3 52 pa8 pa8/tclkc/ irq2 pa8 pa8/tclkc/ irq2 53 pa7 pa7/tclkb/ cs3 pa7 pa7/tclkb/ cs3 54 pa6 pa6/tclka/ cs2 pa6 pa6/tclka/ cs2 56 pd29 pd29/d29/ cs3 pd29 pd29/d29/ cs3 57 pd28 pd28/d28/ cs2 pd28 pd28/d28/ cs2 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 592 of 882 rej09b0108-0400 pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 58 pd27 pd27/d27/dack1 pd27 pd27/d27/dack1 59 pd26 pd26/d26/dack0 pd26 pd26/d26/dack0 60 pd25 pd25/d25/ dreq1 pd25 pd25/d25/ dreq1 62 pd24 pd24/d24/ dreq0 pd24 pd24/d24/ dreq0 64 pd23 pd23/d23/ irq7 / audsync * 1 pd23 pd23/d23/ irq7 / audsync * 1 65 pd22 pd22/d22/ irq6 /audck * 1 pd22 pd22/d22/ irq6 /audck * 1 66 pd21 pd21/d21/ irq5 /audmd * 1 pd21 pd21/d21/ irq5 /audmd * 1 67 pd20 pd20/d20/ irq4 / audrst * 1 pd20 pd20/d20/ irq4 / audrst * 1 68 pd19 pd19/d19/ irq3 / audata3 * 1 pd19 pd19/d19/ irq3 / audata3 * 1 69 pd18 pd18/d18/ irq2 / audata2 * 1 pd18 pd18/d18/ irq2 / audata2 * 1 70 pd17 pd17/d17/ irq1 / audata1 * 1 pd17 pd17/d17/ irq1 / audata1 * 1 72 pd16 pd16/d16/ irq0 / audata0 * 1 pd16 pd16/d16/ irq0 / audata0 * 1 73 pd15 pd15/d15 pd15 pd15/d15 74 pd14 pd14/d14 pd14 pd14/d14 75 pd13 pd13/d13 pd13 pd13/d13 76 pd12 pd12/d12 pd12 pd12/d12 78 pd11 pd11/d11 pd11 pd11/d11 80 pd10 pd10/d10 pd10 pd10/d10 81 pd9 pd9/d9 pd9 pd9/d9 82 pd8 pd8/d8 pd8 pd8/d8 83 pd7 pd7/d7 pd7 pd7/d7 84 pd6 pd6/d6 pd6 pd6/d6 86 pd5 pd5/d5 pd5 pd5/d5 88 pd4 pd4/d4 pd4 pd4/d4 89 pd3 pd3/d3 pd3 pd3/d3 90 pd2 pd2/d2 pd2 pd2/d2 91 pd1 pd1/d1 pd1 pd1/d1 92 pd0 pd0/d0 pd0 pd0/d0 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 593 of 882 rej09b0108-0400 pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 94 xtal xtal xtal xtal 95 md3 md3 md3 md3 96 extal extal extal extal 97 md2 md2 md2 md2 98 nmi nmi nmi nmi 99 fwp * 1 fwp * 1 fwp * 1 fwp * 1 100 pa16 pa16/ audsync * 1 pa16 pa16/ audsync * 1 101 pa17 pa17/ wait pa17 pa17/ wait 102 md1 md1 md1 md1 103 md0 md0 md0 md0 107 ck pa15/ck pa15 pa15/ck 108 res res res res 109 pe0 pe0/tioc0a/ dreq0 / audck * 1 pe0 pe0/tioc0a/ dreq0 / audck * 1 110 pe1 pe1/tioc0b/drak0/ audmd * 1 pe1 pe1/tioc0b/drak0/ audmd * 1 111 pe2 pe2/tioc0c/ dreq1 / audrst * 1 pe2 pe2/tioc0c/ dreq1 / audrst * 1 113 pe3 pe3/tioc0d/drak1/ audata3 * 1 pe3 pe3/tioc0d/drak1/ audata3 * 1 114 pe4 pe4/tioc1a/rxd3/ audata2 * 1 pe4 pe4/tioc1a/rxd3/ audata2 * 1 115 pe5 pe5/tioc1b/txd3/ audata1 * 1 pe5 pe5/tioc1b/txd3/ audata1 * 1 116 pe6 pe6/tioc2a/sck3/ audata0 * 1 pe6 pe6/tioc2a/sck3/ audata0 * 1 118 pf0/an0 pf0/an0 pf0/an0 pf0/an0 119 pf1/an1 pf1/an1 pf1/an1 pf1/an1 120 pf2/an2 pf2/an2 pf2/an2 pf2/an2 121 pf3/an3 pf3/an3 pf3/an3 pf3/an3 122 pf4/an4 pf4/an4 pf4/an4 pf4/an4 123 pf5/an5 pf5/an5 pf5/an5 pf5/an5 125 pf6/an6 pf6/an6 pf6/an6 pf6/an6 126 pf7/an7 pf7/an7 pf7/an7 pf7/an7 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 594 of 882 rej09b0108-0400 pin name pin no. on-chip rom enabled (mcu mode 2) single chip mode (mcu mode 3) sh7145 initial function pfc selected function possibilities initial function pfc selected function possibilities 130 pa0 pa0/rxd0 pa0 pa0/rxd0 131 pa1 pa1/txd0 pa1 pa1/txd0 132 pa2 pa2/sck0/ dreq0 / irq0 pa2 pa2/sck0/ dreq0 / irq0 133 pa3 pa3/rxd1 pa3 pa3/rxd1 134 pa4 pa4/txd1 pa4 pa4/txd1 136 pa5 pa5/sck1/ dreq1 / irq1 pa5 pa5/sck1/ dreq1 / irq1 137 pe7 pe7/tioc2b/rxd2 pe7 pe7/tioc2b/rxd2 138 pe8/(tms * 1 * 2 ) pe8/tioc3a/sck2 pe8/(tms * 1 * 2 ) pe8/tioc3a/sck2 139 pe9/( trst * 1 * 2 ) pe9/tioc3b/sck3 pe9/( trst * 1 * 2 ) pe9/tioc3b/sck3 140 pe10/(tdi * 1 * 2 ) pe10/tioc3c/txd2 pe10/(tdi * 1 * 2 ) pe10/tioc3c/txd2 142 pe11/(tdo * 1 * 2 ) pe11/tioc3d/rxd3 pe11/(tdo * 1 * 2 ) pe11/tioc3d/rxd3 143 pe12/(tck * 1 * 2 ) pe12/tioc4a/txd3 pe12/(tck * 1 * 2 ) pe12/tioc4a/txd3 144 pe13 pe13/tioc4b/ mres pe13 pe13/tioc4b/ mres notes: 1. f-ztat version only 2. fixed to tms, trst , tdi, tdo, and tck when using the e10a (in dbgmd = high). 3. masked rom version and rom less version only 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 595 of 882 rej09b0108-0400 17.1 register descriptions the pfc has the following registers. for details on the addresses of the re gisters and their states during each process, see sect ion 25, list of registers. ? port a i/o register h (paiorh)* ? port a i/o register l (paiorl) ? port a control register h (pacrh)* ? port a control register l2 (pacrl2) ? port a control register l1 (pacrl1) ? port b i/o register (pbior) ? port b control register 1 (pbcr1) ? port b control register 2 (pbcr2) ? port c i/o register (pcior) ? port c control register (pccr) ? port d i/o register h (pdiorh)* ? port d i/o register l (pdiorl) ? port d control register h1 (pdcrh1)* ? port d control register h2 (pdcrh2)* ? port d control register l1 (pdcrl1) ? port d control register l2 (pdcrl2) ? port e i/o register l (peiorl) ? port e control register l1 (pecrl1) ? port e control register l2 (pecrl2) ? high-current port control register (ppcr) note: * can be set only in sh7145. these are not available in sh7144. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 596 of 882 rej09b0108-0400 17.1.1 port a i/o register l, h (paiorl, paiorh) the port a i/o register l, h (paiorl, paiorh) are 16-bit readable/writable registers that are used to set the pins on port a as inputs or outputs. bits pa23ior to pa0ior correspond to pins pa23 to pa0 (names of multiplexed pins are here given as port names and pin numbers alone). paiorl is enabled when the port a pins are functioning as general-purpose inputs/outputs (pa15 to pa0), and sck0 and sck1 pins are functioning as inputs/outputs of sci. in other states, paiorl is disabled. paiorh is enabled when the port a pins are functioning as general-purpose input/output (pa23 to pa16). in other states, paiorh is disabled. a given pin on port a will be an output pin if the corresponding bit in paiorh or paiorl is set to 1, and an input pin if the bit is cleared to 0. bits 7 to 0 of paiorh are, however, disabled in sh7144. bits 15 to 8 of paiorh are reserved. these bits are always read as 0. the write value should always be 0. the initial values of paiorl and paiorh are h'0000, respectively. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 597 of 882 rej09b0108-0400 17.1.2 port a control registers l2, l1, h (pacrl2, pacrl1, pacrh) the port a control registers l2, l1, and h (pacrl2, pacrl1, and pacrh) are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port a. ? port a control registers l2, l1, and h (p acrl2, pacrl1, and pacrh) in sh7144 register bit bit name initial value r/w description pacrh pacrh pacrh pacrh pacrh pacrh pacrl1 pacrl2 15, 13 11, 9 14, 12 10, 8 7 to 4, 2 to 0 3 15, 13, 11, 9, 7, 5 9, 7, 3, 1 ? ? ? ? ? ? ? ? all 0 all 0 all 0 all 0 all 0 0 all 0 all 0 r r r/w r/w r/w r r r reserved these bits are always read as 0. the write value should always be 0. pacrl1 14 pa15md 0 * 1 r/w pa15 mode selects the function of the pa15/ck pin. 0: pa15 i/o (port) 1: ck output (cpg) pacrl1 12 pa14md 0 * 2 r/w pa14 mode selects the function of the pa14/ rd pin. 0: pa14 i/o (port) 1: rd output (bsc) pacrl1 10 pa13md 0 * 2 r/w pa13 mode selects the function of the pa13/ wrh pin. 0: pa13 i/o (port) 1: wrh output (bsc) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 598 of 882 rej09b0108-0400 register bit bit name initial value r/w description pacrl1 8 pa12md 0 * 2 r/w pa12 mode selects the function of the pa12/ wrl pin. 0: pa12 i/o (port) 1: wrl output (bsc) pacrl1 6 pa11md 0 * 2 r/w pa11 mode selects the function of the pa11/ cs1 pin. 0: pa11 i/o (port) 1: cs1 output (bsc) pacrl1 4 pa10md 0 * 2 r/w pa10 mode selects the function of the pa10/ cs0 pin. 0: pa10 i/o (port) 1: cs0 output (bsc) pacrl1 pacrl1 3 2 pa9md1 pa9md0 0 0 r/w r/w pa9 mode select the function of the pa9/tclkd/ irq3 pin. 00: pa9 i/o (port) 01: tclkd input (mtu) 10: irq3 input (intc) 11: setting prohibited pacrl1 pacrl1 1 0 pa8md1 pa8md0 0 0 r/w r/w pa8 mode select the function of the pa8/tclkc/ irq2 pin. 00: pa8 i/o (port) 01: tclkc input (mtu) 10: irq2 input (intc) 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 599 of 882 rej09b0108-0400 register bit bit name initial value r/w description pacrl2 pacrl2 15 14 pa7md1 pa7md0 0 0 r/w r/w pa7 mode select the function of the pa7/tclkb/ cs3 pin. 00: pa7 i/o (port) 01: tclkb input (mtu) 10: cs3 output (bsc) 11: setting prohibited pacrl2 pacrl2 13 12 pa6md1 pa6md0 0 0 r/w r/w pa6 mode select the function of the pa6/tclka/ cs2 pin. 00: pa6 i/o (port) 01: tclka input (mtu) 10: cs2 output (bsc) 11: setting prohibited pacrl2 pacrl2 11 10 pa5md1 pa5md0 0 0 r/w r/w pa5 mode select the function of the pa5/sck1/ dreq1 / irq1 pin. 00: pa5 i/o (port) 01: sck1 i/o (sci) 10: dreq1 input (dmac) 11: irq1 input (intc) pacrl2 8 pa4md 0 r/w pa4 mode selects the function of the pa4/txd1 pin. 0: pa4 i/o (port) 1: txd1 output (sci) pacrl2 6 pa3md 0 r/w pa3 mode selects the function of the pa3/rxd1 pin. 0: pa3 i/o (port) 1: rxd1 input (sci) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 600 of 882 rej09b0108-0400 register bit bit name initial value r/w description pacrl2 pacrl2 5 4 pa2md1 pa2md0 0 0 r/w r/w pa2 mode select the function of the pa2/sck0/ dreq0 / irq0 pin. 00: pa2 i/o (port) 01: sck0 i/o (sci) 10: dreq0 input (dmac) 11: irq0 input (intc) pacrl2 2 pa1md 0 r/w pa1 mode selects the function of the pa1/txd0 pin. 0: pa1 i/o (port) 1: txd0 output (sci) pacrl2 0 pa0md 0 r/w pa0 mode selects the function of the pa0/rxd0 pin. 0: pa0 i/o (port) 1: rxd0 input (sci) notes: 1. the initial value is 1 in the on-chip rom enabled/disabled external-expansion mode. 2. the initial value is 1 in the on-chip rom disabled external-expansion mode. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 601 of 882 rej09b0108-0400 ? port a control registers l2, l1, and h (pacrl2, pacrl1 and pacrh) in the sh7145 register bit bit name initial value r/w description pacrh pacrh pacrh pacrh pacrh pacrl1 pacrl2 15 13 11 9 3 15, 13, 11, 9, 7, 5 9, 7, 3, 1 ? ? ? ? ? ? ? 0 0 0 0 0 all 0 all 0 r r r r r r r reserved these bits are always read as 0. the write value should always be 0. pacrh 14 pa23md 0 * 3 r/w pa23 mode selects the function of the pa23/ wrhh pin. 0: pa23 i/o (port) 1: wrhh output (bsc) pacrh 12 pa22md 0 * 3 r/w pa22 mode selects the function of the pa22/ wrhl pin. 0: pa22 i/o (port) 1: wrhl output (bsc) pacrh 10 pa21md 0 r/w pa21 mode selects the function of the pa21/ cs5 pin. 0: pa21 i/o (port) 1: cs5 output (bsc) * 4 pacrh 8 pa20md 0 r/w pa20 mode selects the function of the pa20/ cs4 pin. 0: pa20 i/o (port) 1: cs4 output (bsc) * 4 pacrh pacrh 7 6 pa19md1 pa19md0 0 0 r/w r/w pa19 mode select the function of the pa19/ back /drak1 pin. 00: pa19 i/o (port) 01: back output (bsc) 10: drak1 output (dmac) 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 602 of 882 rej09b0108-0400 register bit bit name initial value r/w description pacrh pacrh 5 4 pa18md1 pa18md0 0 0 r/w r/w pa18 mode select the function of the pa18/ breq /drak0 pin. 00: pa18 i/o (port) 01: breq input (bsc) 10: drak0 output (dmac) 11: setting prohibited pacrh 2 pa17md 0 r/w pa17 mode selects the function of the pa17/ wait pin. 0: pa17 i/o (port) 1: wait input (bsc) pacrh pacrh 1 0 pa16md1 pa16md0 0 0 r/w r/w pa16 mode select the function of the pa16/ audsync pin. 00: pa16 i/o (port) 01: setting prohibited 10: setting prohibited 11: audsync i/o (aud) * 1 pacrl1 14 pa15md 0 * 2 r/w pa15 mode selects the function of the pa15/ck pin. 0: pa15 i/o (port) 1: ck output (cpg) pacrl1 12 pa14md 0 * 3 r/w pa14 mode selects the function of the pa14/ rd pin. 0: pa14 i/o (port) 1: rd output (bsc) pacrl1 10 pa13md 0 * 3 r/w pa13 mode selects the function of the pa13/ wrh pin. 0: pa13 i/o (port) 1: wrh output (bsc) pacrl1 8 pa12md 0 * 3 r/w pa12 mode selects the function of the pa12/ wrl pin. 0: pa12 i/o (port) 1: wrl output (bsc) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 603 of 882 rej09b0108-0400 register bit bit name initial value r/w description pacrl1 6 pa11md 0 * 3 r/w pa11 mode selects the function of the pa11/ cs1 pin. 0: pa11 i/o (port) 1: cs1 output (bsc) pacrl1 4 pa10md 0 * 3 r/w pa10 mode selects the function of the pa10/ cs0 pin. 0: pa10 i/o (port) 1: cs0 output (bsc) pacrl1 pacrl1 3 2 pa9md1 pa9md0 0 0 r/w r/w pa9 mode select the function of the pa9/tclkd/ irq3 pin. 00: pa9 i/o (port) 01: tclkd input (mtu) 10: irq3 input (intc) 11: setting prohibited pacrl1 pacrl1 1 0 pa8md1 pa8md0 0 0 r/w r/w pa8 mode select the function of the pa8/tclkc/ irq2 pin. 00: pa8 i/o (port) 01: tclkc input (mtu) 10: irq2 input (intc) 11: setting prohibited pacrl2 pacrl2 15 14 pa7md1 pa7md0 0 0 r/w r/w pa7 mode select the function of the pa7/tclkb/ cs3 pin. 00: pa7 i/o (port) 01: tclkb input (mtu) 10: cs3 output (bsc) 11: setting prohibited pacrl2 pacrl2 13 12 pa6md1 pa6md0 0 0 r/w r/w pa6 mode select the function of the pa6/tclka/ cs2 pin. 00: pa6 i/o (port) 01: tclka input (mtu) 10: cs2 output (bsc) 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 604 of 882 rej09b0108-0400 register bit bit name initial value r/w description pacrl2 pacrl2 11 10 pa5md1 pa5md0 0 0 r/w r/w pa5 mode select the function of the pa5/sck1/ dreq1 / irq1 pin. 00: pa5 i/o (port) 01: sck1 i/o (sci) 10: dreq1 input (dmac) 11: irq1 input (intc) pacrl2 8 pa4md 0 r/w pa4 mode selects the function of the pa4/txd1 pin. 0: pa4 i/o (port) 1: txd1 output (sci) pacrl2 6 pa3md 0 r/w pa3 mode selects the function of the pa3/rxd1 pin. 0: pa3 i/o (port) 1: rxd1 input (sci) pacrl2 pacrl2 5 4 pa2md1 pa2md0 0 0 r/w r/w pa2 mode select the function of the pa2/sck0/ dreq0 / irq0 pin. 00: pa2 i/o (port) 01: sck0 i/o (sci) 10: dreq0 input (dmac) 11: irq0 input (intc) pacrl2 2 pa1md 0 r/w pa1 mode selects the function of the pa1/txd0 pin. 0: pa1 i/o (port) 1: txd0 output (sci) pacrl2 0 pa0md 0 r/w pa0 mode selects the function of the pa0/rxd0 pin. 0: pa0 i/o (port) 1: rxd0 input (sci) notes: 1. f-ztat version only. setting prohibi ted for the masked rom version and rom less version. 2. the initial value is 1 in the on-chip rom enabled/disabled external-expansion mode. 3. the initial value is 1 in the on-chip rom disabled external-expansion mode. 4. masked rom version and rom less version only. setting prohibited for the f-ztat version and emulator. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 605 of 882 rej09b0108-0400 17.1.3 port b i/o register (pbior) the port b i/o register (pbior) is a 16-bit readable/writable register that is used to set the pins on port b as inputs or outputs. bits pb9ior to pb0ior correspond to pins pb9 to pb0 (names of multiplexed pins are here given as port names and pin numbers alone). pbior is enabled when port b pins are functioning as general-purpose inputs/outputs (pb9 to pb0). in other states, pbior is disabled. a given pin on port b will be an output pin if the corresponding bit in pbior is set to 1, and an input pin if the bit is cleared to 0. bits 15 to 10 are reserved. these bits are always read as 0. the write value should always be 0. the initial value of pbior is h'0000. 17.1.4 port b control registers 1, 2 (pbcr1, pbcr2) the port b control registers 1 and 2 (pbcr1 and pbcr2) are 16-bit readable/writable registers that are used to select the multiplexed pin function of the pins on port b. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 606 of 882 rej09b0108-0400 ? port b control registers 1 and 2 (pbcr1 and pbcr2) register bit bit name initial value r/w description pbcr1 pbcr1 pbcr1 pbcr2 15, 14 13, 12 9 to 4 3, 1 ? ? ? ? all 0 all 0 all 0 all 0 r r/w r r reserved these bits are always read as 0. the write value should always be 0. pbcr1 pbcr1 3 2 pb9md1 pb9md0 0 0 r r pb9 mode select the function of the pb9/ irq7 /a21/ adtrg pin. 00: pb9 i/o (port) 01: irq7 input (intc) 10: a21 output (bsc) 11: adtrg input (a/d) pbcr1 pbcr1 1 0 pb8md1 pb8md0 0 0 r/w r/w pb8 mode select the function of the pb8/ irq6 /a20/ wait pin. 00: pb8 i/o (port) 01: irq6 input (intc) 10: a20 output (bsc) 11: wait input (bsc) pbcr2 pbcr2 15 14 pb7md1 pb7md0 0 0 r/w r/w pb7 mode select the function of the pb7/ irq5 /a19/ breq pin. 00: pb7 i/o (port) 01: irq5 input (intc) 10: a19 output (bsc) 11: breq input (bsc) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 607 of 882 rej09b0108-0400 register bit bit name initial value r/w description pbcr2 pbcr2 13 12 pb6md1 pb6md0 0 0 r/w r/w pb6 mode select the function of the pb6/ irq4 /a18/ back pin. 00: pb6 i/o (port) 01: irq4 input (intc) 10: a18 output (bsc) 11: back output (bsc) pbcr2 pbcr2 11 10 pb5md1 pb5md0 0 0 r/w r/w pb5 mode select the function of the pb5/ irq3 / poe3 / cs7 pin. 00: pb5 i/o (port) 01: irq3 input (intc) 10: poe3 input (port) 11: cs7 output (bsc) * 2 pbcr2 pbcr2 9 8 pb4md1 pb4md0 0 0 r/w r/w pb4 mode select the function of the pb4/ irq2 / poe2 / cs6 pin. 00: pb4 i/o (port) 01: irq2 input (intc) 10: poe2 input (port) 11: cs6 output (bsc) * 2 pbcr1 pbcr2 pbcr2 11 7 6 pb3md2 pb3md1 pb3md0 0 0 0 r/w r/w r/w pb3 mode select the function of the pb3/ irq1 / poe1 /sda0 pin. 000: pb3 i/o (port) 001: irq1 input (intc) 010: poe1 input (port) 011: setting prohibited 100: sda0 i/o (iic) 101: setting prohibited 110: setting prohibited 111: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 608 of 882 rej09b0108-0400 register bit bit name initial value r/w description pbcr1 pbcr2 pbcr2 10 5 4 pb2md2 pb2md1 pb2md0 0 0 0 r/w r/w r/w pb2 mode select the function of the pb2/ irq0 / poe0 /scl0 pin. 000: pb2 i/o (port) 001: irq0 input (intc) 010: poe0 input (port) 011: setting prohibited 100: scl0 i/o (iic) 101: setting prohibited 110: setting prohibited 111: setting prohibited pbcr2 2 pb1md 0 * 1 r/w pb1 mode selects the function of the pb1/a17 pin. 0: pb1 i/o (port) 1: a17 output (bsc) pbcr2 0 pb0md 0 * 1 r/w pb0 mode selects the function of the pb0/a16 pin. 0: pb0 i/o (port) 1: a16 output (bsc) notes: 1. the initial value is 1 in the on-chip rom disabled external-expansion mode. 2. masked rom version and rom less version only. setting prohibited for the f-ztat version and emulator. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 609 of 882 rej09b0108-0400 17.1.5 port c i/o register (pcior) pcior is a 16-bit readable/writable register that is used to set the pins on port c as inputs or outputs. bits pc15ior to pc0ior correspond to pins pc15 to pc0 (names of multiplexed pins are here given as port names and pin numbers alone). pcior is enabled when the port c pins are functioning as general-purpose inputs/outputs (pc15 to pc0). in other states, pcior is disabled. a given pin on port c will be an output pin if the corresponding bit in pcior is set to 1, and an input pin if the bit is cleared to 0. the initial value of pcior is h'0000. 17.1.6 port c control register (pccr) pccr is a 16-bit readable/writable register that is used to select the multiplexed pin function of the pins on port c. ? port c control register (pccr) register bit bit name initial value r/w description pccr 15 pc15md 0 * r/w pc15 mode selects the function of the pc15/a15 pin. 0: pc15 i/o (port) 1: a15 output (bsc) pccr 14 pc14md 0 * r/w pc14 mode selects the function of the pc14/a14 pin. 0: pc14 i/o (port) 1: a14 output (bsc) pccr 13 pc13md 0 * r/w pc13 mode selects the function of the pc13/a13 pin. 0: pc13 i/o (port) 1: a13 output (bsc) pccr 12 pc12md 0 * r/w pc12 mode selects the function of the pc12/a12 pin. 0: pc12 i/o (port) 1: a12 output (bsc) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 610 of 882 rej09b0108-0400 register bit bit name initial value r/w description pccr 11 pc11md 0 * r/w pc11 mode selects the function of the pc11/a11 pin. 0: pc11 i/o (port) 1: a11 output (bsc) pccr 10 pc10md 0 * r/w pc10 mode selects the function of the pc10/a10 pin. 0: pc10 i/o (port) 1: a10 output (bsc) pccr 9 pc9md 0 * r/w pc9 mode selects the function of the pc9/a9 pin. 0: pc9 i/o (port) 1: a9 output (bsc) pccr 8 pc8md 0 * r/w pc8 mode selects the function of the pc8/a8 pin. 0: pc8 i/o (port) 1: a8 output (bsc) pccr 7 pc7md 0 * r/w pc7 mode selects the function of the pc7/a7 pin. 0: pc7 i/o (port) 1: a7 output (bsc) pccr 6 pc6md 0 * r/w pc6 mode selects the function of the pc6/a6 pin. 0: pc6 i/o (port) 1: a6 output (bsc) pccr 5 pc5md 0 * r/w pc5 mode selects the function of the pc5/a5 pin. 0: pc5 i/o (port) 1: a5 output (bsc) pccr 4 pc4md 0 * r/w pc4 mode selects the function of the pc4/a4 pin. 0: pc4 i/o (port) 1: a4 output (bsc) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 611 of 882 rej09b0108-0400 register bit bit name initial value r/w description pccr 3 pc3md 0 * r/w pc3 mode selects the function of the pc3/a3 pin. 0: pc3 i/o (port) 1: a3 output (bsc) pccr 2 pc2md 0 * r/w pc2 mode selects the function of the pc2/a2 pin. 0: pc2 i/o (port) 1: a2 output (bsc) pccr 1 pc1md 0 * r/w pc1 mode selects the function of the pc1/a1 pin. 0: pc1 i/o (port) 1: a1 output (bsc) pccr 0 pc0md 0 * r/w pc0 mode selects the function of the pc0/a0 pin. 0: pc0 i/o (port) 1: a0 output (bsc) note: * the initial value is 1 in the on-chip rom disabled external-expansion mode. 17.1.7 port d i/o registers l, h (pdiorl, pdiorh) the port d i/o registers l and h (pdiorl and pdiorh) are 16-bit readab le/writable registers that are used to set the pins on port d as inputs or outputs. bits pd31ior to pd0ior correspond to pins pd31 to pd0 (names of multiplexed pins are here given as port names and pin numbers alone). pdiorl is enabled when the port d pins are functioning as general-purpose inputs/outputs (pd15 to pd0). in other states, pdiorl is disabled. pdiorh is enabled when the port d pins are functioning as general-purpose inputs/outputs (pd31 to pd16). in other states, pdiorh is disabled. a given pin on port d will be an output pin if the corresponding bit in pdiorl or pdiorh is set to 1, and an input pin if the bit is cleared to 0. note that bits 15 to 0 in pdiorh are disabled in the sh7144. the initial value of pdior is h'0000. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 612 of 882 rej09b0108-0400 17.1.8 port d control registers l1, l2, h1, h2 (pdcrl1, pdcrl2, pdcrh1, pdcrh2) the port d control registers l1, l2, h1, an d h2 (pdcrl1, pdcrl2, pdcrh1, and pdcrh2) are 16-bit readable/writable registers that are used to select the multiplexed pin function of the pins on port d. ? port d control registers l1, l2, h1, and h2 (pdcrl1, pdcrl2, pdcrh1, and pdcrh2) in sh7144 register bit bit name initial value r/w description pdcrh1 pdcrh2 pdcrl2 15 to 0 15 to 0 7 to 0 ? ? ? all 0 all 0 all 0 r/w r/w r reserved these bits are always read as 0. the write value should always be 0. pdcrl2 pdcrl1 15 15 pd15md1 pd15md0 0 0 * 2 r/w r/w pd15 mode select the function of the pd15/d15/ audsync pin. 00: pd15 i/o (port) 01: d15 i/o (bsc) 10: audsync i/o (aud) * 1 11: setting prohibited pdcrl2 pdcrl1 14 14 pd14md1 pd14md0 0 0 * 2 r/w r/w pd14 mode select the function of the pd14/d14/audck pin. 00: pd14 i/o (port) 01: d14 i/o (bsc) 10: audck i/o (aud) * 1 11: setting prohibited pdcrl2 pdcrl1 13 13 pd13md1 pd13md0 0 0 * 2 r/w r/w pd13 mode select the function of the pd13/d13/audmd pin. 00: pd13 i/o (port) 01: d13 i/o (bsc) 10: audmd input (aud) * 1 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 613 of 882 rej09b0108-0400 register bit bit name initial value r/w description pdcrl2 pdcrl1 12 12 pd12md1 pd12md0 0 0 * 2 r/w r/w pd12 mode select the function of the pd12/d12/ audrst pin. 00: pd12 i/o (port) 01: d12 i/o (bsc) 10: audrst input (aud) * 1 11: setting prohibited pdcrl2 pdcrl1 11 11 pd11md1 pd11md0 0 0 * 2 r/w r/w pd11 mode select the function of the pd11/d11/audata3 pin. 00: pd11 i/o (port) 01: d11 i/o (bsc) 10: audata3 i/o (aud) * 1 11: setting prohibited pdcrl2 pdcrl1 10 10 pd10md1 pd10md0 0 0 * 2 r/w r/w pd10 mode select the function of the pd10/d10/audata2 pin. 00: pd10 i/o (port) 01: d10 i/o (bsc) 10: audata2 i/o (aud) * 1 11: setting prohibited pdcrl2 pdcrl1 9 9 pd9md1 pd9md0 0 0 * 2 r/w r/w pd9 mode select the function of the pd9/d9/audata1 pin. 00: pd9 i/o (port) 01: d9 i/o (bsc) 10: audata1 i/o (aud) * 1 11: setting prohibited pdcrl2 pdcrl1 8 8 pd8md1 pd8md0 0 0 * 2 r/w r/w pd8 mode select the function of the pd8/d8/audata0 pin. 00: pd8 i/o (port) 01: d8 i/o (bsc) 10: audata0 i/o (aud) * 1 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 614 of 882 rej09b0108-0400 register bit bit name initial value r/w description pdcrl1 7 pd7md 0 * 3 r/w pd7 mode selects the function of the pd7/d7 pin. 0: pd7 i/o (port) 1: d7 i/o (bsc) pdcrl1 6 pd6md 0 * 3 r/w pd6 mode selects the function of the pd6/d6 pin. 0: pd6 i/o (port) 1: d6 i/o (bsc) pdcrl1 5 pd5md 0 * 3 r/w pd5 mode selects the function of the pd5/d5 pin. 0: pd5 i/o (port) 1: d5 i/o (bsc) pdcrl1 4 pd4md 0 * 3 r/w pd4 mode selects the function of the pd4/d4 pin. 0: pd4 i/o (port) 1: d4 i/o (bsc) pdcrl1 3 pd3md 0 * 3 r/w pd3 mode selects the function of the pd3/d3 pin. 0: pd3 i/o (port) 1: d3 i/o (bsc) pdcrl1 2 pd2md 0 * 3 r/w pd2 mode selects the function of the pd2/d2 pin. 0: pd2 i/o (port) 1: d2 i/o (bsc) pdcrl1 1 pd1md 0 * 3 r/w pd1 mode selects the function of the pd1/d1 pin. 0: pd1 i/o (port) 1: d1 i/o (bsc) pdcrl1 0 pd0md 0 * 3 r/w pd0 mode selects the function of the pd0/d0 pin. 0: pd0 i/o (port) 1: d0 i/o (bsc) notes: 1. f-ztat version only. setting prohibi ted for the masked rom version and rom less version. 2. the initial value is 1 in the on-chip rom disabled 16-bit external-expansion mode. 3. the initial value is 1 in the on-chip rom disabled external-expansion mode. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 615 of 882 rej09b0108-0400 ? port d control registers l1, l2, h1, and h2 (pdcrl1, pdcrl2, pdcrh1, and pdcrh2) in sh7145 register bit bit name initial value r/w description pdcrl2 7 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. pdcrh1 pdcrh1 15 14 pd31md1 pd31md0 0 0 * 2 r/w r/w pd31 mode select the function of the pd31/d31/ adtrg pin. 00: pd31 i/o (port) 01: d31 i/o (bsc) 10: adtrg input (a/d) 11: setting prohibited pdcrh1 pdcrh1 13 12 pd30md1 pd30md0 0 0 * 2 r/w r/w pd30 mode select the function of the pd30/d30/ irqout pin. 00: pd30 i/o (port) 01: d30 i/o (bsc) 10: irqout output (intc) 11: setting prohibited pdcrh1 pdcrh1 11 10 pd29md1 pd29md0 0 0 * 2 r/w r/w pd29 mode select the function of the pd29/d29/ cs3 pin. 00: pd29 i/o (port) 01: d29 i/o (bsc) 10: cs3 output (bsc) 11: setting prohibited pdcrh1 pdcrh1 9 8 pd28md1 pd28md0 0 0 * 2 r/w r/w pd28 mode select the function of the pd28/d28/ cs2 pin. 00: pd28 i/o (port) 01: d28 i/o (bsc) 10: cs2 output (bsc) 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 616 of 882 rej09b0108-0400 register bit bit name initial value r/w description pdcrh1 pdcrh1 7 6 pd27md1 pd27md0 0 0 * 2 r/w r/w pd27 mode select the function of the pd27/d27/dack1 pin. 00: pd27 i/o (port) 01: d27 i/o (bsc) 10: dack1 output (dmac) 11: setting prohibited pdcrh1 pdcrh1 5 4 pd26md1 pd26md0 0 0 * 2 r/w r/w pd26 mode select the function of the pd26/d26/dack0 pin. 00: pd26 i/o (port) 01: d26 i/o (bsc) 10: dack0 output (dmac) 11: setting prohibited pdcrh1 pdcrh1 3 2 pd25md1 pd25md0 0 0 * 2 r/w r/w pd25 mode select the function of the pd25/d25/ dreq1 pin. 00: pd25 i/o (port) 01: d25 i/o (bsc) 10: dreq1 input (dmac) 11: setting prohibited pdcrh1 pdcrh1 1 0 pd24md1 pd24md0 0 0 * 2 r/w r/w pd24 mode select the function of the pd24/d24/ dreq0 pin. 00: pd24 i/o (port) 01: d24 i/o (bsc) 10: dreq0 input (dmac) 11: setting prohibited pdcrh2 pdcrh2 15 14 pd23md1 pd23md0 0 0 * 2 r/w r/w pd23 mode select the function of the pd23/d23/ irq7 / audsync pin. 00: pd23 i/o (port) 01: d23 i/o (bsc) 10: irq7 input (intc) 11: audsync i/o (aud) * 1 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 617 of 882 rej09b0108-0400 register bit bit name initial value r/w description pdcrh2 pdcrh2 13 12 pd22md1 pd22md0 0 0 * 2 r/w r/w pd22 mode select the function of the pd22/d22/ irq6 /audck pin. 00: pd22 i/o (port) 01: d22 i/o (bsc) 10: irq6 input (intc) 11: audck i/o (aud) * 1 pdcrh2 pdcrh2 11 10 pd21md1 pd21md0 0 0 * 2 r/w r/w pd21 mode select the function of the pd21/d21/ irq5 /audmd pin. 00: pd21 i/o (port) 01: d21 i/o (bsc) 10: irq5 input (intc) 11: audmd input (aud) * 1 pdcrh2 pdcrh2 9 8 pd20md1 pd20md0 0 0 * 2 r/w r/w pd20 mode select the function of the pd20/d20/ irq4 / audrst pin. 00: pd20 i/o (port) 01: d20 i/o (bsc) 10: irq4 input (intc) 11: audrst input (aud) * 1 pdcrh2 pdcrh2 7 6 pd19md1 pd19md0 0 0 * 2 r/w r/w pd19 mode select the function of the pd19/d19/ irq3 /audata3 pin. 00: pd19 i/o (port) 01: d19 i/o (bsc) 10: irq3 input (intc) 11: audata3 i/o (aud) * 1 pdcrh2 pdcrh2 5 4 pd18md1 pd18md0 0 0 * 2 r/w r/w pd18 mode select the function of the pd18/d18/ irq2 /audata2 pin. 00: pd18 i/o (port) 01: d18 i/o (bsc) 10: irq2 input (intc) 11: audata2 i/o (aud) * 1 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 618 of 882 rej09b0108-0400 register bit bit name initial value r/w description pdcrh2 pdcrh2 3 2 pd17md1 pd17md0 0 0 * 2 r/w r/w pd17 mode select the function of the pd17/d17/ irq1 /audata1 pin. 00: pd17 i/o (port) 01: d17 i/o (bsc) 10: irq1 input (intc) 11: audata1 i/o (aud) * 1 pdcrh2 pdcrh2 1 0 pd16md1 pd16md0 0 0 * 2 r/w r/w pd16 mode select the function of the pd16/d16/ irq0 /audata0 pin. 00: pd16 i/o (port) 01: d16 i/o (bsc) 10: irq0 input (intc) 11: audata0 i/o (aud) * 1 pdcrl2 pdcrl1 15 15 pd15md1 pd15md0 0 0 * 3 r/w r/w pd15 mode select the function of the pd15/d15 pin. 00: pd15 i/o (port) 01: d15 i/o (bsc) 10: setting prohibited 11: setting prohibited pdcrl2 pdcrl1 14 14 pd14md1 pd14md0 0 0 * 3 r/w r/w pd14 mode select the function of the pd14/d14 pin. 00: pd14 i/o (port) 01: d14 i/o (bsc) 10: setting prohibited 11: setting prohibited pdcrl2 pdcrl1 13 13 pd13md1 pd13md0 0 0 * 3 r/w r/w pd13 mode select the function of the pd13/d13 pin. 00: pd13 i/o (port) 01: d13 i/o (bsc) 10: setting prohibited 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 619 of 882 rej09b0108-0400 register bit bit name initial value r/w description pdcrl2 pdcrl1 12 12 pd12md1 pd12md0 0 0 * 3 r/w r/w pd12 mode select the function of the pd12/d12 pin. 00: pd12 i/o (port) 01: d12 i/o (bsc) 10: setting prohibited 11: setting prohibited pdcrl2 pdcrl1 11 11 pd11md1 pd11md0 0 0 * 3 r/w r/w pd11 mode select the function of the pd11/d11 pin. 00: pd11 i/o (port) 01: d11 i/o (bsc) 10: setting prohibited 11: setting prohibited pdcrl2 pdcrl1 10 10 pd10md1 pd10md0 0 0 * 3 r/w r/w pd10 mode select the function of the pd10/d10 pin. 00: pd10 i/o (port) 01: d10 i/o (bsc) 10: setting prohibited 11: setting prohibited pdcrl2 pdcrl1 9 9 pd9md1 pd9md0 0 0 * 3 r/w r/w pd9 mode select the function of the pd9/d9 pin. 00: pd9 i/o (port) 01: d9 i/o (bsc) 10: setting prohibited 11: setting prohibited pdcrl2 pdcrl1 8 8 pd8md1 pd8md0 0 0 * 3 r/w r/w pd8 mode select the function of the pd8/d8 pin. 00: pd8 i/o (port) 01: d8 i/o (bsc) 10: setting prohibited 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 620 of 882 rej09b0108-0400 register bit bit name initial value r/w description pdcrl1 7 pd7md 0 * 3 r/w pd7 mode selects the function of the pd7/d7 pin. 0: pd7 i/o (port) 1: d7 i/o (bsc) pdcrl1 6 pd6md 0 * 3 r/w pd6 mode selects the function of the pd6/d6 pin. 0: pd6 i/o (port) 1: d6 i/o (bsc) pdcrl1 5 pd5md 0 * 3 r/w pd5 mode selects the function of the pd5/d5 pin. 0: pd5 i/o (port) 1: d5 i/o (bsc) pdcrl1 4 pd4md 0 * 3 r/w pd4 mode selects the function of the pd4/d4 pin. 0: pd4 i/o (port) 1: d4 i/o (bsc) pdcrl1 3 pd3md 0 * 3 r/w pd3 mode selects the function of the pd3/d3 pin. 0: pd3 i/o (port) 1: d3 i/o (bsc) pdcrl1 2 pd2md 0 * 3 r/w pd2 mode selects the function of the pd2/d2 pin. 0: pd2 i/o (port) 1: d2 i/o (bsc) pdcrl1 1 pd1md 0 * 3 r/w pd1 mode selects the function of the pd1/d1 pin. 0: pd1 i/o (port) 1: d1 i/o (bsc) pdcrl1 0 pd0md 0 * 3 r/w pd0 mode selects the function of the pd0/d0 pin. 0: pd0 i/o (port) 1: d0 i/o (bsc) notes: 1. f-ztat version only. setting prohibi ted for the masked rom version and rom less version. 2. the initial value is 1 in the on-chip rom disabled 32-bit external-expansion mode. 3. the initial value is 1 in the on-chip rom disabled external-expansion mode. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 621 of 882 rej09b0108-0400 17.1.9 port e i/o register l (peiorl) the port e i/o register l (peiorl) is a 16-bit readab le/writable register that is used to set the pins on port e as inputs or outputs. bits pe15ior to pe0ior correspond to pins pe15 to pe0 (names of multiplexed pins are here given as port na mes and pin numbers alone). peiorl is enabled when the port e pins are functioning as general-purpose inputs/outputs (pe15 to pd0), tioc pins are functioning as inputs/outputs of mtu, and sck2 and sck3 pins are functioning as inputs/outputs of sci. in other states, peiorl is disabled. a given pin on port e will be an output pin if the corresponding peiorl bit is set to 1, and an input pin if the bit is cleared to 0. the initial value of peiorl is h'0000. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 622 of 882 rej09b0108-0400 17.1.10 port e control registers l1, l2 (pecrl1, pecrl2) the port e control registers l1 and l2 (pec rl1 and pecrl2) are 16-b it readable/writable registers that are used to select the multiplexed pin function of the pins on port e. ? port e control registers l1 and l2 (pecrl1 and pecrl2) in sh7144 register bit bit name initial value r/w description pecrl1 pecrl1 15 14 pe15md1 pe15md0 0 0 r/w r/w pe15 mode select the function of the pe15/tioc4d/dack1/ irqout pin. 00: pe15 i/o (port) 01: tioc4d i/o (mtu) 10: dack1 output (dmac) 11: irqout output (intc) pecrl1 pecrl1 13 12 pe14md1 pe14md0 0 0 r/w r/w pe14 mode select the function of the pe14/tioc4c/dack0 pin. 00: pe14 i/o (port) 01: tioc4c i/o (mtu) 10: dack0 output (dmac) 11: setting prohibited pecrl1 pecrl1 11 10 pe13md1 pe13md0 0 0 r/w r/w pe13 mode select the function of the pe13/tioc4b/ mres pin. 00: pe13 i/o (port) 01: tioc4b i/o (mtu) 10: mres input (intc) 11: setting prohibited pecrl1 pecrl1 9 8 pe12md1 pe12md0 0 0 r/w r/w pe12 mode select the function of the pe12/tioc4a/txd3 pin. 00: pe12 i/o (port) 01: tioc4a i/o (mtu) 10: setting prohibited 11: txd3 output (sci) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 623 of 882 rej09b0108-0400 register bit bit name initial value r/w description pecrl1 pecrl1 7 6 pe11md1 pe11md0 0 0 r/w r/w pe11 mode select the function of the pe11/tioc3d/rxd3 pin. 00: pe11 i/o (port) 01: tioc3d i/o (mtu) 10: setting prohibited 11: rxd3 input (sci) pecrl1 pecrl1 5 4 pe10md1 pe10md0 0 0 r/w r/w pe10 mode select the function of the pe10/tioc3c/txd2 pin. 00: pe10 i/o (port) 01: tioc3c i/o (mtu) 10: txd2 output (sci) 11: setting prohibited pecrl1 pecrl1 3 2 pe9md1 pe9md0 0 0 r/w r/w pe9 mode select the function of the pe9/tioc3b/sck3 pin. 00: pe9 i/o (port) 01: tioc3b i/o (mtu) 10: setting prohibited 11: sck3 i/o (sci) pecrl1 pecrl1 1 0 pe8md1 pe8md0 0 0 r/w r/w pe8 mode select the function of the pe8/tioc3a/sck2 pin. 00: pe8 i/o (port) 01: tioc3a i/o (mtu) 10: sck2 i/o (sci) 11: setting prohibited pecrl2 pecrl2 15 14 pe7md1 pe7md0 0 0 r/w r/w pe7 mode select the function of the pe7/tioc2b/rxd2 pin. 00: pe7 i/o (port) 01: tioc2b i/o (mtu) 10: rxd2 input (sci) 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 624 of 882 rej09b0108-0400 register bit bit name initial value r/w description pecrl2 pecrl2 13 12 pe6md1 pe6md0 0 0 r/w r/w pe6 mode select the function of the pe6/tioc2a/sck3 pin. 00: pe6 i/o (port) 01: tioc2a i/o (mtu) 10: sck3 i/o (sci) 11: setting prohibited pecrl2 pecrl2 11 10 pe5md1 pe5md0 0 0 r/w r/w pe5 mode select the function of the pe5/tioc1b/txd3 pin. 00: pe5 i/o (port) 01: tioc1b i/o (mtu) 10: txd3 output (sci) 11: setting prohibited pecrl2 pecrl2 9 8 pe4md1 pe4md0 0 0 r/w r/w pe4 mode select the function of the pe4/tioc1a/rxd3/tck pin. fixed to tck input when using e10a (in dbgmd = high). * 00: pe4 i/o (port) 01: tioc1a i/o (mtu) 10: rxd3 input (sci) 11: setting prohibited pecrl2 pecrl2 7 6 pe3md1 pe3md0 0 0 r/w r/w pe3 mode select the function of the pe3/tioc0d/drak1/tdo pin. fixed to tdo output when using e10a (in dbgmd = high). * 00: pe3 i/o (port) 01: tioc0d i/o (mtu) 10: drak1 output (dmac) 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 625 of 882 rej09b0108-0400 register bit bit name initial value r/w description pecrl2 pecrl2 5 4 pe2md1 pe2md0 0 0 r/w r/w pe2 mode select the function of the pe2/tioc0c/ dreq1 /tdi pin. fixed to tdi input when using e10a (in dbgmd = high). * 00: pe2 i/o (port) 01: tioc0c i/o (mtu) 10: dreq1 input (dmac) 11: setting prohibited pecrl2 pecrl2 3 2 pe1md1 pe1md0 0 0 r/w r/w pe1 mode select the function of the pe1/tioc0b/drak0/ trst pin. fixed to trst input when using e10a (in dbgmd = high). * 00: pe1 i/o (port) 01: tioc0b i/o (mtu) 10: drak0 output (dmac) 11: setting prohibited pecrl2 pecrl2 1 0 pe0md1 pe0md0 0 0 r/w r/w pe0 mode select the function of the pe0/tioc0a/ dreq0 /tms pin. fixed to tms input when using e10a (in dbgmd = high). * 00: pe0 i/o (port) 01: tioc0a i/o (mtu) 10: dreq0 input (dmac) 11: setting prohibited note: * f-ztat version only. setting prohibited for the masked rom version and rom less version. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 626 of 882 rej09b0108-0400 ? port e control registers l1 and l2 (pecrl1 and pecrl2) in sh7145 register bit bit name initial value r/w description pecrl1 pecrl1 15 14 pe15md1 pe15md0 0 0 r/w r/w pe15 mode select the function of the pe15/tioc4d/dack1/ irqout pin. 00: pe15 i/o (port) 01: tioc4d i/o (mtu) 10: dack1 output (dmac) 11: irqout output (intc) pecrl1 pecrl1 13 12 pe14md1 pe14md0 0 0 r/w r/w pe14 mode select the function of the pe14/tioc4c/dack0 pin. 00: pe14 i/o (port) 01: tioc4c i/o (mtu) 10: dack0 output (dmac) 11: setting prohibited pecrl1 pecrl1 11 10 pe13md1 pe13md0 0 0 r/w r/w pe13 mode select the function of the pe13/tioc4b/ mres pin. 00: pe13 i/o (port) 01: tioc4b i/o (mtu) 10: mres input (intc) 11: setting prohibited pecrl1 pecrl1 9 8 pe12md1 pe12md0 0 0 r/w r/w pe12 mode select the function of the pe12/tioc4a/tck/txd3 pin. fixed to tck input when using e10a (in dbgmd = high). * 00: pe12 i/o (port) 01: tioc4a i/o (mtu) 10: setting prohibited 11: txd3 output (sci) 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 627 of 882 rej09b0108-0400 register bit bit name initial value r/w description pecrl1 pecrl1 7 6 pe11md1 pe11md0 0 0 r/w r/w pe11 mode select the function of the pe11/tioc3d/tdo/rxd3 pin. fixed to tdo output when using e10a (in dbgmd = high). * 00: pe11 i/o (port) 01: tioc3d i/o (mtu) 10: setting prohibited 11: rxd3 input (sci) pecrl1 pecrl1 5 4 pe10md1 pe10md0 0 0 r/w r/w pe10 mode select the function of the pe10/tioc3c/txd2/tdi pin. fixed to tdi input when using e10a (in dbgmd = high). * 00: pe10 i/o (port) 01: tioc3c i/o (mtu) 10: txd2 output (sci) 11: setting prohibited pecrl1 pecrl1 3 2 pe9md1 pe9md0 0 0 r/w r/w pe9 mode select the function of the pe9/tioc3b/ trst /sck3 pin. fixed to trst input when using e10a (in dbgmd = high). * 00: pe9 i/o (port) 01: tioc3b i/o (mtu) 10 setting prohibited 11: sck3 i/o (sci) pecrl1 pecrl1 1 0 pe8md1 pe8md0 0 0 r/w r/w pe8 mode select the function of the pe8/tioc3a/sck2/tms pin. fixed to tms input when using e10a (in dbgmd = high). * 00: pe8 i/o (port) 01: tioc3a i/o (mtu) 10: sck2 i/o (sci) 11: setting prohibited 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 628 of 882 rej09b0108-0400 register bit bit name initial value r/w description pecrl2 pecrl2 15 14 pe7md1 pe7md0 0 0 r/w r/w pe7 mode select the function of the pe7/tioc2b/rxd2 pin. 00: pe7 i/o (port) 01: tioc2b i/o (mtu) 10: rxd2 input (sci) 11: setting prohibited pecrl2 pecrl2 13 12 pe6md1 pe6md0 0 0 r/w r/w pe6 mode select the function of the pe6/tioc2a/sck3/audata0 pin. 00: pe6 i/o (port) 01: tioc2a i/o (mtu) 10: sck3 i/o (sci) 11: audata0 i/o (aud) * pecrl2 pecrl2 11 10 pe5md1 pe5md0 0 0 r/w r/w pe5 mode select the function of the pe5/tioc1b/txd3/audata1 pin. 00: pe5 i/o (port) 01: tioc1b i/o (mtu) 10: txd3 output (sci) 11: audata1 i/o (aud) * pecrl2 pecrl2 9 8 pe4md1 pe4md0 0 0 r/w r/w pe4 mode select the function of the pe4/tioc1a/rxd3/audata2 pin. 00: pe4 i/o (port) 01: tioc1a i/o (mtu) 10: rxd3 input (sci) 11: audata2 i/o (aud) * pecrl2 pecrl2 7 6 pe3md1 pe3md0 0 0 r/w r/w pe3 mode select the function of the pe3/tioc0d/drak1/audata3 pin. 00: pe3 i/o (port) 01: tioc0d i/o (mtu) 10: drak1 output (dmac) 11: audata3 i/o (aud) * 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 629 of 882 rej09b0108-0400 register bit bit name initial value r/w description pecrl2 pecrl2 5 4 pe2md1 pe2md0 0 0 r/w r/w pe2 mode select the function of the pe2/tioc0c/ dreq1 / audrst pin. 00: pe2 i/o (port) 01: tioc0c i/o (mtu) 10: dreq1 input (dmac) 11: audrst input (aud) * pecrl2 pecrl2 3 2 pe1md1 pe1md0 0 0 r/w r/w pe1 mode select the function of the pe1/tioc0b/drak0/audmd pin. 00: pe1 i/o (port) 01: tioc0b i/o (mtu) 10: drak0 output (dmac) 11: audmd input (aud) * pecrl2 pecrl2 1 0 pe0md1 pe0md0 0 0 r/w r/w pe0 mode select the function of the pe0/tioc0a/ dreq0 /audck pin. 00: pe0 i/o (port) 01: tioc0a i/o (mtu) 10: dreq0 input (dmac) 11: audck i/o (aud) * note: * f-ztat version only. setting prohibited for the masked rom version and rom less version. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 630 of 882 rej09b0108-0400 17.1.11 high-current port control register (ppcr ) the high-current port control register (ppcr) is an 8-bit readable/writable register that is used to control six pins (pe9/tioc3b/sck3/ trst *, pe11/tioc3d/rxd3/tdo*, pe12/tioc4a/txd3/tck*, pe13/tioc4b/ mres , pe14/tioc4c/dack0, pe15/tioc4d/dack1/ irqout ) of the high-current ports. this register is not supported in the emulator. b its are always read as u ndefined in the emulator. note: * only in the sh7145 bit bit name initial value r/w description 7 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 mzize 0 r/w high-current port high-impedance this bit selects whether or not the high-current ports are set to high-impedance regardless of the pfc setting when detecting oscillation halt or in software standby mode. 0: set to high-impedance 1: not set to high-impedance if this bit is set to 1, the pin state is retained when detecting oscillation halt. for the pin state in software standby mode, refer to appendix a, pin states. 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 631 of 882 rej09b0108-0400 17.2 usage notes 1. in this lsi, the same function is available as a multiplexed function on multiple pins. this approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. if two or more pins are specified for one function, however, there are two cautions shown below. ? when the pin function is input signals input to several pins are formed as one signal through or or and logic and the signal is transmitted into the ls i. therefore, a signal that differs from the input signals may be transmitted to the lsi depending on the input signals in other pins that have the same functions. table 17.15 shows the transmit forms of input functions allocated to several pins. when using one of the functions shown below in multiple pins, use it with care of signal polarity consider ing the transmit forms. table 17.15 transmit forms of input functions allocated to multiple pins product or type and type sh7144 sck3, rxd3 irq0 to irq3 , dreq0 , dreq1 sh7145 sck3, rxd3, audmd * , audata0 to audata3 * irq0 to irq7 , dreq0 , dreq1 , breq , wait , adtrg , audrst * , audsync * , audck * note: * f-ztat version only or type: signals input to several pins are formed as one signal through or logic and the signal is transmitted into the lsi. and type: signals input to several pins are formed as one signal through and logic and the signal is transmitted into the lsi. ? when the pin function is output each selected pin can output the same function. 2. when the port input is switched from a low level to the dreq or the irq edge for the pins that are multiplexed with input/output and dreq or irq , the corresponding edge is detected. 3. do not set functions other than those specified in tables 17.13 and 17.14. otherwise, correct operation cannot be guaranteed. 4. when pin functions are selected, set the port i/o registers (pbior and pdiorl) after setting the port control registers (pbcr1 , pbcr2, pdcrl1, and pdcrl2). however, when selecting pin functions that are multiplexed with port a, port c, pd31 to pd16 of port d, and port e, no strict attention is required in setting the order of port control registers (pacrh, pacrl1, pacrl2, p ccr, pdcrh1, pdcrh2, pecrl1, and pecrl2) and port i/o registers (paiorh, paiorl, pcior, pdiorh, and peiorl). 17. pin function controller (pfc) rev.4.00 mar. 27, 2008 page 632 of 882 rej09b0108-0400 5. when the system uses the exte rnal space, the data i/o pins must be set as follows according to the bus sizes in the cs space set by the bus control register 1 (bcr1). ? when the cs space is the byte size (8-bit size), set all pins, d7 to d0 , as data i/o pins. ? when the cs space is the word size (16-bit size), set all pins, d15 to d0, as data i/o pins. ? when the cs space is the longword size (32-bit size), set all pins, d31 to d0, as data i/o pins. if the contents in the external space are read by settings other than above ways, no correct data can be latched. this note applies to entire space, cs0 to cs7. 6. if a power-on reset is input to the res pin in the state where the pin is a general output pin and set to output 1 (that is, the port control register is in the general i/o state, port i/o register is 1, and port data register is 1), a low level may occur in the pin at a power-on reset input. to avoid this low level from occurring, input a power-on reset after clearing the port i/o register to 0 (general input). the low level above will not occur when an internal power-on reset is input due to a wdt overflow. 18. i/o ports rev.4.00 mar. 27, 2008 page 633 of 882 rej09b0108-0400 section 18 i/o ports the sh7144 has six ports: a to f. ports a, c, d, and e are 16-bit ports, and port b is a 10-bit port. port f is an 8-bit input-only port. the sh7145 has six ports: a to f. port a is a 24-bit port, port b is a 10-bit port, port c is a 16-bit port, port d is a 32-bit port, and port e is a 16-bit port. port f is an 8-bit input-only port. all the port pins are multiplexed as general input/output pins and special function pins. the functions of the multiplex pins are selected by means of the pin function controller (pfc). each port is provided with a data register for storing the pin data. 18. i/o ports rev.4.00 mar. 27, 2008 page 634 of 882 rej09b0108-0400 18.1 port a port a in the sh7144 is an input/output port with the 16 pins shown in figure 18.1. pa15 (i/o) / ck (output) pa14 (i/o) / rd (output) pa13 (i/o) / wrh (output) pa12 (i/o) / wrl (output) pa11 (i/o) / cs1 (output) pa10 (i/o) / cs0 (output) pa9 (i/o) / tclkd (input) / irq3 (input) pa8 (i/o) / tclkc (input) / irq2 (input) pa7 (i/o) / tclkb (input) / cs3 (output) pa6 (i/o) / tclka (input) / cs2 (output) pa5 (i/o) / sck1 (i/o) / dreq1 (input) / irq1 (input) pa4 (i/o) / txd1 (output) pa3 (i/o) / rxd1 (input) pa2 (i/o) / sck0 (i/o) / dreq0 (input) / irq0 (input) pa1 (i/o) / txd0 (output) pa0 (i/o) / rxd0 (input) port a figure 18.1 port a (sh7144) 18. i/o ports rev.4.00 mar. 27, 2008 page 635 of 882 rej09b0108-0400 port a in the sh7145 is an input/output port with the 24 pins shown in figure 18.2 pa15 (i/o) / ck (output) pa14 (i/o) / rd (output) pa21 (i/o) / cs5 (output) * 2 pa20 (i/o) / cs4 (output) * 2 pa13 (i/o) / wrh (output) pa23 (i/o) / wrhh (output) pa22 (i/o) / wrhl (output) pa12 (i/o) / wrl (output) pa11 (i/o) / cs1 (output) pa10 (i/o) / cs0 (output) pa9 (i/o) / tclkd (input) / irq3 (input) pa8 (i/o) / tclkc (input) / irq2 (input) pa7 (i/o) / tclkb (input) / cs3 (output) pa6 (i/o) / tclka (input) / cs2 (output) pa19 (i/o) / back (output) / drak1 (output) pa18 (i/o) / breq (input) / drak0 (output) pa17 (i/o) / wait (input) pa16 (i/o) / audsync (i/o) pa5 (i/o) / sck1 (i/o) / dreq1 (input) / irq1 (input) pa4 (i/o) / txd1 (output) pa3 (i/o) / rxd1 (input) pa2 (i/o) / sck0 (i/o) / dreq0 (input) / irq0 (input) pa1 (i/o) / txd0 (output) pa0 (i/o) / rxd0 (input) port a * 1 notes: 1. only for the f-ztat version (no correspondin g function in the masked rom version and rom less version). 2. only for the masked rom version and rom less version (no correspondin g function in the f-ztat version and emulator). figure 18.2 port a (sh7145) 18. i/o ports rev.4.00 mar. 27, 2008 page 636 of 882 rej09b0108-0400 18.1.1 register descriptions port a is a 16-bit input/output port in the sh7144; a 24-bit input/output port in the sh7145. port a has the following registers. for details on regi ster addresses and regist er states during each processing, refer to section 25, list of registers. ? port a data register h (padrh) ? port a data register l (padrl) 18.1.2 port a data registers h and l (padrh and padrl) the port a data registers h and l (padrh and padrl) are 16-bit readab le/writable registers that store port a data. bits pa15dr to pa0dr correspond to pins pa15 to pa0 (multiplexed functions omitted here) in the sh7144. bits pa23dr to pa0dr correspond to pins pa23 to pa0 (multiplexed functions omitted here) in the sh7145. when a pin functions is a general output, if a value is written to padrh or padrl, that value is output directly from the pin, and if padrh or padrl is read, the register value is returned directly regardless of the pin state. when a pin functions is a general input, if padrh or padrl is read, the pin state, not the register value, is returned directly. if a value is written to padrh or padrl, although that value is written into padrh or padrl, it does not affect the pin state. table 18.1 summarizes port a data register l read/write operations. 18. i/o ports rev.4.00 mar. 27, 2008 page 637 of 882 rej09b0108-0400 ? padrh bit bit name initial value r/w description 15 to 8 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 7 pa23dr 0 r/w see table 18.1 * 6 pa22dr 0 r/w 5 pa21dr 0 r/w 4 pa20dr 0 r/w 3 pa19dr 0 r/w 2 pa18dr 0 r/w 1 pa17dr 0 r/w 0 pa16dr 0 r/w note: * these bits are reserved in the sh7144. t hey are always read as 0 and the write value should always be 0. ? padrl bit bit name initial value r/w description 15 pa15dr 0 r/w see table 18.1 14 pa14dr 0 r/w 13 pa13dr 0 r/w 12 pa12dr 0 r/w 11 pa11dr 0 r/w 10 pa10dr 0 r/w 9 pa9dr 0 r/w 8 pa8dr 0 r/w 7 pa7dr 0 r/w 6 pa6dr 0 r/w 5 pa5dr 0 r/w 4 pa4dr 0 r/w 3 pa3dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w 0 pa0dr 0 r/w 18. i/o ports rev.4.00 mar. 27, 2008 page 638 of 882 rej09b0108-0400 table 18.1 port a data register (padr) read/write operations ? padrh bits 7 to 0 and padrl bits 15 to 0 paiorl, h pin function read write 0 general input pin state can writ e to padrh and padrl, but it has no effect on pin state other than general input pin state can write to padrh and padrl, but it has no effect on pin state 1 general output padrh or l value value written is output from pin other than general output padrh or l value can write to padrh and padrl, but it has no effect on pin state 18. i/o ports rev.4.00 mar. 27, 2008 page 639 of 882 rej09b0108-0400 18.2 port b port b is an input/output port with the 10 pins shown in figure 18.3. pb3 (i/o) / irq1 (input) / poe1 (input) / sda0 (i/o) pb4 (i/o) / irq2 (input) / poe2 (input) cs6 (output) * pb5 (i/o) / irq3 (input) / poe3 (input) cs7 (output) * pb6 (i/o) / irq4 (input) / a18 (output) / back (output) pb7 (i/o) / irq5 (input) / a19 (output) / breq (input) pb8 (i/o) / irq6 (input) / a20 (output) / wait (input) pb9 (i/o) / irq7 (input) / a21 (output) / adtrg (input) pb2 (i/o) / irq0 (input) / poe0 (input) / scl0 (i/o) pb1 (i/o) / a17 (output) pb0 (i/o) / a16 (output) port b note: * only for the masked rom version and rom less version (no correspondin g function in the f-ztat version and emulator). figure 18.3 port b 18.2.1 register descriptions port b is a 10-bit input/output port. port b has the following register. for details on register addresses and register states during each proce ssing, refer to section 25 , list of registers. ? port b data register (pbdr) 18. i/o ports rev.4.00 mar. 27, 2008 page 640 of 882 rej09b0108-0400 18.2.2 port b data register (pbdr) the port b data register (pbdr) is a 16-bit readab le/writable register that stores port b data. bits pb9dr to pb0dr correspond to pins pb9 to pb0 (multiplexed functions omitted here). when a pin functions is a general output, if a value is written to pbdr, that value is output directly from the pin, and if pbdr is read, the register value is returned directly regardless of the pin state. when a pin functions is a general input, if pbdr is read, the pin state, not the register value, is returned directly. if a value is written to pbdr, although that value is written into pbdr, it does not affect the pin state. tabl e 18.2 summarizes port b data register read/write operations. bit bit name initial value r/w description 15 to 10 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 9 pb9dr 0 r/w see table 18.2 8 pb8dr 0 r/w 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w 0 pb0dr 0 r/w 18. i/o ports rev.4.00 mar. 27, 2008 page 641 of 882 rej09b0108-0400 table 18.2 port b data regist er (pbdr) read/write operations ? bits 9 to 0 pbior pin function read write 0 general input pin state can write to pbdr, but it has no effect on pin state other than general input pin state can write to pbdr, but it has no effect on pin state 1 general output pbdr value valu e written is output from pin other than general output pbdr value can write to pbdr, but it has no effect on pin state 18. i/o ports rev.4.00 mar. 27, 2008 page 642 of 882 rej09b0108-0400 18.3 port c port c is an input/output port with 16 pins shown in figure 18.4. pc15 (i/o) / a15 (output) pc14 (i/o) / a14 (output) pc13 (i/o) / a13 (output) pc12 (i/o) / a12 (output) pc11 (i/o) / a11 (output) pc10 (i/o) / a10 (output) pc9 (i/o) / a9 (output) pc8 (i/o) / a8 (output) pc7 (i/o) / a7 (output) pc6 (i/o) / a6 (output) pc5 (i/o) / a5 (output) pc4 (i/o) / a4 (output) pc3 (i/o) / a3 (output) pc2 (i/o) / a2 (output) pc1 (i/o) / a1 (output) pc0 (i/o) / a0 (output) port c figure 18.4 port c 18.3.1 register descriptions port c is a 16-bit input/output port. port c has the following register. for details on register addresses and register states during each proce ssing, refer to section 25, list of registers. ? port c data register (pcdr) 18. i/o ports rev.4.00 mar. 27, 2008 page 643 of 882 rej09b0108-0400 18.3.2 port c data register (pcdr) the port c data register (pcdr) is a 16-bit readab le/writable register that stores port c data. bits pc15dr to pc0dr correspond to pins pc15 to pc0 (multiplexed functions omitted here). when a pin functions is a general output, if a value is written to pcdr, that value is output directly from the pin, and if pcdr is read, the register value is returned directly regardless of the pin state. when a pin function is a general input, if pcdr is read, the pin state, not the register value, is returned directly. if a value is written to pcdr, although that value is written into pcdr, it does not affect the pin state. tabl e 18.3 summarizes port c data register read/write operations. ? pcdr bit bit name initial value r/w description 15 pc15dr 0 r/w see table 18.3 14 pc14dr 0 r/w 13 pc13dr 0 r/w 12 pc12dr 0 r/w 11 pc11dr 0 r/w 10 pc10dr 0 r/w 9 pc9dr 0 r/w 8 pc8dr 0 r/w 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w 0 pc0dr 0 r/w 18. i/o ports rev.4.00 mar. 27, 2008 page 644 of 882 rej09b0108-0400 table 18.3 port c data register (pcdr) read/write operations ? bits 15 to 0 pcior pin function read write 0 general input pin state can write to pcdr, but it has no effect on pin state other than general input pin state can write to pcdr, but it has no effect on pin state 1 general output pcdr value valu e written is output from pin other than general output pcdr value can write to pcdr, but it has no effect on pin state 18. i/o ports rev.4.00 mar. 27, 2008 page 645 of 882 rej09b0108-0400 18.4 port d port d of the sh7144 is an input/output port with 16 pins shown in figure 18.5. pd15 (i/o) / d15 (i/o) / audsync (i/o) * pd14 (i/o) / d14 (i/o) / audck (i/o) * pd13 (i/o) / d13 (i/o) / audmd (input) * pd12 (i/o) /d12 (i/o) / audrst (input) * pd11 (i/o) / d11 (i/o) / audata3 (i/o) * pd10 (i/o) / d10 (i/o) / audata2 (i/o) * pd9 (i/o) / d9 (i/o) / audata1 (i/o) * pd8 (i/o) / d8 (i/o) / audata0 (i/o) * pd7 (i/o) / d7 (i/o) pd6 (i/o) / d6 (i/o) pd5 (i/o) / d5 (i/o) pd4 (i/o) / d4 (i/o) pd3 (i/o) / d3 (i/o) pd2 (i/o) / d2 (i/o) pd1 (i/o) / d1 (i/o) pd0 (i/o) / d0 (i/o) port d note: * only for the f-ztat version (no correspondin g function in the masked rom version and rom less version). figure 18.5 port d (sh7144) 18. i/o ports rev.4.00 mar. 27, 2008 page 646 of 882 rej09b0108-0400 port d of the sh7145 is an input/output port with 32 pins shown in figure 18.6. pd25 (i/o) / d25 (i/o) / dreq1 (input) pd24 (i/o) / d24 (i/o) / dreq0 (input) pd23 (i/o) / d23 (i/o) / irq7 (input) / audsync (i/o) * pd22 (i/o) / d22 (i/o) / irq6 (input) / audck (i/o) * pd21 (i/o) / d21 (i/o) / irq5 (input) / audmd (input) * pd20 (i/o) / d20 (i/o) / irq4 (input) / audrst (input) * pd19 (i/o) / d19 (i/o) / irq3 (input) / audata3 (i/o) * pd31 (i/o) / d31 (i/o) / adtrg (input) pd30 (i/o) / d30 (i/o) / irqout (output) pd29 (i/o) / d29 (i/o) / cs3 (output) pd28 (i/o) / d28 (i/o) / cs2 (output) pd27 (i/o) / d27 (i/o) / dack1 (output) pd26 (i/o) / d26 (i/o) / dack0 (output) pd18 (i/o) / d18 (i/o) / irq2 (input) / audata2 (i/o) * pd17 (i/o) / d17 (i/o) / irq1 (input) / audata1 (i/o) * pd16 (i/o) / d16 (i/o) / irq0 (input) / audata0 (i/o) * pd15 (i/o) / d15 (i/o) pd14 (i/o) / d14 (i/o) pd13 (i/o) / d13 (i/o) pd12 (i/o) / d12 (i/o) pd11 (i/o) / d11 (i/o) pd10 (i/o) / d10 (i/o) pd9 (i/o) / d9 (i/o) pd8 (i/o) / d8 (i/o) pd7 (i/o) / d7 (i/o) pd6 (i/o) / d6 (i/o) pd5 (i/o) / d5 (i/o) pd4 (i/o) / d4 (i/o) pd3 (i/o) / d3 (i/o) pd2 (i/o) / d2 (i/o) pd1 (i/o) / d1 (i/o) pd0 (i/o) / d0 (i/o) note: * only for the f-ztat version (no correspondin g function in the masked rom version and rom less version). port d figure 18.6 port d (sh7145) 18. i/o ports rev.4.00 mar. 27, 2008 page 647 of 882 rej09b0108-0400 18.4.1 register descriptions port d is a 16-bit input/output port in the sh7144; a 32-bit input/output port in the sh7145. port d has the following registers. for details on regi ster addresses and regist er states during each processing, refer to section 25, list of registers. ? port d data register h (pddrh) ? port d data register l (pddrl) 18.4.2 port d data registers h and l (pddrh and pddrl) the port d data registers h and l (pddrh and pd drl) are 16-bit readable/writable registers that store port d data. bits pd15dr to pd0dr correspond to pins pd15 to pd0 (multiplexed functions omitted here) in the sh7144. bits pd31dr to pd0dr correspond to pins pd31 to pd0 (multiplexed functions omitted here) in the sh7145. when a pin functions is a general output, if a value is written to pddrh or pddrl, that value is output directly from the pin, and if pddrh or pddrl is read, the register value is returned directly regardless of the pin state. when a pin functions is a general input, if pddrh or pddrl is read, the pin state, not the register value, is returned directly. if a value is written to pddrh or pddrl, although that value is written into pddrh or pddrl, it does not affect the pin state. table 18.4 summarizes port d data register l read/write operations. 18. i/o ports rev.4.00 mar. 27, 2008 page 648 of 882 rej09b0108-0400 ? pddrh bit bit name initial value r/w description 15 pd31dr 0 r/w see table 18.4 * 14 pd30dr 0 r/w 13 pd29dr 0 r/w 12 pd28dr 0 r/w 11 pd27dr 0 r/w 10 pd26dr 0 r/w 9 pd25dr 0 r/w 8 pd24dr 0 r/w 7 pd23dr 0 r/w 6 pd22dr 0 r/w 5 pd21dr 0 r/w 4 pd20dr 0 r/w 3 pd19dr 0 r/w 2 pd18dr 0 r/w 1 pd17dr 0 r/w 0 pd16dr 0 r/w note: * these bits are reserved in the sh7144. t hey are always read as 0 and the write value should always be 0. 18. i/o ports rev.4.00 mar. 27, 2008 page 649 of 882 rej09b0108-0400 ? pddrl bit bit name initial value r/w description 15 pd15dr 0 r/w see table 18.4 14 pd14dr 0 r/w 13 pd13dr 0 r/w 12 pd12dr 0 r/w 11 pd11dr 0 r/w 10 pd10dr 0 r/w 9 pd9dr 0 r/w 8 pd8dr 0 r/w 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w 0 pd0dr 0 r/w table 18.4 port d data register (pddr) read/write operations ? pddrh bits 15 to 0 and pddrl bits 15 to 0 pdiorl, h pin function read write 0 general input pin state can write to pddrh or pddrl, but it has no effect on pin state other than general input pin state can write to pddrh or pddrl, but it has no effect on pin state 1 general output pddrh or l value value written is output from pin other than general output pddrh or l value can write to pddrh or pddrl, but it has no effect on pin state 18. i/o ports rev.4.00 mar. 27, 2008 page 650 of 882 rej09b0108-0400 18.5 port e port e in the sh7144 is an input/output port with the 16 pins shown in figure 18.7. pe15 (i/o) / tioc4d (i/o) / dack1 (output) / irqout (output) pe14 (i/o) / tioc4c (i/o) / dack0 (output) pe13 (i/o) / tioc4b (i/o) / mres (input) pe12 (i/o) / tioc4a (i/o) / txd3 (output) pe11 (i/o) / tioc3d (i/o) / rxd3 (input) pe10 (i/o) / tioc3c (i/o) / txd2 (output) pe9 (i/o) / tioc3b (i/o) / sck3 (i/o) pe8 (i/o) / tioc3a (i/o) / sck2 (i/o) pe7 (i/o) / tioc2b (i/o) / rxd2 (input) pe6 (i/o) / tioc2a (i/o) / sck3 (i/o) pe5 (i/o) / tioc1b (i/o) / txd3 (output) pe4 (i/o) / tioc1a (i/o) / rxd3 (input) / tck (input) * pe3 (i/o) / tioc0d (i/o) / drak1 (output) / tdo (output) * pe2 (i/o) / tioc0c (i/o) / dreq1 (input) / tdi (input) * pe1 (i/o) / tioc0b (i/o) / drak0 (output) / trst (input) * pe0 (i/o) / tioc0a (i/o) / dreq0 (input) / tms (input) * port e note: * only for the f-ztat version (no correspondin g function in the masked rom version and rom less version). figure 18.7 port e (sh7144) 18. i/o ports rev.4.00 mar. 27, 2008 page 651 of 882 rej09b0108-0400 port e in the sh7145 is an input/output port with the 16 pins shown in figure 18.8. pe15 (i/o) / tioc4d (i/o) / dack1 (output) / irqout (output) pe14 (i/o) / tioc4c (i/o) / dack0 (output) pe13 (i/o) / tioc4b (i/o) / mres (input) pe12 (i/o) / tioc4a (i/o) / tck (input) * / txd3 (output) pe11 (i/o) / tioc3d (i/o) / tdo (output) * / rxd3 (input) pe10 (i/o) / tioc3c (i/o) / txd2 (output) / tdi (input) * pe9 (i/o) / tioc3b (i/o) / trst (input) * / sck3 (i/o) pe8 (i/o) / tioc3a (i/o) / sck2 (i/o) / tms (input) * pe7 (i/o) / tioc2b (i/o) / rxd2 (input) pe6 (i/o) / tioc2a (i/o) / sck3 (i/o) / audata0 (i/o) * pe5 (i/o) / tioc1b (i/o) / txd3 (output) / audata1 (i/o) * pe4 (i/o) / tioc1a (i/o) / rxd3 (input) / audata2 (i/o) * pe3 (i/o) / tioc0d (i/o) / drak1 (output) / audata3 (i/o) * pe2 (i/o) / tioc0c (i/o) / dreq1 (input) / audrst (input) * pe1 (i/o) / tioc0b (i/o) / drak0 (output) / audmd (input) * pe0 (i/o) / tioc0a (i/o) / dreq0 (input) / audck (i/o) * note: * only for the f-ztat version (no correspondin g function in the masked rom version and rom less version). port e figure 18.8 port e (sh7145) 18.5.1 register descriptions port e has the following register. for details on register addresses and register states during each processing, refer to section 25, list of registers. ? port e data register l (pedrl) 18. i/o ports rev.4.00 mar. 27, 2008 page 652 of 882 rej09b0108-0400 18.5.2 port e data register l (pedrl) the port e data register l (pedrl) is a 16-bit re adable/writable registers that stores port e data. bits pe15dr to pe0dr correspond to pins pe15 to pe0 (multiplexed functions omitted here). when a pin functions is a general output, if a value is written to pedrl, that value is output directly from the pin, and if pedrl is read, the register value is returned directly regardless of the pin state. when a pin functions is a general input, if pedrl is read, the pin state, not the register value, is returned directly. if a value is written to pedrl, although that value is written into pedrl it does not affect the pin state. table 18.5 summari zes port e data register read/write operations. ? pedrl bit bit name initial value r/w description 15 pe15dr 0 r/w see table 18.5 14 pe14dr 0 r/w 13 pe13dr 0 r/w 12 pe12dr 0 r/w 11 pe11dr 0 r/w 10 pe10dr 0 r/w 9 pe9dr 0 r/w 8 pe8dr 0 r/w 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w 0 pe0dr 0 r/w 18. i/o ports rev.4.00 mar. 27, 2008 page 653 of 882 rej09b0108-0400 table 18.5 port e data register l (pedrl) read/write operations ? bits 15 to 0 in pedrl peior pin function read write 0 general input pin state can write to pedrl, but it has no effect on pin state other than general input pin state can write to pedrl, but it has no effect on pin state 1 general output pedrl value valu e written is output from pin other than general output pedrl value can write to pedrl, but it has no effect on pin state 18. i/o ports rev.4.00 mar. 27, 2008 page 654 of 882 rej09b0108-0400 18.6 port f port f is an input-only port with the eight pins shown in figure 18.9. pf7 (input) / an7 (input) pf6 (input) / an6 (input) pf5 (input) / an5 (input) pf4 (input) / an4 (input) pf3 (input) / an3 (input) pf2 (input) / an2 (input) pf1 (input) / an1 (input) pf0 (input) / an0 (input) port f figure 18.9 port f 18.6.1 register descriptions port f is an 8-bit input-only port. port f ha s the following register. for details on register addresses and register states during each proce ssing, refer to section 25 , list of registers. ? port f data register (pfdr) 18.6.2 port f data register (pfdr) the port f data register (pfdr) is an 8-bit read-only register that stores port f data. bits pf7dr to pf0dr correspond to pins pf7 to pf0 (multiplexed functions omitted here). any value written into these bits is ignored, and th ere is no effect on the state of the pins. when any of the bits are read, the pin state rather than the bit value is read directly. however, when an a/d converter analog input is being sampled, values of 1 are read out. table 18.6 summarizes port f data register read/write operations. 18. i/o ports rev.4.00 mar. 27, 2008 page 655 of 882 rej09b0108-0400 bit bit name initial value r/w description 7 pf7dr 0/1 * r see table 18.6 * 6 pf6dr 0/1 * r 5 pf5dr 0/1 * r 4 pf4dr 0/1 * r 3 pf3dr 0/1 * r 2 pf2dr 0/1 * r 1 pf1dr 0/1 * r 0 pf0dr 0/1 * r notes: * initial values are dependent on the state of the pins. table 18.6 port f data regist er (pfdr) read/write operations ? bits 7 to 0 pin function read write general input pin state ignored (no effect on pin state) ann input (analog input) 1 ignor ed (no effect on pin state) 18. i/o ports rev.4.00 mar. 27, 2008 page 656 of 882 rej09b0108-0400 19. flash memory (f-ztat version) rom3251a_020020030800 rev.4.00 mar. 27, 2008 page 657 of 882 rej09b0108-0400 section 19 flash memory (f-ztat version) the features of the flash me mory in the flash memory version are summarized below. the block diagram of the flash memory is shown in figure 19.1. 19.1 features ? size: 256 kbytes ? programming/erasing methods ? the flash memory is programmed 128 bytes at a time. erase is performed in single-block units. the flash memory is configured as follows: 64 kbytes 3 blocks, 32 kbytes 1 block, and 4 kbytes 8 blocks. to erase the entire flash memory, each block must be erased in turn. ? reprogramming capability see section 26.5, flash memory characteristics. ? two on-board programming modes ? boot mode ? user program mode ? on-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or progra m of the entire flash memory. in normal user program mode, individual blocks can be erased or programmed. ? prom programmer mode ? flash memory can be programmed/erased in programmer mode using a prom programmer, as well as in on-board programming mode. ? automatic bit rate adjustment ? with data transfer in boot mode, this lsi's bi t rate can be automatically adjusted to match the transfer bit rate of the host computer. ? programming/erasing protection ? sets software protection against flash memory programming/erasing/verifying. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 658 of 882 rej09b0108-0400 module bus bus interface/controller flash memory (256 kbytes) operatin g mode flmcr2 internal address bus internal data bus (32 bits) fwp pin mode pin ebr1 ebr2 ramer flmcr1 flash memory control re g ister 1 flash memory control re g ister 2 erase block re g ister 1 erase block re g ister 2 ram emulation re g ister [le g end] flmcr1: flmcr2: ebr1: ebr2: ramer: figure 19.1 block diagram of flash memory 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 659 of 882 rej09b0108-0400 19.2 mode transitions when the mode pin and the fwp pin are set in the re set state and a reset-start is executed, this lsi enters an operating mode as shown in figure 19.2. in user mode, flash memory can be read but not programmed or erased. the boot mode, user program mode, and prom programmer modes are provided as modes to write and erase the flash memory. the differences between boot mode and user program mode are shown in table 19.1. figure 19.3 shows boot mode, and figure 19.4 shows user program mode. md1 = 0, fwp = 0 res = 0 res = 0 fwp = 0 fwp = 1 * 1 * 1 * 2 md1 = 1, fwp = 0 reset state boot mode on-board pro g rammin g mode user pro g ram mode user mode (on-chip rom enabled) md1 = 1, fwp = 1 prom pro g rammer mode res = 0 res = 0 notes: only make a transition between user mode and user pro g ram mode when the cpu is not accessin g the flash memory. 1. ram emulation possible 2. this lsi transits to prom pro g rammer mode by usin g the dedicated prom pro g rammer. figure 19.2 flash memory state transitions 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 660 of 882 rej09b0108-0400 table 19.1 differences between b oot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * program/program-verify erase/erase-verify program/program-verify emulation note: * to be provided by the user, in accordance with the recommended algorithm. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 661 of 882 rej09b0108-0400 flash memory this lsi ram host pro g rammin g control pro g ram sci application pro g ram (old version) new application pro g ram flash memory this lsi ram host sci application pro g ram (old version) boot pro g ram area new application pro g ram flash memory this lsi ram host sci flash memory erase boot pro g ram new application pro g ram flash memory this lsi pro g ram execution state ram host sci new application pro g ram boot pro g ram pro g rammin g control pro g ram 1. initial state the old pro g ram version or data remains written in the flash memory. the user should prepare the pro g rammin g control pro g ram and new application pro g ram beforehand in the host. 2. pro g rammin g control pro g ram transfer when boot mode is entered, the boot pro g ram in this lsi (ori g inally incorporated in the chip) is started and the pro g rammin g control pro g ram in the host is transferred to ram via sci communication. the boot pro g ram required for flash memory erasin g is automatically transferred to the ram boot pro g ram area. 3. flash memory initialization the erase pro g ram in the boot pro g ram area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without re g ard to blocks. 4. writin g new application pro g ram the pro g rammin g control pro g ram transferred from the host to ram is executed, and the new application pro g ram in the host is written into the flash memory. pro g rammin g control pro g ram boot pro g ram boot pro g ram boot pro g ram area boot pro g ram area pro g rammin g control pro g ram figure 19.3 boot mode 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 662 of 882 rej09b0108-0400 flash memory this lsi ram host pro g rammin g / erase control pro g ram sci boot pro g ram new application pro g ram flash memory this lsi ram host sci new application pro g ram flash memory this lsi ram host sci flash memory erase boot pro g ram new application pro g ram flash memory this lsi pro g ram execution state ram host sci boot pro g ram boot pro g ram fwe assessment pro g ram application pro g ram (old version) new application pro g ram 1. initial state the fwe assessment pro g ram that confirms that user pro g ram mode has been entered, and the pro g ram that will transfer the pro g rammin g /erase control pro g ram from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the pro g rammin g /erase control pro g ram should be prepared in the host or in the flash memory. 2. pro g rammin g /erase control pro g ram transfer when user pro g ram mode is entered, user software confirms this fact, executes transfer pro g ram in the flash memory, and transfers the pro g rammin g /erase control pro g ram to ram. 3. flash memory initialization the pro g rammin g /erase pro g ram in ram is executed, and the flash memory is initialized (to h'ff). erasin g can be performed in block units, but not in byte units. 4. writin g new application pro g ram next, the new application pro g ram in the host is written into the erased flash memory blocks. do not write to unerased blocks. pro g rammin g / erase control pro g ram pro g rammin g / erase control pro g ram pro g rammin g / erase control pro g ram transfer pro g ram application pro g ram (old version) transfer pro g ram fwe assessment pro g ram fwe assessment pro g ram transfer pro g ram fwe assessment pro g ram transfer pro g ram figure 19.4 user program mode 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 663 of 882 rej09b0108-0400 19.3 block configuration figure 19.5 shows the block configuration of 256-kbyte flash memory. the thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. the flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). erasing is performed in these units. programming is performed in 128-byte units starting from an address with lower eight bits h'00 or h'80. eb0 eb1 eb2 eb3 eb4 eb5 eb6 eb7 eb8 eb9 h'000000 h'000fff h'00007f h'004fff h'005fff h'001fff h'002fff h'003fff h'01ffff h'006fff h'007fff h'00ffff h'001000 h'002000 h'003000 h'004000 h'005000 h'006000 h'007000 h'008000 h'010000 eb10 h'02ffff h'020000 eb11 h'03ffff h'030000 pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes pro g rammin g unit: 128 bytes erase unit 4 kbytes erase unit 4 kbytes erase unit 4 kbytes erase unit 4 kbytes erase unit 4 kbytes erase unit 4 kbytes erase unit 4 kbytes erase unit 4 kbytes erase unit 32 kbytes erase unit 64 kbytes erase unit 64 kbytes erase unit 64 kbytes ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? figure 19.5 flash memory block configuration 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 664 of 882 rej09b0108-0400 19.4 input/output pins the flash memory is controlled by means of the pins shown in table 19.2. table 19.2 pin configuration pin name i/o function res input reset fwp * 1 input flash programming/er asing protection by hardware md1 input sets this lsi's operating mode md0 input sets this lsi's operating mode txd1 (pa4) * 2 output serial transmit data output rxd1 (pa3) * 2 input serial receive data input notes: 1. protection cannot be made to flas h memory programming/erasing regardless of the setting of the fwp pin when using e10a (when dbgmd is high) 2. in boot mode, sci pins are fixed, and pa3 and pa4 pins are used as sci pins. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 665 of 882 rej09b0108-0400 19.5 register descriptions the flash memory has the following registers. for details on register addresses and register states during each processing, refer to section 25, list of registers. ? flash memory control register 1 (flmcr1) ? flash memory control register 2 (flmcr2) ? erase block register 1 (ebr1) ? erase block register 2 (ebr2) ? ram emulation register (ramer) 19.5.1 flash memory control register 1 (flmcr1) flmcr1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. for details on register setting, refer to section 19.8, flash memory programming/erasing. bit bit name initial value r/w description 7 few 1/0 r flash write enable * reflects the input level at the fwp pin. it is set to 1 when a low level is input to the fwp pin, and cleared to 0 when a high level is input. 6 swe 0 r/w software write enable when this bit is set to 1 while the few bit is 1, flash memory programming/erasing is enabled. when this bit is cleared to 0, other flmcr1 bits and all ebr1 and ebr2 bits cannot be set. 5 esu 0 r/w erase setup when this bit is set to 1 while the few and swe bits are 1, the flash memory changes to the erase setup state. when it is cleared to 0, the erase setup state is cancelled. 4 psu 0 r/w program setup when this bit is set to 1 while the few and swe bits are 1, the flash memory changes to the program setup state. when it is cl eared to 0, the program setup state is cancelled. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 666 of 882 rej09b0108-0400 bit bit name initial value r/w description 3 ev 0 r/w erase-verify when this bit is set to 1 while the few and swe bits are 1, the flash memory changes to erase-verify mode. when it is cleared to 0, erase-verify mode is cancelled. 2 pv 0 r/w program-verify when this bit is set to 1 while the few and swe bits are 1, the flash memory changes to program-verify mode. when it is cleared to 0, program-verify mode is cancelled. 1 e 0 r/w erase when this bit is set to 1 while the few, swe and esu bits are 1, the flash memory changes to erase mode. when it is cleared to 0, erase mode is cancelled. 0 p 0 r/w program when this bit is set to 1 while the few, swe and psu bits are 1, the flash memory changes to program mode. when it is cleared to 0, program mode is cancelled. note: * the value of this bit is 1 when using e10a (when dbgmd is high). 19.5.2 flash memory control register 2 (flmcr2) flmcr2 is a register that displays the st ate of flash memory programming/erasing. bit bit name initial value r/w description 7 fler 0 r indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error-protection state. see section 19.9.3, error protection, for details. 6 to 0 ? all 0 r reserved these bits are always read as 0. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 667 of 882 rej09b0108-0400 19.5.3 erase block register 1 (ebr1) ebr1 specifies the flash memory erase block. ebr1 is initialized to h'00 when a high level is input to the fwp pin. it is also initialized to h'00, when the swe bit in flmcr1 is 0 regardless of value in the fwp pin. do not set more than one bit at a time in ebr1 and ebr2, as this will cause all the bits in ebr1 and ebr2 to be automatically cleared to 0. bit bit name initial value r/w description 7 eb7 0 r/w when this bit is set to 1, 4 kbytes of eb7 (h'007000 to h'007fff) are to be erased. 6 eb6 0 r/w when this bit is set to 1, 4 kbytes of eb6 (h'006000 to h'006fff) are to be erased. 5 eb5 0 r/w when this bit is set to 1, 4 kbytes of eb5 (h'005000 to h'005fff) are to be erased. 4 eb4 0 r/w when this bit is set to 1, 4 kbytes of eb4 (h'004000 to h'004fff) are to be erased. 3 eb3 0 r/w when this bit is set to 1, 4 kbytes of eb3 (h'003000 to h'003fff) are to be erased. 2 eb2 0 r/w when this bit is set to 1, 4 kbytes of eb2 (h'002000 to h'002fff) are to be erased. 1 eb1 0 r/w when this bit is set to 1, 4 kbytes of eb1 (h'001000 to h'001fff) are to be erased. 0 eb0 0 r/w when this bit is set to 1, 4 kbytes of eb0 (h'000000 to h'000fff) are to be erased. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 668 of 882 rej09b0108-0400 19.5.4 erase block register 2 (ebr2) ebr2 specifies the flash memory erase block. ebr2 is initialized to h'00 when a high level is input to the fwp pin. it is also initialized to h'00, when the swe bit in flmcr1 is 0 regardless of value in the fwp pin. do not set more than one bit at a time in ebr1 and ebr2, as this will cause all the bits in ebr1 and ebr2 to be automatically cleared to 0. bit bit name initial value r/w description 7 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 eb11 0 r/w when this bit is set to 1, 64 kbytes of eb11 (h'030000 to h'03ffff) are to be erased. 2 eb10 0 r/w when this bit is set to 1, 64 kbytes of eb10 (h'020000 to h'02ffff) are to be erased. 1 eb9 0 r/w when this bit is set to 1, 64 kbytes of eb9 (h'010000 to h'01ffff) will be erased. 0 eb8 0 r/w when this bit is set to 1, 32 kbytes of eb8 (h'008000 to h'00ffff) will be erased. 19.5.5 ram emulation register (ramer) ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer settings should be made in user mode or user program mode. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed imme diately after this regist er has been modified. normal execution of an access immediately after register m odification is not guaranteed. bit bit name initial value r/w description 15 to 4 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 3 rams 0 r/w ram select specifies selection or non-selection of flash memory emulation in ram. when rams = 1, the flash memory is overlapped with part of ram, and all flash memory blocks are program/erase-protected. when rams = 0, the ram emulation function is disabled. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 669 of 882 rej09b0108-0400 bit bit name initial value r/w description 2 1 0 ram2 ram1 ram0 0 0 0 r/w r/w r/w flash memory area selection when the rams bit is set to 1, these bits specify one of the following flash memory areas to be overlapped with part of ram. 000: h'00000000 to h'00000fff (eb0) 001: h'00001000 to h'00001fff (eb1) 010: h'00002000 to h'00002fff (eb2) 011: h'00003000 to h'00003fff (eb3) 100: h'00004000 to h'00004fff (eb4) 101: h'00005000 to h'00005fff (eb5) 110: h'00006000 to h'00006fff (eb6) 111: h'00007000 to h'00007fff (eb7) 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 670 of 882 rej09b0108-0400 19.6 on-board programming modes there are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and prom programmer mode, in which programming/erasing is performed with a prom programmer. on-board programming/erasing can also be performed in user program mode. at reset-start in reset mode, this lsi changes to a mode depending on the md pin settings and fwp pin setting, as shown in table 19.3. when changing to boot mode, the boot program buil t into this lsi is initiated. the boot program transfers the programming control program from the externally-connected host to on-chip ram via sci1. after erasing the entire flash memory, the programming control program is executed. this can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. in user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. table 19.3 setting on-board programming modes md1 md0 fwp lsi state after reset end 0 0 expanded mode 0 1 boot mode single-chip mode 1 0 user program mode expanded mode 1 single-chip mode 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 671 of 882 rej09b0108-0400 19.6.1 boot mode table 19.4 shows the boot mode operations between reset end and branching to the programming control program. 1. when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. prepare a programming control program in accordance with the description in section 19.8, flash memory programming/erasing. 2. the sci1 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. when the boot program is initiated, the chip measures the low-level period of asynchronous sci communication data (h'00) transmitted continuously from the host. the chip then calculates the bit rate of transmission from the host, and adjusts the sci1 bit rate to match that of the host. the reset should end with the rxd pin high. the rxd and txd pins should be pulled up on the board if necessary. 4. after matching the bit rates, the chip transmits one h'00 byte to the host to indicate the completion of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the chip. if reception could not be performed normally, initia te boot mode again by a reset. depending on the host's transfer bit rate and system clock frequency of this lsi, there will be a discrepancy between the bit rates of the host and the chip. to operate the sci properly, set the host's transfer bit rate and system clock frequency of this lsi within the ranges listed in table 19.5. 5. in boot mode, a part of the on-chip ram area is used by the boot program. the area h'ffffe800 to h'ffffffff is the area to wh ich the programming control program is transferred from th e host. the boot program area cannot be used until the ex ecution state in boot mode switches to the programming control program. 6. before branching to the programming control pr ogram, the chip terminat es transfer operations by sci1 (by clearing the re and te bits in scr to 0), however the adjusted bit rate value remains set in brr. therefore, the programming co ntrol program can still use it for transfer of write data or verify data with the host. the tx d pin is high. the contents of the cpu general registers are undefined immediately after br anching to the programming control program. these registers must be initialized at the beginni ng of the programming control program, as the stack pointer (sp), in particular, is used implicitly in subroutine calls, etc. 7. boot mode can be cleared by a reset. end the reset after driving the reset pin low, waiting at least 25 states, and then setting the mode (md) pins. boot mode is also cleared when a wdt overflow occurs. 8. do not change the md pin input levels in boot mode. 9. all interrupts are disabled during programming or erasing of the flash memory. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 672 of 882 rej09b0108-0400 table 19.4 boot mode operation item host operation communi c ations contents lsi operation boot mode start branches to boot pro g ram at reset-start. pro c essing contents pro c essing contents bit rate adjustment continuously transmits data h'00 at specified bit rate. h'00, h'00 ...... h'00 h'00 h'55 ? measures low-level period of receive data h'00. ? calculates bit rate and sets it in brr of sci_1. ? transmits data h'00 to host as adjustment end indication. transmits data h'aa to host when data h'55 is received. transmits data h'55 when data h'00 is received error-free. transmits number of bytes (n) of pro g rammin g control as pro g ram to be transferred 2-byte data (lower byte followin g upper byte) receives data h'aa. transmits 1-byte of pro g rammin g control pro g ram (repeated for n times) receives data h'aa. transfer of pro g rammin g control pro g ram flash memory erase boot pro g ram initiation echobacks the 2-byte data received. branches to pro g rammin g control pro g ram transferred to on-chip ram and starts execution. echobacks received data to host and also transfers it to ram (repeated for n times) checks flash memory data, erases all flash memory blocks in case of written data existin g , and transmits data h'aa to host. (if erase could not be done, transmits data h'ff to host and aborts operation.) upper byte and lower byte h'xx h'aa echoback echoback h'ff h'aa boot pro g ram erase error table 19.5 peripheral clock (p ) frequencies for which automatic adjustment of lsi bit rate is possible host bit rate peripheral cl ock frequency range of lsi 9,600 bps 4 to 40 mhz 19,200 bps 8 to 40 mhz 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 673 of 882 rej09b0108-0400 19.6.2 programming/erasing in user program mode on-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. the user must set branching conditions and provide on-board means of supplying programming data. the flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. as the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip ram or external memory, and execute it. figure 19.6 shows a sample procedure for programming/erasing in user program mode. prepare a user program/ erase control program in accordance with the description in section 19.8, flash memory programming/erasing. ye s no pro g ram/erase? transfer user pro g ram/erase control pro g ram to ram reset-start branch to user pro g ram/erase control pro g ram in ram execute user pro g ram/erase control pro g ram (flash memory rewrite) branch to flash memory application pro g ram branch to flash memory application pro g ram fwp = low * fwp = hi g h note: * do not constantly apply a low level to the fwp pin. only apply a low level to the fwp pin when pro g rammin g or erasin g the flash memory. to prevent excessive pro g rammin g or excessive erasin g , while a low level is bein g applied to the fwp pin, activate the watchdo g timer in case of handlin g cpu runaways. figure 19.6 programming/erasing fl owchart example in user program mode 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 674 of 882 rej09b0108-0400 19.7 flash memory emulation in ram a setting in the ram emulation register (ramer) enables part of ram to overlap with the flash memory area so that data to be written to flas h memory can be emulated in ram in real time. emulation can be performed in user mode or user program mode. figure 19.7 shows an example of emulation of real-time flash memory programming. 1. set ramer to overlap part of ram with the area for which real-time programming is required. 2. emulation is performed using the overlapped ram. 3. after the program data has been confirmed, the rams bit is cleared, thus releasing the ram overlap. 4. the data written in the overlapped ram is written into the flash memory area. set ramer write tunin g data to overlapped ram execute application pro g ram tunin g ok? clear ramer write to flash memory emulation block no ye s start of emulation pro g ram end of emulation pro g ram figure 19.7 flowchart for flash memory emulation in ram 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 675 of 882 rej09b0108-0400 figure 19.8 shows a sample procedure for flash memory block area overlapping. 1. the ram area to be overlapped is fixed at a 4-kbyte area in the range h'ffffe000 to h'ffffefff. 2. the flash memory area to be overlapped is selected by ramer from a 4-kbyte area of the eb0 to eb7 blocks. 3. the overlapped ram area can be accessed fr om both the flash memory addresses and ram addresses. 4. when the rams bit in ramer is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). in this state, setting the p or e bit in flmcr1 to 1 does not cause a transition to program mode or erase mode. 5. a ram area cannot be erased by execu tion of software in accordance with the erase algorithm. 6. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlapped ram. eb0 h'00000 h'01000 h'02000 h'03000 h'04000 h'05000 h'06000 h'07000 h'08000 h'3ffff eb1 eb2 eb3 eb4 eb5 eb6 eb7 eb8 to eb11 h'ffffe000 h'ffffefff h'ffffffff this area can be accessed from both the flash memory addresses and ram addressed. flash memory on-chip ram figure 19.8 example of ra m overlap operation (ram[2:0] = b'000) 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 676 of 882 rej09b0108-0400 19.8 flash memory programming/erasing a software method using the cpu is employed to program and erase the flash memory in on- board programming modes. depending on the flmcr1 and flmcr2 settings, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. the programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. flash memory programming and erasing should be performed in accordance with the descriptions in section 19.8 .1, program/program-veri fy mode and section 19.8.2, erase/erase-veri fy mode, respectively. 19.8.1 program/program-verify mode when writing data or programs to the flash memory, the program/program-verify flowchart shown in figure 19.9 should be followed. performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. programming must be done to an empty address. do not reprogram an address to which programming has already been performed. 2. programming should be carried out 128 bytes at a time. a 128-byte data transfer must be performed even if writing fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. prepare the following data storage areas in ram: a 128-byte programming data area, a 128- byte reprogramming data area, and a 128-byte additional-programming data area. perform reprogramming data computation and additional programming data computation according to figure 19.9. 4. consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flas h memory. the program address and 128-byte data are latched in the flash memory. the lower 8 bits of the start addres s in the flash memory destination area must be h'00 or h'80. 5. the time during which the p bit is set to 1 is the programming time. figure 19.9 shows the allowable programming time. 6. the watchdog timer (wdt) is set to prevent overprogramming due to program runaway, etc. an overflow cycle of approximately 6.6 ms is allowed. 7. for a dummy write to a verify address, write 1- byte data h'ff to an address to be read. verify data can be read in longwords from the address to which a dummy write was performed. 8. the number of repetitions of the program/program-verify sequence to the same bit should not exceed the maximum number of programming (n). 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 677 of 882 rej09b0108-0400 start end sub 1 2 3 4 5 6 7 8 9 10 11 12 13 998 999 1000 t sp 30 t sp 30 t sp 30 t sp 30 t sp 30 t sp 30 t sp 200 t sp 200 t sp 200 t sp 200 t sp 200 t sp 200 t sp 200 t sp 200 t sp 200 t sp 200 ng ng ng ng ok ok ok * 2 * 7 * 7 * 4 * 7 * 7 * 5 * 7 * 7 * 1 * 4 * 3 * 7 * 7 * 7 * 1 * 4 ok ng ok ng ok ram end of pro g rammin g set swe bit in flmcr1 start of pro g rammin g wait (t sswe ) s n = 1 m = 0 wait (t spv ) s wait (t spvr ) s wait (t cpv ) s apply write pulse (tsp30 or tsp200) sub-routine-call set pv bit in flmcr1 h'ff dummy write to verify address read verify data write data = verify data? transfer repro g ram data to repro g ram data area repro g ram data computation transfer additional-pro g rammin g data to additional-pro g rammin g data area additional-pro g rammin g data computation clear pv bit in flmcr1 clear swe bit in flmcr1 m = 1 repro g ram see note *6 for pulse width m = 0 ? increment address pro g rammin g failure clear swe bit in flmcr1 wait (t cswe ) s 6 n? 6 n ? wait (t cswe ) s n n? n n + 1 store 128-byte pro g ram data in pro g ram data area and repro g ram data area apply write pulse (tsp10) (additional pro g rammin g ) 128-byte data verification completed? successively write 128-byte data from additional- pro g rammin g data area in ram to flash memory perform pro g rammin g in the erased state. do not perform additional pro g rammin g on previously pro g rammed addresses. ori g inal data (d) verify data (v) repro g ram data (x) comments pro g rammin g completed still in erased state; no action pro g rammin g incomplete; repro g ram repro g ram data computation table repro g ram data (x') verify data (v) additional- pro g rammin g data (y) 1 1 1 1 0 1 0 0 0 0 1 1 comments additional pro g rammin g to be executed additional pro g rammin g not to be executed additional pro g rammin g not to be executed additional pro g rammin g not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 additional-pro g rammin g data computation table notes: 1. data transfer is performed by byte transfer. the lower 8 bits of the start address to be written to must be h'00 or h '80. a 128-byte data transfer must be performed even if writin g fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. 2. verify data is read in 32-bit (lon g word) units. 3. repro g ram data is determined by the operation shown in the table below (comparison between the data stored in the pro g ram data area and the verify data). bits for which the repro g ram data is 0 are pro g rammed in the next repro g rammin g loop. therefore, even bits for which pro g rammin g has been completed will be subjected to pro g rammin g once a g ain if the subsequent verify operation ends in failure. 4. a 128-byte area for the stora g e of pro g rammin g data, a 128-byte area for the stora g e of repro g rammin g data, and a 128-byte area for the stora g e of additional- pro g rammin g data must be provided in ram. the contents of the repro g ram data area and additional-pro g ram data area are modified as pro g rammin g proceeds. 5. a write pulse of 30 s or 200 s is applied accordin g to the pro g ress of the pro g rammin g operation. see note 6 for details of the pulse widths. when writin g of additional-pro g rammin g data is executed, a 10 s write pulse should be applied. repro g ram data x' means repro g ram data when the write pulse is applied. 7. the wait times and value of n are shown in section 26.5, flash memory characteristics. pro g ram data stora g e area (128 bytes) repro g ram data stora g e area (128 bytes) additional-pro g rammin g data stora g e area (128 bytes) number of writes n note: 6. write pulse width write time (tsp) s * use a t sp 10 write pulse for additional pro g rammin g . write pulse application subroutine apply write pulse set psu bit in flmcr1 enable wdt disable wdt wait (t spsu ) s set p bit in flmcr1 wait (tsp10, tsp30, or tsp200) s clear p bit in flmcr1 wait (t cp ) s clear psu bit in flmcr1 wait (t cpsu ) s start of pro g rammin g end of pro g rammin g * 7 successively write 128-byte data from repro g ram data area in ram to flash memory figure 19.9 program/pr ogram-verify flowchart 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 678 of 882 rej09b0108-0400 19.8.2 erase/erase-verify mode when erasing flash memory, the erase/erase-veri fy flowchart shown in figure 19.10 should be followed. 1. prewriting (setting erase block da ta to all 0s) is not necessary. 2. erasing is performed in block units. make only a single-bit specification in the erase block register 1 (ebr1) and the erase block register 2 (ebr2). to erase multiple blocks, each block must be erased in turn. 3. the time during which the e bit is set to 1 is the flash memory erase time. 4. the watchdog timer (wdt) is set to prevent overerasing due to prog ram runaway, etc. an overflow cycle of approximately 19.8 ms is allowed. 5. for a dummy write to a verify address, write 1- byte data h'ff to the read address. verify data can be read in longwords fr om the address to which a dummy write was performed. 6. if the read data is not erased successfully, se t erase mode again, and repeat the erase/erase- verify sequence as before. the number of repeti tions of the erase/erase-verify sequence should not exceed the maximum number of erasing (n). 19.8.3 interrupt handli ng when programming/erasing flash memory all interrupts, including the nmi interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. an interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. if an interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the cpu malfunctions. 3. if an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 679 of 882 rej09b0108-0400 no no ye s ye s ye s no no ye s * 1 * 3 * 2 * 4 erase start set ebr1 and ebr2 enable wdt disable wdt read verify data increment address verify data = all 1s? last address of block? all erase block erased? set block start address as verify address h'ff dummy write to verify address swe bit 1 n 1 esu bit 1 e bit 1 wait (t sswe ) s wait (t sesu ) e bit 0 ev bit 1 wait (t se ) esu bit 0 wait (t ce ) wait (t cesu ) wait (t sev ) ev bit 0 n n + 1 wait (t cev ) swe bit 0 wait (t cswe ) ev bit 0 n 100? wait (t cev ) swe bit 0 wait (t cswe ) erase failure end of erasin g wait (t sevr ) notes: 1. prewritin g (settin g erase block data to all 0s) is not necessary. 2. verify data is read in 32-bit (lon g word) units. 3. make only a sin g le-bit specification in the erase block re g ister 1 (ebr1) and the erase block re g ister 2 (ebr2). 4. erasin g is performed in block units. to erase multiple blocks, each block must be erased in turn. figure 19.10 erase/erase-verify flowchart 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 680 of 882 rej09b0108-0400 19.9 program/erase protection there are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 19.9.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), erase block register 1 (ebr1), and er ase block register 2 (ebr2) are initialized. protect function item description program erase fwp pin protect when a high level is input to the fwp pin, flmcr1, ebr 1, and ebr 2 are initialized, and the program/erase protection state is entered. * yes yes reset/standby protect in the reset state (including the reset state when the wdt overflows) and standby mode, flmcr1, ebr 1, and ebr 2 are initialized, and the program/erase protection state is entered. in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes note: * protection by the fwp pin cannot be made when using e10a (when dbgmd is high). 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 681 of 882 rej09b0108-0400 19.9.2 software protection software protection can be implemented against programming/erasing of all flash memory blocks by clearing the swe bit in flmcr1. when software protection is in effect, setting the p or e bit in flmcr1 does not cause a transition to program mode or erase mode. by setting the erase block register 1 (ebr1), erase protection can be set for individual blocks. when ebr1 is set to h'00, erase protection is set for all blocks. protect function item description program erase swe bit protect when the swe bit in flmcr1 is cleared to 0, all blocks are program/e rase-protected. (this setting should be carried out in on-chip ram or external memory.) yes yes block protect by setting the erase block register 1 (ebr1) and the erase block register 2 (ebr2), erase protection can be set for individual blocks. when both ebr1 and ebr2 are set to h'00, erase protection is set for all blocks. ? yes emulation protect when the rams bit in ramer is set to 1, all blocks are program/erase-protected. yes yes 19.9.3 error protection in error protection, an error is detected when cpu runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the prog ram/erase operation is forcibly ab orted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. when the following errors are de tected during programming/eras ing of flash memory, the fler bit in flmcr2 is set to 1, and the error protection state is entered. ? when the flash memory is read during programming/erasing (including vector read and instruction fetch) ? immediately after exception handling (excluding a reset) during programming/erasing ? when a sleep instruction is executed during programming/erasing the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, however pr ogram mode or erase mode is forcibly aborted at the point when the error is detected. program mode or erase mode cannot be re-entered by re-setting the p1 or e1 b it. however, pv and ev bit settings are retained, 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 682 of 882 rej09b0108-0400 and a transition can be made to verify mode. th e error protection state can be cancelled by the power-on reset only. 19.10 prom programmer mode in prom programmer mode, a prom programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. use a prom programmer that supports the renesas 256-kbyte flash memory on-chip mcu device type (fztat256v3a). 19.11 usage note 19.11.1 module standby mode setting access to flash memory can be enabled/disabled by the module standby control register (mstcr1). the initial value enab les access to flash memory. flas h memory access is disabled by setting the module standby control register. for details, see section 24, power-down modes. 19.11.2 notes when converting the f-ztat versions to the ma sked-rom versions please note the following when converting the f-ztat versions to the masked-rom versions, with using the f-ztat application software. in the masked-rom version, addresses of the fl ash memory registers (r efer to section 25.1, register addresses table (in the order from lower addresses)) return undefined value if read. when the f-ztat application software is used in the masked-rom version, the fwp pin level cannot be determined. when converting the program, make sure the reprogramming (erasing/programming) part of the flash memory and the ram emulation part not to be initiated. in the masked-rom version, boot mode pin setting should not be performed. note: this difference applies to all the f-ztat versions and all the masked-rom versions that have different rom size. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 683 of 882 rej09b0108-0400 19.11.3 notes on flash memory programming and erasing precautions concerning the use of on-board programming mode, the ram emulation function, and programmer mode ar e summarized below. use the specified voltages and ti ming for programming and erasing: appling excessive voltage beyond the specification can perman ently damage the device. use an eprom programmer that supports the renesas' microcomputer device having on-chip 256-kbyte flash memory. use only the specified socket adapte r, otherwise a serious damage may occur. powering on and off (see figures 19.11 to 19.13): do not apply a low level to the fwp pin until v cc has been stabilized. also, drive the fwp pin high before turning off v cc . if v cc is to be applied or disconnected, fix the fwp pin level at v cc and place the flash memory in the hardware protection state in advance. conditions for this power-on and power-o ff timing should also be applied in the event of a power failure and subsequent recovery. fwp application/disconnection (see figures 19.11 to 19.13): if v cc is on or off while low level is applied to fwp pin, a voltage surge from low level on the reset pin may cause unintentional programming or erasing of flash memory. applying voltage to fwp should be carried out while mcu operation is in a stable condition. if mcu operation is not stable, fix the fwp pin high and set the protection state. the foll owing points must be observed concerning fwp application and disconnection to prevent unintentional programming or erasing of flash memory: ? apply voltage to fwp while the v cc voltage is stable enough to satisfy the specification voltage range. ? in boot mode, apply voltage to fwp or disconnect it during a reset. ? prior to applying voltage while fwp pin is in low level in boot mode, ensure that the reset pin level is surely kept low despite the applying voltage is rising to v cc . note that in a case where ics for reset are used, the voltage leve l of reset pin can transiently exceed 1/2 v cc while v cc is rising. ? in user program mode, fwp can be switched between high and low level regardless of the reset state. fwp input can also be switched during execution of a program in flash memory. ? apply voltage to fwp while programs are not running away. ? disconnect fwp only wh en the swe, esu, psu, ev, pv, p, and e bits in flmcr1 are cleared. make sure that the sw e, esu, psu, ev, pv, p, and e bits are not set by mistake when applying voltage to fwp pin or disconnecting. do not apply a constant low level to the fwp pin: if a program runs away while low level is applied to fwp pin, incorrect programming or erasing may occur. apply a low level to the fwp 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 684 of 882 rej09b0108-0400 pin only when programming or erasing flash memory. avoid creating a system configuration in which a low level is constantly applied to the fw p pin. also, while a low level is applied to the fwp pin, the watchdog timer should be activ ated to prevent excess programming or excess erasing due to program runaway, etc. use the recommended algorithm when pr ogramming and erasing flash memory: the recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program da ta reliability. when setting the p or e bit in flmcr1, the watchdog timer should be set before hand as a precaution against program runaway, etc. do not set or clear the swe bit during execution of a program in flash memory: wait for at least 100 s after clearing the swe bit before execu ting a program or reading data in flash memory. when the swe bit is set, data in flash memory can be rewritten. access flash memory only for verify operations (verification during programming/erasing). also, do not clear the swe bit during programming, erasing, or verifying. similarly, when using the ram emulation function while a low level is being input to the fwp pin, the swe bit must be cleared before executing a program or reading data in flash memory. however, the ram area overlapping flash memory space can be read and written to regardless of whether the swe bit is set or cleared. do not use interrupts while flash memory is being programmed or erased: all interrupt requests, including nmi, should be disabled during fwp application to give priority to program/erase operations. do not perform additional programming. erase the memory before reprogramming: in on- board programming, perform only one programming operation on a 128-byte programming unit block. in programmer mode, too, perform only one programming operation on a 128-byte programming unit block. programming should be carried out with the entire programming unit block erased. before programming, check that the chip is correctly mounted in the eprom programmer: overcurrent damage to the device can result if the index marks on the eprom programmer socket, socket adapter, and ch ip are not correctly aligned. do not touch the socket adapt er or chip during programming: casual contact with either of these by hand or something while programming can generate a transient noise on the fwp and reset pins or cause incorrect programming or erasing due to bad electrical contact. reset the flash memory before turning on the power: if v cc is applied to the reset pin while in high state, mode signals are not correctly downloaded, causing mcu's runaway. in a case where fwp pin is in low state, incorr ect programming or erasing can occur. 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 685 of 882 rej09b0108-0400 apply the reset signal while swe is low to reset the flash memory during its operation: the reset signal is applied at least 100 s after the swe bit has been cleard. comply with power-on procedure de signated by the programmer maker: when executing an on-board writing with a programmer, incorrect programming or erasing may occur unless the power-on procedure designated by the programmer makers is applied. ck vcc fwp md3 to md0 * 1 res swe bit wait time: t sswe wait time: 10 0 s pro g rammable/ erasable swe set swe clear t osc1 t mds * 3 t mds * 3 min 0 s min 0 s prohibition time of accessin g flash memory (t sswe : wait time after swe set) * 2 repro g rammable time of flash memory (prohibition of pro g ram execution on flash memory and of readin g data except verify) notes: 1. 2. 3. levels of mode pins (md3 to md0) should be fixed to pull down or pull up until power-off except mode switchim g occasion. see section 26.5, flash memory characteristics. see section 26.3.3, control si g nal timin g . figure 19.11 power on /off timing (boot mode) 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 686 of 882 rej09b0108-0400 ck vcc fwp md3 to md0 * 1 res swe bit wait time: t sswe wait time:10 0 s pro g rammable/ erasable swe set swe clear t osc1 t mds * 3 min 0 s prohibition time of accessin g flash memory (t sswe : wait time after swe set) * 2 repro g rammable time of flash memory (prohibition of pro g ram execution on flash memory and of readin g data except verify) notes: 1. 2. 3. levels of mode pins (md3 to md0) should be fixed to pull down or pull up until power-off except mode switchim g occasion. see section 26.5, flash memory characteristics. see section 26.3.3, control si g nal timin g . figure 19.12 power on/off timing (user program mode) 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 687 of 882 rej09b0108-0400 ck vcc fwp md3 to md0 res swe bit wait time: t sswe wait time: t sswe wait time: t sswe wait time: t sswe pro g rammable/ erasable pro g rammable/ erasable pro g rammable/ erasable pro g rammable/ erasable swe set swe clear t mds * 2 t mds * 2 t mds * 2 t resw min 0 s prohibition time of accessin g flash memory (t sswe : wait time after swe set) * 3 repro g rammable time of flash memory (prohibition of pro g ram execution on flash memory and of readin g data except verify) boot mode mode switch * 1 user mode user pro g ram mode user mode user pro g ram mode mode switch * 1 t osc1 * 4 * 4 * 4 * 4 notes: 1. 2. 3. 4. when transitin g to boot mode or transitin g to other modes from boot mode, mode switch by res input is necessary. see section 26.3.3, control si g nal timin g . see section 26.5, flash memory characteristics. wait time: 100 s figure 19.13 mode transit timing (example: boot mode user mode ? user program mode) 19. flash memory (f-ztat version) rev.4.00 mar. 27, 2008 page 688 of 882 rej09b0108-0400 20. mask rom rev.4.00 mar. 27, 2008 page 689 of 882 rej09b0108-0400 section 20 mask rom this lsi is available with 256 kbytes of on-c hip mask rom. the on-chip rom is connected to the cpu, direct memory access controller (dmac), and data transfer cont roller (dtc ) through a 32-bit data bus (figure 20.1). the cpu, dmac, and dtc can access the on-chip rom in 8, 16 and 32-bit widths. data in the on-chip ro m can always be accessed in one cycle. h'00000000 h'00000004 h'00000001 h'00000005 h'00000002 h'00000006 h'00000003 h'00000007 h'0003fffc h'0003fffd h'0003fffe h'0003ffff internal data bus (32 bits) on-chip rom figure 20.1 mask rom block diagram the operating mode determines whether the on-chip rom is valid or not. the operating mode is selected using mode-setting pins fwp and md3-md0 as shown in table 3.1. if you are using the on-chip rom, select mode 2 or mode 3; if you are not, select mode 0 or 1. the on-chip rom is allocated to addresses h'00000000 to h'0003ffff of memory area 0. 20.1 usage note ? module standby mode setting access to the on-chip rom can be enabled/disabled by the module standby control register (mstcr1). the initial value en ables the on-chip rom operation. on-chip rom access is disabled by setting the module standby mode. for details, see section 24, power-down modes. 20. mask rom rev.4.00 mar. 27, 2008 page 690 of 882 rej09b0108-0400 21. ram ram0200a_010020030800 rev.4.00 mar. 27, 2008 page 691 of 882 rej09b0108-0400 section 21 ram this lsi has an on-chip high-speed static ram. the on-chip ram is connected to the cpu, direct memory access controller (dmac), data tr ansfer controller (dtc), and advanced user debugger (aud)* by a 32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on- chip ram. data in the on-chip ram can always be accessed in one cycle, providing high-speed access that makes this ram ideal for use as a prog ram area, stack area, or data area. the on-chip ram is allocated to address h' ffffe000 to h'ffffffff. the contents of the on-chip ram are retained in sleep mode and standby mode, and by a power-on reset and a manual reset. the on-chip ram can be enabled or disabled by means of the rame bit in the system control register (syscr). for details on the system c ontrol register (syscr), refer to section 24.2.2, system control register (syscr). note: * flash version only. 21.1 usage note ? module standby mode setting ram can be enabled/disabled by the module standby control register (mstcr1). the initial value enables ram operation. ram access is di sabled by setting th e module standby mode. for details, see section 24, power-down modes. 21. ram rev.4.00 mar. 27, 2008 page 692 of 882 rej09b0108-0400 22. user debugging interface (h-udi) hud0001a_010020020700 rev.4.00 mar. 27, 2008 page 693 of 882 rej09b0108-0400 section 22 user debugging interface (h-udi) 22.1 overview the user debugging interface (h-udi) provides data transfer and interrupt request functions. the h-udi performs serial transfer by means of external signal control. 22.1.1 features the h-udi has the following features: ? five test signals (tck, tdi, tdo, tms, and trst ) ? tap controller ? two instructions ? bypass mode test mode conforming to ieee 1149.1 ? h-udi interrupt h-udi interrupt request to intc note: this lsi does not support test modes other than the bypass mode. 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 694 of 882 rej09b0108-0400 22.1.2 block diagram figure 22.1 shows a block diagram of the h-udi. tap controller tck tms trst tdi tdo h-udi interrupt si g nal sdir: sdsr: sddrh: sddrl: sdbpr: [le g end] mux decoder internal bus controller instruction re g ister status re g ister data re g ister h data re g ister l bypass re g ister tck: tms: trst : tdi: tdo: test clock test mode select test reset test data input test data output peripheral bus sdbpr shift re g ister sdir sdsr sddrh sddrl 16 figure 22.1 h-udi block diagram 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 695 of 882 rej09b0108-0400 22.2 input/output pins table 22.1 shows the h-udi pin configuration. table 22.1 h-udi pins pin name abbreviation i/o function test clock tck input test clock input tck supplies an independent clock to the h-udi. as the clock input to tck is supplied directly to the h-udi, a clock waveform with a duty cycle close to 50% should be input (see section 26, electrical characteristics, for details). test mode select tms input test mode select input signal tms is sampled at the rising edge of tck. tms controls the internal stat e of the tap controller. test data input tdi input serial data input tdi performs serial input of instructions and data to h- udi registers. tdi is sampled at the rising edge of tck. test data output tdo output serial data output tdo performs serial output of instructions and data from h-udi registers. transfer is synchronized with tck. when no signal is being output, tdo goes to the high-impedance state. test reset trst input test reset input signal trst is used to initialize the h-udi asynchronously. 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 696 of 882 rej09b0108-0400 22.3 register description the h-udi has the following registers. for the regi ster addresses and register states in each operating mode, refer to section 25, list of registers. ? instruction register (sdir) ? status register (sdsr) ? data register h (sddrh) ? data register l (sddrl) ? bypass register (sdbpr) instructions and data can be input to the instruc tion register (sdir) and data register (sddr) by serial transfer from the test data input pin (tdi). data from the status register (sdsr), and sddr can be output via the test data output pin (tdo). the bypass register (sdbpr) is a one-bit register that is connected to tdi and tdo in bypass mo de. except for sdbpr, all the registers can be accessed by the cpu. table 22.2 shows the kinds of serial transfer that can be used with each of the h-udi?s registers. table 22.2 serial transfer characteristics of h-udi registers register serial input serial output sdir possible not possible sdsr not possible possible sddrh possible possible sddrl possible possible sdbpr possible possible 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 697 of 882 rej09b0108-0400 22.3.1 instruction register (sdir) the instruction register (sdir) is a 16-bit register that can be read , but not written to, by the cpu. h-udi instructions can be transferred to sdir from tdi by serial input. sdir can be initialized by the trst signal, but is not initialized in software standby mode. instructions transferred to sdir must be 4 bits in length. if an instructio n exceeding 4 bits is input, the last 4 bits of the serial data will be stored in sdir. bit bit name initial value r/w description 15 14 13 12 ts3 ts2 ts1 ts0 1 1 1 1 r r r r test set bit 0xxx: setting prohibited 100x: setting prohibited 1010: h-udi interrupt 1011: setting prohibited 110x: setting prohibited 1110: setting prohibited 1111: bypass mode [legend] x: don?t care 11 to 0 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 698 of 882 rej09b0108-0400 22.3.2 status register (sdsr) the status register (sdsr) is a 16-bit register that can be read and written to by the cpu. the sdsr value can be output from tdo, but serial data cannot be written to sdsr via tdi. the sdtrf bit is output by means of a one-bit shift. in a two-bit shift, the sdtrf bit is output first, followed by a reserved bit. sdsr is initialized by trst signal input, but is not initialized in software standby mode. bit bit name initial value r/w description 15 to 12 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 11 ? 1 r reserved this bit is always read as 1. the write value should always be 1. 10 to 1 ? all 0 r reserved these bits are always read as 0. the write value should always be 0. 0 sdtrf 1 r/w serial data transfer control flag indicates whether h-udi registers can be accessed by the cpu. the sdtrf bit is initialized by the trst signal, but is not initialized in software standby mode. 0: serial transfer to sddr has ended, and sddr can be accessed 1: serial transfer to sddr is in progress 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 699 of 882 rej09b0108-0400 22.3.3 data register (sddr) the data register (sddr) comprises data register h (sddrh) and data register l (sddrl). sddrh and sddrl are 16-bit registers that can be read and written to by the cpu. sddr is connected to tdo and tdi for serial data tr ansfer to and from an external device. 32-bit data is input and output in serial data tran sfer. if data exceeding 32 bits is input, only the last 32 bits will be stored in sddr. serial data is input starting with the msb of sddr (bit 15 of sddrh), and output starting with the lsb (bit 0 of sddrl). sddr is not initialized by a reset, in software standby mode, or by the trst signal. the initial value of sddr is undefined. 22.3.4 bypass register (sdbpr) the bypass register (sdbpr) is a one-bit shift register. in bypass mode, sdbpr is connected to tdi and tdo, and this lsi is bypassed in a board test. sdbpr cannot be read or written to by the cpu. 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 700 of 882 rej09b0108-0400 22.4 operation 22.4.1 h-udi interrupt when an h-udi interrupt instructio n is transferred to sdir via tdi, an interrupt is generated. data transfer can be controlled by means of the h-udi interrupt service routine. transfer can be performed by means of sddr. control of data input/output between an external device and the h-udi is performed by monitoring the sdtrf bit in sdsr externally and internally. internal sdtrf bit monitoring is carried out by having sdsr read by the cpu. the h-udi interrupt and serial tr ansfer procedure is as follows. 1. an instruction is input to sdir by serial tran sfer, and an h-udi interrupt request is generated. 2. after the h-udi interrupt request is issued, the sdtrf bit in sdsr is monitored externally. after output of sdtrf = 1 from tdo is observed, serial data is transferred to sddr. 3. on completion of the serial transfer to sddr, the sdtrf bit is cleared to 0, and sddr can be accessed by the cpu. after sddr has been accesse d, sddr serial transfer is enabled by setting the sdtrf bit in sdsr to 1. 4. serial data transfer between an external devi ce and the h-udi can be carried out by constantly monitoring the sdtrf bit in sdsr externally and internally. figure 22.2, figure 22.3, and figure 22.4 show the timing of data transfer between an external device and the h-udi. 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 701 of 882 rej09b0108-0400 sdtrf (in sdsr) * 1 h-udi interrupt request serial data sdsr and sddr mux * 2 sddr access state input/ output sdtrf input shift enabled sddr sddr sdsr sdsr serial transfer (monitorin g ) instruc- tion 1 1 0 shift disabled sdsr shift shift cpu cpu notes: 1. sdtrf fla g (in sdsr): indicates whether sddr access by the cpu or serial transfer data input/output to sddr is possible. 1 sddr is shift-enabled. do not access sddr until sdtrf = 0. 0 sddr is shift-disabled. sddr access by the cpu is enabled. conditions: ? sdtrf = 1 ? when trst = 0 ? when the cpu writes 1 ? in bypass mode ? sdtrf = 0 ? end of sddr shift access in serial transfer 2. sdsr/sddr (update-dr state) internal mux switchover timin g ? switchover from sdsr to sddr: on completion of serial transfer in which sdtrf = 1 is output from tdo ? switchover from sddr to sdsr: on completion of serial transfer to sddr shift enabled figure 22.2 data input/output timing chart (1) 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 702 of 882 rej09b0108-0400 tck tms tdi tdo trst test-lo g ic-reset run-test/idle select-dr select-ir capture-ir shift-ir update-ir select-dr capture-dr shift-dr test-lo g ic-reset run-test/idle exit1-dr update-dr ts0 ts3 sdtrf exit1-ir figure 22.3 data input/output timing chart (2) tck tms tdi tdo trst select-dr select-dr capture-dr shift-dr exit1-dr update-dr select-dr capture-dr shift-dr update-dr bit 0 sdtrf shift-dr capture-dr shift-dr select-dr update-dr capture-dr update-dr exit1-dr exit1-dr exit1-dr bit 31 bit 0 bit 31 sdtrf bit 0 bit 31 bit 0 bit 31 figure 22.4 data input/output timing chart (3) 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 703 of 882 rej09b0108-0400 22.4.2 bypass mode bypass mode can be used to bypass this lsi in a boundary-scan test. bypass mode is entered by transferring b'1111 to sdir. in bypass mode, sdbpr is connected to tdi and tdo. 22.4.3 h-udi reset the h-udi can be reset as follows. ? by holding the trst signal at 0 ? when trst = 1, by inputting at least five tck clock cycles while tms = 1 22. user debugging interface (h-udi) rev.4.00 mar. 27, 2008 page 704 of 882 rej09b0108-0400 22.5 usage notes ? the registers are not initialized in software standby mode. if trst is set to 0 in software standby mode, bypass mode will be entered. ? the frequency of tck must be lower than that of the peripheral module clock (p ). for details, see section 26, electrical characteristics. ? in serial data transfer, data input/output starts with the lsb. figure 22.5 shows serial data input/output. ? if the h-udi serial transfer sequence is disrupted, a trst reset must be executed. transfer should then be retried, regardless of the transfer operation. ? the tdo output timing is from the rise of tck. ? in the shift-ir state, the lower 2 bits of the output data from tdo (the ir status word) may not always be 01. ? if more than 32 bits are serially transferred, serial data exceeding 32 bits output from tdo should be ignored. ? the tdi pin must not be in the high-impedance state. shift re g ister sdir, sdsr, sddrh/sddrl 31 30 1 0 tdi tdo serial data input/output is in lsb-first order. figure 22.5 serial data input/output 23. advanced user debugger (aud) aud0001a_020020030800 rev.4.00 mar. 27, 2008 page 705 of 882 rej09b0108-0400 section 23 advanced user debugger (aud) 23.1 overview this lsi has an on-chip advanced user debugger (aud). use of the aud simplifies the construction of a simple emulator , with functions such as acqui sition of branch trace data and monitoring/tuning of on-chip ram data. aud can be enabled or disabled using the audsrst bit in the system control register (syscr). refer to section 24.2.2, system co ntrol register (syscr), for syscr. 23.1.1 features the aud has the fo llowing features: ? eight input/output pins ? data bus (audata3-audata0) ? aud reset ( audrst ) ? aud sync signal ( audsync ) ? aud clock (audck) ? aud mode (audmd) ? two modes ? branch trace mode ? ram monitor mode 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 706 of 882 rej09b0108-0400 23.1.2 block diagram figure 23.1 shows a block diagram of the aud. pc output circuit address buffer data buffer mode control internal bus bus controller peripheral module bus on-chip memory on-chip peripheral module cpu audata0 audata1 audata2 audata3 audrst audmd audck audsync figure 23.1 aud block diagram 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 707 of 882 rej09b0108-0400 23.2 input/output pins table 23.1 shows the aud's input/output pins. table 23.1 aud pin configuration function name abbreviation branch trace mode ram monitor mode aud data audata3 to audata0 branch destination address output monitor address/data input/output aud reset audrst aud reset input aud reset input aud mode audmd mode select input (l) mode select input (h) aud clock audck sync clock ( /2) output sync clock input aud sync signal audsync data start position identification signal output data start position identification signal input 23.2.1 pin descriptions ? pins used in both modes pin description audmd the mode is selected by changi ng the input level at this pin. low: branch trace mode high: ram monitor mode the input at this pin should be changed when audrst is low. audrst the aud's internal buffers and logic are initialized by inputting a low level to this pin. when this signal goes low, the aud enters the reset state and the aud's internal buffers and logic are reset. when audrst goes high again after the audmd level settles, the aud st arts operating in the selected mode. 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 708 of 882 rej09b0108-0400 ? pin functions in branch trace mode pin description audck this pin outputs 1/2 the operating frequency ( /2). this is the clock for audata synchronization. audsync this pin indicates whether output from audata is valid. high: valid address data is not being output low: valid address is being output 1. when audsync is low when a program branch or interrupt branch occurs, the aud asserts audsync and outputs the branch destinati on address. the output order is as follows: a3 to a0, a7 to a4, a11 to a8, a15 to a12, a19 to a16, a23 to a20, a27 to a24, a31 to a28. 2. when audsync is high when waiting for branch destination addr ess output, these pins constantly output 0011. when an branch occurs, audata3 and audata2 output 10, and audata1 and audata0 indicate whether a 4-, 8-, 16-, or 32-bit address is to be output by comparing the pr evious fully output address with the address output this time (see table below). audata1 and audata0 settings 00 address bits a31 to a4 match; 4 address bits a3 to a0 are to be output (i.e. output is performed once). 01 address bits a31 to a8 match; 8 address bits a3 to a0 and a7 to a4 are to be output (i.e. output is performed twice). 10 address bits a31 to a16 match; 16 address bits a3 to a0, a7 to a4, a11 to a8, and a15 to a12 are to be output (i.e. output is performed four times). audata3 to audata0 11 none of the above cases applies; 32 address bits a3 to a0, a7 to a4, a11 to a8, a15 to a12, a19 to a16, a23 to a20, a27 to a24, and a31 to a28 are to be output (i.e. output is performed eight times). 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 709 of 882 rej09b0108-0400 ? pin functions in ram monitor mode pin description audck the external clock input pin. input the clock to be used for debugging to this pin. the input frequency must not exceed 1/4 the operating frequency. audsync do not assert this pin until a command is input to audata externally and the necessary data can be prepared. for deta ils, see the protocol description in the following. audata3 to audata0 when a command is input externally, data is output after ready transmit. output starts when audsync is negated. for details, see the protocol description in the following. 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 710 of 882 rej09b0108-0400 23.3 branch trace mode 23.3.1 overview in this mode, the branch destination address is ou tput when a branch occurs in the user program. branches may be caused by branch instruction execution or interrupt/exception processing, but no distinction is made between the two in this mode. 23.3.2 operation operation starts in branch trace mode when audrst is asserted, audmd is driven low, and then audrst is negated. figure 23.2 shows an example of data output. while the user program is being executed withou t branches, the audata pins constantly output 0011 in synchronization with audck. when a branch occurs, after execution starts at the branch destination address in the pc, the previous fully output address (i.e. for which output was not interrupted by the occurrence of another branch) is compared with the current branch address, and depending on the result, audsync is asserted and the branch destination address output after 1-clock output of 1000 (in the case of 4-bit output), 1001 (8-bit output), 1010 (16-bit output), or 1011 (32-bit output). the initial value of the compared address is h'00000000. on completion of the cycle in which the address is output, audsync is negated and 0011 is simultaneously output from the audata pins. if another branch occurs during branch destination address output, the later branch has priority for output. in this case, audsync is negated and the audata pins output the address after outputting 10xx again (figure 23.3 shows an example of the output when consecutive branches occur). note that the compared address is the previous fully output address, and not an interrupted address (since the upper address of an interrupted address will be unknown). the interval from the start of execution at the branch destina tion address in the pc until the audata pins output 10xx is 1.5 or 2 audck cycles. 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 711 of 882 rej09b0108-0400 audck 0011 0011 1011 a3 to a0 a7 to a4 a11 to a8 a15 to a12 a19 to a16 a23 to a20 a27 to a24 a31 to a28 0011 audsync audata [3:0] start of execution at branch destination address in pc figure 23.2 example of data output (32-bit output) audck 0011 0011 1011 a3 to a0 0011 0011 a3 to a0 a7 to a4 1010 a7 to a4 a11 to a8 a15 to a12 audsync audata [3:0] start of execution at branch destination address in pc (1) start of execution at branch destination address in pc (2) figure 23.3 example of output in case of successive branches 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 712 of 882 rej09b0108-0400 23.4 ram monitor mode 23.4.1 overview in this mode, all the modules connected to this lsi's internal or external bus can be read and written to, allowing ram monitoring and tuning to be carried out. when an address is written to audata externally, the data corresponding to that address is output. if an address and data are written to auda ta, the data is transferred to the address. 23.4.2 communication protocol the aud latches the audata input when audsync is asserted. the following audata input format should be used. 0000 dir a3 to a0 a31 to a28 d3 to d0 dn to dn-3 input format spare bits (4 bits): b'0000 command fixed at 1 0: read 1: write 00: byte 01: word 10: lon g word bit 3 bit 2 bit 1 bit 0 . . . . . . . . . . . . address data (in case of write only) b write: n = 7 w write: n = 15 l write: n = 31 figure 23.4 audata input format 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 713 of 882 rej09b0108-0400 23.4.3 operation operation starts in ram monitor mode when audrst is asserted, audmd is driven high, then audrst is negated. figure 23.5 shows an example of a read oper ation, and figure 23.6 an example of a write operation. when audsync is asserted, input from the audata pins begins. when a command, address, or data (writing only) is input in the format shown in figure 23.4, execution of read/write access to the specified address is started. during internal execution, th e aud returns not ready (0000). when execution is completed, the ready flag (0 001) is returned (figures 23.5 and 23.6). table 23.2 shows the ready flag format. in a read, data of the specified size is output when audsync is negated following detection of this flag (figure 23.5). if a command other than the above is input in dir, the aud treats this as a command error, disables processing, and sets bit 1 in the ready flag to 1. if a read/write operation initiated by the command specified in dir causes a bus error, the aud disables processing and sets bit 2 in the ready flag to 1 (figure 23.7). bus error conditions are shown below. 1. word access to ad dress 4n+1 or 4n+3 2. longword access to address 4n+1, 4n+2, or 4n+3 3. longword access to on-chip i/o 8-bit area 4. access to external area in single-chip mode table 23.2 ready flag format bit 3 bit 2 bit 1 bit 0 fixed at 0 0: normal status 1: bus error 0: normal status 1: command error 0: not ready 1: ready 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 714 of 882 rej09b0108-0400 audck not ready dir ready ready ready 0001 0001 0000 0000 1000 0001 a31 to a28 d7 to d4 d3 to d0 a3 to a0 audsync audatan input/output chan g eover input output figure 23.5 example of read operation (byte read) audck not ready ready dir ready ready 0000 0000 1110 0001 0001 0001 a31 to a28 d3 to d0 d31 to d28 a3 to a0 audatan input/output chan g eover input output audsync figure 23.6 example of writ e operation (longword write) audck not ready dir ready (bus error) ready (bus error) ready (bus error) 0101 0101 0000 0000 1010 0101 a31 to a28 a3 to a0 audsync audatan input/output chan g eover input output figure 23.7 example of e rror occurrence (longword read) 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 715 of 882 rej09b0108-0400 23.5 usage notes 23.5.1 initialization the debugger's internal buffers and processing states are initialized in the following cases: 1. in a power-on reset 2. when audrst is driven low 3. when the audsrst bit in the syscr register is cleared to 0 (see section 24.2.2, system control register (syscr)) 4. when the mstp3 bit in the mstcr2 register is set to 1 (see section 24.2.3, module standby control register 1 and 2 (mstcr1 and mstcr2)) 23.5.2 operation in software standby mode the debugger is not initialized in software st andby mode. however, since this lsi's internal operation halts in software standby mode: 1. when audmd is high (ram monitor mode), ready is not returned (not ready continues to be returned). however, when operating on an external clock, the protocol continues. 2. when audmd is low (branch trace mode), operation stops. however, operation continues when software standby is released. 23.5.3 setting the pa15/ck pin some debug tools have specification that the audck signal is generated out of the ck signal. decide the pin function controller setting after reading the manual of the debug tool to be used. 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 716 of 882 rej09b0108-0400 23.5.4 pin states 1. module standby audmd z audck z audsync z audata z 2. audrst = low-level input audmd input audck (1) audmd = high: input (2) audmd = low: high-level output audsync (1) audmd = high: input (2) audmd = low: high-level output audrst low-level input audata (1) audmd = high: input (2) audmd = low: high-level output 3. normal operation/software standby audrst = 1 audmd input audck (1) audmd = high: input (2) audmd = low: output audsync (1) audmd = high: input (2) audmd = low: output audrst high-level input audata (1) audmd = high: input/output (2) audmd = low: output 23.5.5 aud start-up sequence follow the sequence described below to start up the aud. after selecting the aud pin by the pfc, input at least three clocks to the audck pin while retaining the audrst pin at low level. then, set the aud reset bit (audsrst) in syscr to clear the aud reset. low level input to the audrst pin and clock input to the audck pin can be started prior to the selection of the aud pin by the pfc. 23.5.6 ram monitor operation using the pd22/audck pin while using the pd22/audck pin for ram monitor function, the pe3/audata3, pe4/audata2, pe5/audata1, pe6/audata0, and pa16/ audsync pins are not available. instead of those unavailable pins, the pd19/audata3, pd18/audata2, pd17/audata1, pd16/audata0 and pd23/ audsync pins must be used. 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 717 of 882 rej09b0108-0400 23.5.7 settings of aud-related pins when using e10a when using the e10a and aud functions of the sh7145, use port d and the multiplexed aud- related pins. 23. advanced user debugger (aud) rev.4.00 mar. 27, 2008 page 718 of 882 rej09b0108-0400 24. power-down modes lpwsh21a_010020030800 rev.4.00 mar. 27, 2008 page 719 of 882 rej09b0108-0400 section 24 power-down modes in addition to the normal program execution state, this lsi has three power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip peripheral functions, and so on. this lsi's power-down modes are as follows: ? sleep mode ? software standby mode ? module standby mode sleep mode indicates the state of the cpu, and mo dule standby mode indicat es the state of the on- chip peripheral function (including the bus master other than the cpu). so me of these states can be combined. after a reset, the lsi is in normal-operation mode. table 24.1 lists internal oper ation states in each mode. 24. power-down modes rev.4.00 mar. 27, 2008 page 720 of 882 rej09b0108-0400 table 24.1 internal operat ion states in each mode function normal operation sleep module standby software standby system clock pulse generator functioning functioning ? halted cpu functioning halted (retained) ? halted (retained) nmi functioning functioning ? functioning external interrupts irq7 to irq0 ubc functioning functioning halted (reset) halted (retained) dmac dtc peripheral functions iic functioning functioning halted (reset) halted (reset) i/o port functioning functioning ? halted (retained) wdt functioning functioning ? halted (retained) sci a/d mtu cmt functioning functioning halted (reset) halted (reset) h-udi functioning functioning halted (retained) halted (retained) aud rom functioning functioning halted (reset) halted (reset) ram functioning functioning halted (retained) halted (retained) notes: 1. "halted (retained)" means that the operat ion of the internal state is suspended, although internal register values are retained. 2. "halted (reset)" means that internal regi ster values and internal state are initialized. 3. in module standby mode, only modules for which a stop setting has been made are halted (reset or retained). 4. there are two types of on-chip peripheral module registers; ones which are initialized by module standby mode or software standby mode, and those not initialized by that mode. for details, refer to section 25.3, r egister states in each operating mode. 5. the port high-impedance bit (hiz) in sby cr sets the state of the i/o port in software standby mode. for details on the setting, re fer to section 24.2.1, standby control register (sbycr). for the state of pi ns, refer to appendix a, pin states. 24. power-down modes rev.4.00 mar. 27, 2008 page 721 of 882 rej09b0108-0400 24.1 input/output pins table 24.2 lists the pins relating to power-down mode. table 24.2 pin configuration pin name i/o function res input power-on reset input pin mres input manual reset input pin 24.2 register descriptions registers related to power down modes are shown below. for details on register addresses and register states during eac h process, refer to section 25, list of registers. ? standby control register (sbycr) ? system control register (syscr) ? module standby control register 1 (mstcr1) ? module standby control register 2 (mstcr2) 24. power-down modes rev.4.00 mar. 27, 2008 page 722 of 882 rej09b0108-0400 24.2.1 standby control register (sbycr) sbycr is an 8-bit readable/writable register that performs software standby mode control. bit bit name initial value r/w description 7 ssby 0 r/w software standby this bit specifies the transition mode after executing the sleep instruction. 0: shifts to sleep mode after the sleep instruction has been executed 1: shifts to software standby mode after the sleep instruction has been executed this bit cannot be set to 1 when the watchdog timer (wdt) is operating (when the tme bit in tcsr of the wdt is set to 1). when transferring to software standby mode, clear the tme bit to 0, stop the wdt, then set the ssby bit to 1. 6 hi-z 0 r/w port high-impedance in software standby mode, this bit selects whether the pin state of the i/o port is retained or changed to high-impedance. 0: in software standby mode, the pin state is retained. 1: in software standby mode, the pin state is changed to high-impedance. the hiz bit cannot be set to 1 when the tme bit in tcsr of the wdt is set to 1. when changing the pin stat e of the i/o port to high- impedance, clear the tme bit to 0, then set the hiz bit to 1. 5 ? 0 r reserved this bit is always read as 0, and should always be written with 0. 4 to 2 ? all 1 r reserved these bits are always read as 1, and should always be written with 1. 24. power-down modes rev.4.00 mar. 27, 2008 page 723 of 882 rej09b0108-0400 bit bit name initial value r/w description 1 irqeh 1 r/w irq7 to irq4 enable irq7 to irq4 interrupts are enabled to clear software standby mode. 0: enable to clear the software standby mode 1: disable to clear the software standby mode 0 irqel 1 r/w irq3 to irq0 enable irq3 to irq0 interrupts are enabled to clear software standby mode. 0: enable to clear the software standby mode 1: disable to clear the software standby mode 24. power-down modes rev.4.00 mar. 27, 2008 page 724 of 882 rej09b0108-0400 24.2.2 system control register (syscr) syscr is an 8-bit readable/writable register that performs aud software reset control and enables/disables the acces s to the on-chip ram. bit bit name initial value r/w description 7, 6 ? all 1 r reserved these bits are always read as 1, and should always be written with 1. 5 to 2 ? all 0 r reserved these bits are always read as 0, and should always be written with 0. 1 audsrst 0 r/w aud software reset this bit controls the aud reset by software. when 0 is written to audsrst, aud module shifts to power- on reset state. 0: shifts to aud reset state. 1: clears the aud reset. 0 rame 1 r/w ram enable this bit enables/disables the on-chip ram. 0: on-chip ram disabled 1: on-chip ram enabled when this bit is cleared to 0, the access the on-chip ram is disabled. in this case, an undefined value is returned when reading or fetching the data or instruction from the on-chip ram, and writing to the on-chip ram is ignored. when rame is cleared to 0 to disable the on-chip ram, an instruction to access the on-chip ram should not be set next to the instruction to write to syscr. if such an instruct ion is set, normal access is not guaranteed. when rame is set to 1 to enable the on-chip ram, an instruction to read syscr should be set next to the instruction to write to syscr. if an instruction to access the on-chip ram is set next to the instruction to write to syscr, normal access is not guaranteed. 24. power-down modes rev.4.00 mar. 27, 2008 page 725 of 882 rej09b0108-0400 24.2.3 module standby control register 1 and 2 (mstcr1 and mstcr2) mstcr, comprising two 16-bit readable/writabl e registers, performs module standby mode control. setting a bit to 1, the corresponding module enters module standby mode, while clearing the bit to 0 clears the module standby mode. ? mstcr1 bit bit name initial value r/w description 15 to 12 ? all 1 r reserved these bits are always read as 1, and should always be written with 1. 11 mstp27 0 r/w on-chip ram 10 mstp26 0 r/w on-chip rom 9 mstp25 0 r/w 8 mstp24 0 r/w data transfer controller (dtc) direct memory access controller (dmac) set the identical value to mstp25 and mstp24, respectively. when setting module standby, write b'11, while clearing, write b'00. 7, 6 ? all 0 r reserved these bits are always read as 0, and should always be written with 0. 5 mstp21 1 r/w i 2 c bus interface (iic) 4 ? 1 r reserved these bits are always read as 1, and should always be written with 1. 3 mstp19 1 r/w serial communication interface 3 (sci_3) 2 mstp18 1 r/w serial communication interface 2 (sci_2) 1 mstp17 1 r/w serial communication interface 1 (sci_1) 0 mstp16 1 r/w serial communication interface 0 (sci_0) 24. power-down modes rev.4.00 mar. 27, 2008 page 726 of 882 rej09b0108-0400 ? mstcr2 bit bit name initial value r/w description 15, 14 ? all 1 r reserved this bit is always read as 1, and should always be written with 1. 13 mstp13 1 r/w multi-function timer pulse unit (mtu) 12 mstp12 1 r/w compare match timer (cmt) 11 to 8 ? all 0 r reserved these bits are always read as 0, and should always be written with 0. 7, 6 ? all 1 r reserved these bits are always read as 1, and should always be written with 1. 5 mstp5 1 r/w a/d converter (a/d1) 4 mstp4 1 r/w a/d converter (a/d0) 3 mstp3 0 r/w advanced user debugger (aud) * 2 mstp2 0 r/w user debugging interface (h-udi) * 1 ? 0 r reserved this bit is always read as 0, and should always be written with 0. 0 mstp0 0 r/w user break controller (ubc) note: * although this bit can be read from/written to when using e10a (in dbgmd=h), aud or h-udi is in normal operation regardless of the set value. 24. power-down modes rev.4.00 mar. 27, 2008 page 727 of 882 rej09b0108-0400 24.3 operation 24.3.1 sleep mode transition to sleep mode: if sleep instruction is executed while the ssby bit in sbycr = 0, the cpu enters sleep mode. in sleep mode, cpu operation stops, however the contents of the cpu's internal registers are retained. peri pheral functions except the cpu do not stop. in sleep mode, data should not be accessed by the dmac, dtc, or aud. clearing sleep mode: sleep mode is cleared by the conditions below. ? clearing by the power-on reset when the res pin is driven low, the cpu enters the reset state. when the res pin is driven high after the elapse of the specified reset in put period, the cpu starts the reset exception handling. when an internal power-on reset by wd t occurs, sleep mode is also cleared. ? clearing by the manual reset when the mres pin is driven low while the res pin is high, the cpu shifts to the manual reset state and thus sl eep mode is cleared. when an internal manual reset by wdt occurs, sleep mode is also cleared. 24. power-down modes rev.4.00 mar. 27, 2008 page 728 of 882 rej09b0108-0400 24.3.2 software standby mode transition to software standby mode: a transition is made to software standby mode if the sleep instruction is executed while the ssby bit in sbycr is set to 1. in this mode, the cpu, on-chip peripheral functions, and the oscillator, all stop. however, the contents of the cpu's internal regi sters and on-chip ram data are retained as long as the specified voltage is supplied. there are two types of on-chip peripheral module registers; ones which are initialized by software standby mode, and those not initialized by that mode. for details, refer to section 25.3, register states in each operating mode. the port high-impedance bit (hi-z) in sbycr sets the state of the i/o port e ither to "retained" or "high-impedance". for the state of pins, refer to appendix a, pin states. in software standby mode, the oscillator stops and thus power consumption is significantly reduced. clearing software standby mode: software standby mode is cleared by the condition below. ? clearing by the nmi interrupt input when the falling edge or rising edge of the nmi pin (selected by the nmi edge select bit (nmie) in icr1 of the interrupt controller (intc)) is detected, clock oscillation is started. this clock pulse is supplied only to the watchdog timer (wdt). after the elapse of the time set in the clock select bits (cks2 to cks0) in tcsr of the wdt before the transition to software standby mode, the wdt overflow occurs. since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. software standby mode is thus cleared and the nmi exception handling is started. when clearing software standby mode by the nmi interrupt, set cks2 to cks0 bits so that the wdt overflow period will be longer than the oscillation stabilization time. when so&tware standby mode is cleared by the falling edge of the nmi pin, the nmi pin should be high when the cpu enters software standby mode (when the clock pulse stops) and should be low when the cpu returns from standby mode (when the clock is initiated after the oscillation stabilization). when software standby mode is cleared by the rising edge of the nmi pin, the nmi pin should be low when the cpu enters software standby mode (when the clock pulse stops) and should be high when the cpu returns from software standby mode (when the clock is initiated after the oscillation stabilization). ? clearing by the res pin when the res pin is driven low, clock oscillation is started. at the same time as clock oscillation is started, clock pulse is supplied to the entire chip. ensure that the res pin is held low until clock oscillation stabilizes. when the res pin is driven high, the cpu starts the reset exception handling. 24. power-down modes rev.4.00 mar. 27, 2008 page 729 of 882 rej09b0108-0400 ? clearing by the irq interrupt input when the falling edge or rising edge of the irq pin (selected by the irq7s to irq0s bits in icr1 of the interrupt controller (intc) and the irq7es[1:0] to irq0es[1:0] bits in icr2) is detected, clock oscillation is started*. this clock pulse is supplied only to the watchdog timer (wdt). the irq interrupt priority level should be higher than the interrupt mask level set in the status register (sr) of the cpu before the transition to software standby mode. after the elapse of the time set in the clock select bits (cks2 to cks0) in tcsr of the wdt before the transition to software standby mode, the wdt overflow occurs. since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. software standby mode is thus cleared and the irq exception handling is started. when clearing software standby mode by the irq interrupt, set cks2 to cks0 bits so that the wdt overflow period will be longer than the oscillation stabilization time. when software standby mode is cleared by the falling edge or both rising and falling edges of the irq pin, the irq pin should be high when the cpu enters software standby mode (when the clock pulse stops) and should be low when the cpu returns from software standby mode (when the clock is initiated after the oscillation stabilization). when software standby mode is cleared by the rising edge of the irq pin, the irq pin should be low when the cpu enters software standby mode (when the clock pulse stops) and should be high when the cpu returns from software standby mode (when the clock is initiated after the oscillation stabilization). note: * if the irq pin setting is detection at the falling edge or detection at both rising and falling edges, clock oscillation starts at the falling edge detection. if the setting is detection at the rising edge, it starts at the rising edge detection. do not set the irq pin to detection at the low level. software standby mode application example: figure 24.1 shows an example in which a transition is made to software standby mode at the falling edge of the nmi pin, and software standby mode is cleared at a rising edge of the nmi pin. in this example, when the nmi pin is driven low while the nmi edge select bit (nmie) in icr1 is 0 (falling edge specification), an nm i interrupt is accepted. then, the nmie bit is set to 1 (rising edge specification) in the nmi exception service ro utine, the ssby bit in sbycr is set to 1, and a sleep instruction is executed to transfer to software standby mode. software standby mode is cleared at the rising edge of the nmi pin. 24. power-down modes rev.4.00 mar. 27, 2008 page 730 of 882 rej09b0108-0400 oscillator ck nmi input nmie bit ssby bit lsi state oscillation start time pro g ram execution state exception service routine software standby mode wdt settin g time nmi exception handlin g nmi exception handlin g oscillation stabilization time figure 24.1 nmi timing in softwa re standby mode (application example) 24.3.3 module standby mode module standby mode can be set for individual on-chip peripheral functions. when the corresponding mstp bit in mstcr is set to 1, module operation st ops at the end of the bus cycle and a transition is made to module standby mode. the cpu continues operating independently. when the corresponding mstp bit is cleared to 0, module standby mode is cleared and the module starts operating at the end of the bus cycl e. in some of the modules that have entered module standby mode, register values are initialized . therefore, set registers again when operating the modules. after reset clearing, the i 2 c, sci, mtu, cmt, and a/d converter are in module standby mode. the modules of registers in module standby mode cannot be read or written to. 24. power-down modes rev.4.00 mar. 27, 2008 page 731 of 882 rej09b0108-0400 24.4 usage notes 24.4.1 i/o port status when a transition is made to software standby mode while the port high-impedance bit (hiz) in sbycr is 0, i/o port states are retained. therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 24.4.2 current consumptio n during oscillation stabilization wait period current consumption increases during the oscillation stabilization wait period. 24.4.3 on-chip peripheral module interrupt relevant interrupt operations cannot be performed in module standby mode. consequently, if the cpu enters module standby mode while an interrupt has been requested, it will not be possible to clear the cpu interrupt source or the dmac/dtc activation source. interrupts should therefore be disabled before entering module standby mode. 24.4.4 writing to mstcr1 and mstcr2 mstcr1 and mstcr2 should only be written to by the cpu. 24.4.5 dmac, dtc, or aud operation in sleep mode in sleep mode, data should not be accessed by the dmac, dtc, or aud. 24. power-down modes rev.4.00 mar. 27, 2008 page 732 of 882 rej09b0108-0400 25. list of registers rev.4.00 mar. 27, 2008 page 733 of 882 rej09b0108-0400 section 25 list of registers this section gives information on internal i/o regist ers. the contents of this section are as follows: 1. register address table (in the order from a lower address) ? registers are listed in the order from lower allocated addresses. ? as for reserved addresses, the regist er name column is indicated with ? . do not access reserved addresses. ? as for 16- or 32-bit address, the msb addresses are shown. ? the list is classified according to module names. ? the register access size is shown. 2. register bit table ? bit configurations are shown in the order of the register address table. ? as for reserved bits, the bit name column is indicated with ? . ? as for the blank column of the bit names, the whol e register is allocated to the counter or data. ? as for 16- or 32-bit registers, b its are indicated from the msb. 3. register state in each operating mode ? register states are listed in the or der of the register address table. ? register states in the basic operating mode are shown. as for modules including their specific states such as reset, see th e sections of those modules. 25. list of registers rev.4.00 mar. 27, 2008 page 734 of 882 rej09b0108-0400 25.1 register address table (in the order from lower addresses) access sizes are indicated with th e number of bits. access states are indicated with the number of specified reference clock states. these values ar e those at 8-bit access (b), 16-bit access (w), or 32-bit access (l). note: access to undefined or reserved addresses is prohibited. correct operation cannot be guaranteed if these addresses are accessed. register name abbreviation no. of bits addr ess module access size n o. of access states ? ? ? h'ffff8000 to h'ffff819f ? ? ? serial mode regist er_0 smr_0 8 h'ffff 81a0 sci 8, 16 p reference bit rate register_0 brr_0 8 h'ffff81a1 (channel 0) 8 b:2 serial control register_0 s cr_0 8 h'ffff81a2 8, 16 w:4 transmit data register_0 tdr_0 8 h'ffff81a3 8 serial status re gister_0 ssr_0 8 h 'ffff81a4 8, 16 receive data register_0 rdr_0 8 h'ffff81a5 8 serial direction control register_0 sdcr_0 8 h'ffff81a6 8 ? ? ? h'ffff81a7 to h'ffff81af ? ? serial mode regist er_1 smr_1 8 h'ffff 81b0 sci 8, 16 bit rate register_1 brr_1 8 h'ffff81b1 (channel 1) 8 serial control register_1 scr_1 8 h'ffff81b2 8, 16 transmit data register_1 tdr_1 8 h'ffff81b3 8 serial status re gister_1 ssr_1 8 h 'ffff81b4 8, 16 receive data register_1 rdr_1 8 h'ffff81b5 8 serial direction co ntrol register_1 sdcr _1 8 h'ffff81b6 8 ? ? ? h'ffff81b7 to h'ffff81bf ? ? serial mode regist er_2 smr_2 8 h'ffff 81c0 sci 8, 16 bit rate register_2 brr_2 8 h'ffff81c1 (chann el 2) 8 serial control register_2 scr_2 8 h'ffff81c2 8, 16 transmit data register_2 tdr_2 8 h'ffff81c3 8 serial status re gister_2 ssr_2 8 h 'ffff81c4 8, 16 receive data register_2 rdr_2 8 h'ffff81c5 8 serial direction co ntrol register_2 sdcr _2 8 h'ffff81c6 8 25. list of registers rev.4.00 mar. 27, 2008 page 735 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states ? ? ? h'ffff81c7 to h'ffff81cf ? ? serial mode regi ster_3 smr_3 8 h 'ffff81d0 sci 8, 16 bit rate register_3 brr _3 8 h'ffff81d1 (c hannel 3) 8 p reference b:2 w:4 serial control register_3 scr_3 8 h'ffff81d2 8, 16 transmit data register_3 tdr_3 8 h'ffff81d3 8 serial status regi ster_3 ssr_3 8 h'ffff 81d4 sci 8, 16 receive data register_3 rdr _3 8 h'ffff81d5 (c hannel 3) 8 serial direction co ntrol register_3 sdcr _3 8 h'ffff81d6 8 ? ? ? h'ffff81d7 to h'ffff81ff ? ? timer control register_3 tcr _3 8 h'ffff8200 mtu 8, 16, 32 p reference timer control register_4 tcr_4 8 h'ffff8201 (channels 3, 4) 8 b:2 timer mode register_3 tmdr _3 8 h'ffff8202 8, 16 w:2 timer mode register_4 tmdr_4 8 h'ffff8203 8 l:4 timer i/o control register h_3 t iorh_3 8 h'ffff8204 8, 16, 32 timer i/o control register l_3 tiorl_3 8 h'ffff8205 8 timer i/o control register h_4 tiorh_4 8 h'ffff8206 8, 16 timer i/o control register l_4 tiorl_4 8 h'ffff8207 8 timer interrupt enable register_3 tier_3 8 h 'ffff8208 8, 16, 32 timer interrupt enable regi ster_4 tier_4 8 h'ffff8209 8 timer output master enable regist er toer 8 h'ffff820a 8, 16 timer output control register tocr 8 h'ffff820b 8 ? ? ? h'ffff820c ? timer gate control register tgcr 8 h'ffff820d 8 ? ? ? h'ffff820e ? ? ? ? h'ffff820f timer counter_3 tcnt_3 16 h'ffff8210 16, 32 timer counter_4 tcnt _4 16 h'ffff8212 16 timer cyclic data register tcdr 16 h'ffff8214 16, 32 timer dead time data regi ster tddr 16 h'ffff8216 16 timer general register a_3 tgra_3 16 h'ffff8218 16, 32 timer general register b _3 tgrb_3 16 h'ffff821a 16 timer general register a_4 tgra_4 16 h'ffff821c 16, 32 timer general register b _4 tgrb_4 16 h'ffff821e 16 25. list of registers rev.4.00 mar. 27, 2008 page 736 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states timer sub-counter tcnts 16 h'ffff8220 mtu 16, 32 p reference timer cyclic buffer register tcbr 16 h'ffff8222 (channels 3, 4) 16 b:2 timer general regist er c_3 tgrc_3 16 h 'ffff8224 16, 32 w:2 timer general register d _3 tgrd_3 16 h'ffff8226 16 l:4 timer general regist er c_4 tgrc_4 16 h'ffff8228 16, 32 timer general register d _4 tgrd_4 16 h'ffff822a 16 timer status register_3 ts r_3 8 h'ffff822c 8, 16 timer status register_4 tsr_4 8 h'ffff822d 8 ? ? ? h'ffff822e to h'ffff823f ? timer start register tstr 8 h'ffff8240 8, 16 timer synchronous regi ster tsyr 8 h'ffff8241 mtu (for all channels) 8 ? ? ? h'ffff8242 to h'ffff825f ? p reference b:2 w:2 timer control register_0 tcr _0 8 h'ffff8260 mtu 8, 16, 32 p reference timer mode register _0 tmdr_0 8 h'ffff8261 (channel 0) 8 b:2 timer i/o control register h_0 tiorh_0 8 h'ffff8262 8, 16 w:2 timer i/o control register l_0 tiorl_0 8 h'ffff8263 8 l:4 timer interrupt enable register_0 tier_0 8 h 'ffff8264 8, 16, 32 timer status register_0 tsr_0 8 h'ffff8265 8 timer counter_0 tcnt _0 16 h'ffff8266 16 timer general register a_0 tgra_0 16 h'ffff8268 16, 32 timer general register b _0 tgrb_0 16 h'ffff826a 16 timer general regist er c_0 tgrc_0 16 h 'ffff826c 16, 32 timer general register d _0 tgrd_0 16 h'ffff826e 16 ? ? ? h'ffff8270 to h'ffff827f ? 25. list of registers rev.4.00 mar. 27, 2008 page 737 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states timer control register_1 t cr_1 8 h'ffff8280 mtu 8, 16 p reference timer mode register _1 tmdr_1 8 h'ffff8281 (channel 1) 8 b:2 timer i/o control register _1 tior_1 8 h'ffff8282 8 w:2 ? ? ? h'ffff8283 ? l:4 timer interrupt enable register_1 tier_1 8 h 'ffff8284 8, 16, 32 timer status register_1 tsr_1 8 h'ffff8285 8 timer counter_1 tcnt _1 16 h'ffff8286 16 timer general register a_1 tgra_1 16 h'ffff8288 16, 32 timer general register b _1 tgrb_1 16 h'ffff828a 16 ? ? ? h'ffff828c to h'ffff829f ? timer control register_2 tcr_2 8 h'ffff82a0 mtu (channel 2) 8, 16 timer mode register_2 tm dr_2 8 h'ffff82a1 mtu 8 timer i/o control register_2 tior _2 8 h'ffff82a2 (channel 2) 8 ? ? ? h'ffff82a3 ? timer interrupt enable register_2 tier_2 8 h'ffff 82a4 8, 16, 32 timer status register_2 tsr_2 8 h'ffff82a5 8 timer counter_2 tcnt _2 16 h'ffff82a6 16 timer general register a_2 tgra_2 16 h'ffff82a8 16, 32 timer general register b _2 tgrb_2 16 h'ffff82aa 16 ? ? ? h'ffff82ac to ? h'ffff833f 25. list of registers rev.4.00 mar. 27, 2008 page 738 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states ? ? ? h'ffff8340 to h'ffff8347 intc ? interrupt priority register a ipra 16 h'ffff8348 8, 16, 32 interrupt priority register b iprb 16 h'ffff834a 8, 16 reference b:2 w:2 l:4 interrupt priority register c iprc 16 h'ffff834c 8, 16, 32 interrupt priority register d iprd 16 h'ffff834e 8, 16 interrupt priority register e ipre 16 h'ffff8350 8, 16, 32 interrupt priority register f iprf 16 h'ffff8352 8, 16 interrupt priority register g iprg 16 h'ffff8354 8, 16, 32 interrupt priority register h iprh 16 h'ffff8356 8, 16 interrupt control register1 icr1 16 h'ffff8358 8, 16, 32 irq status register is r 16 h'ffff835a 8, 16 interrupt priority register i ipri 16 h'ffff835c 8, 16, 32 interrupt priority register j iprj 16 h'ffff835e 8, 16 ? ? ? h'ffff8360 to h'ffff8365 ? interrupt control register 2 icr2 16 h'ffff8366 8, 16 ? ? ? h'ffff8368 to h'ffff837f ? port a data register h padrh 16 h'ffff8380 i/o 8, 16, 32 port a data register l pa drl 16 h'ffff8382 8, 16 port a i/o register h paiorh 16 h'ffff8384 pfc 8, 16, 32 port a i/o register l paiorl 16 h'ffff8386 8, 16 port a control register h pacrh 16 h'ffff8388 8, 16, 32 ? ? ? h?ffff838a ? port a control register l1 pa crl1 16 h?ffff838c 8, 16, 32 port a control register l2 pacrl2 16 h?ffff838e 8, 16 port b data register pbdr 16 h?ffff8390 i/o 8, 16, 32 port c data register pcdr 16 h?ffff8392 8, 16 port b i/o register pbior 16 h'ffff8394 pfc 8, 16, 32 port c i/o register pc ior 16 h'ffff8396 8, 16 port b control register 1 pbcr1 16 h'ffff8398 8, 16, 32 port b control register 2 pbcr2 16 h'ffff839a 8, 16 port c control register 2 pccr 16 h'ffff839c 8, 16, 32 25. list of registers rev.4.00 mar. 27, 2008 page 739 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states ? ? ? h'ffff839e to h'ffff839f ? ? port d data register h pddrh 16 h'ffff83a0 i/o 8, 16, 32 port d data register l pddrl 16 h'ffff83a2 8, 16 port d i/o register h pdiorh 16 h'ffff83a4 pfc 8, 16, 32 port d i/o register l pd iorl 16 h'ffff83a6 8, 16 port d control register h1 pdcrh1 16 h'ffff83a8 8, 16, 32 port d control register h2 pdcrh2 16 h'ffff83aa 8, 16 port d control register l1 p dcrl1 16 h'ffff83ac 8, 16, 32 port d control register l2 pdcrl2 16 h'ffff83ae 8, 16 port e data register l pedrl 16 h'ffff83b0 i/o 8, 16, 32 ? ? ? h'ffff83b2 ? ? port f data register pfdr 8 h'ffff83b3 i/o 8 port e i/o register l peiorl 16 h'ffff83b4 pfc 8, 16, 32 ? ? ? h'ffff83b6 to h'ffff83b7 ? ? port e control register l1 pecrl1 16 h'ffff83b8 pfc 8, 16, 32 port e control register l2 pecrl2 16 h'ffff83ba 8, 16 ? ? ? h'ffff83bc to h'ffff83bf ? ? reference b:2 w:2 l:4 input control/status register 1 icsr 1 16 h'ffff83c0 poe 8, 16, 32 output control/stat us register ocsr 16 h'ffff83c2 8, 16 ? ? ? h'ffff83c4 to h'ffff83cf ? ? 25. list of registers rev.4.00 mar. 27, 2008 page 740 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states compare match timer star t register cmstr 16 h 'ffff83d0 cmt 8, 16, 32 compare match timer control/ status register_0 cmcsr_0 16 h'ffff83d2 8, 16 compare match timer counter_0 cm cnt_0 16 h'ffff83d4 8, 16, 32 compare match timer cons tant register_0 cmcor _0 16 h'ffff83d6 8, 16 p reference b:2 w:2 l:4 compare match timer control/ status register_1 cmcsr_1 16 h'ffff83d8 8, 16, 32 compare match timer counter_1 cmcnt_1 16 h'ffff83da 8, 16 compare match timer cons tant register_1 cmcor _1 16 h'ffff83dc 8, 16 ? ? ? h'ffff83de to h'ffff841f ? ? ? a/d data register 0 addr0 16 h'ffff8420 a/d 8, 16 a/d data register 1 addr1 16 h'ffff8422 (channel0) 8, 16 a/d data register 2 addr2 16 h'ffff8424 8, 16 a/d data register 3 addr3 16 h'ffff8426 8, 16 a/d data register 4 addr4 16 h'ffff8428 a/d 8, 16 a/d data register 5 addr5 16 h'ffff842a (channel1) 8, 16 a/d data register 6 addr6 16 h'ffff842c 8, 16 a/d data register 7 addr7 16 h'ffff842e 8, 16 ? ? ? h'ffff8430 to h'ffff847f ? ? a/d control/status register_0 adcsr_0 8 h'ffff8480 a/d 8, 16 a/d control/status register_1 adcsr_1 8 h'ffff8481 8 ? ? ? h'ffff8482 to h'ffff8487 ? a/d control register_0 a dcr_0 8 h'ffff8488 a/d 8, 16 a/d control register _1 adcr_1 8 h'ffff8489 8 p reference b:3 w:6 ? ? ? h'ffff848a to h?ffff857f ? 25. list of registers rev.4.00 mar. 27, 2008 page 741 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states flash memory control register 1 flmcr1 8 h'ffff8580 8, 16 flash memory control regi ster 2 flmcr2 8 h'ffff8581 8 erase block register 1 ebr1 8 h'ffff8582 8, 16 erase block register 2 ebr2 8 h'ffff8583 8 ? ? ? h'ffff8584 to h'ffff85ff flash (only in f- ztat version) ? reference b:3 w:6 user break address register h ubarh 16 h'ffff8600 ubc 8, 16, 32 user break address register l ubarl 16 h'ffff8602 8, 16 user break address mask register h ubamrh 16 h'ffff8604 8, 16, 32 user break address mask register l ubamrl 16 h'ffff8606 8, 16 user break bus cycle register ubbr 16 h 'ffff8608 8, 16, 32 user break control register ubcr 16 h'ffff860a 8, 16 reference b:3 w:3 l:6 ? ? ? h'ffff860c to h'ffff860f ? timer control/status register tcsr 8 h'ffff8610 wdt 8 * 2 /16 * 1 reference timer counter tcnt * 1 8 h'ffff8610 * 1: write 16 b:3 timer counter tcnt * 2 8 h'ffff8611 * 2: read 8 w:3 reset control/status register rstcsr * 1 8 h'ffff8612 16 reset control/status register rstcsr * 2 8 h'ffff8613 8 standby control register sbycr 8 h'ffff8614 power-down modes 8 reference b:3 ? ? ? h'ffff8615 to h'ffff8617 ? ? ? system control register syscr 8 h'ffff8618 8 ? ? ? h'ffff8619 to h'ffff861b power-down modes ? module standby control register 1 mstcr1 16 h'ffff861c 8, 16, 32 p reference b:3 w:3 l:6 module standby control register 2 mstcr2 16 h'ffff861e 8, 16 25. list of registers rev.4.00 mar. 27, 2008 page 742 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states bus control register 1 bcr1 16 h'ffff8620 bsc 8, 16, 32 bus control register 2 bcr2 16 h'ffff8622 8, 16 wait control register 1 wcr1 16 h'ffff8624 8, 16, 32 wait control register 2 wcr2 16 h'ffff8626 8, 16 reference b:3 w:3 l:6 ram emulation register ramer 16 h'ffff8628 flash (only in f- ztat version) 8, 16 reference b:3 w:3 ? ? ? h'ffff862a to h'ffff86af ? ? ? dma operation register dm aor 16 h'ffff86b0 8, 16 ? ? ? h'ffff86b2 to h'ffff86bf dmac (for all channels) ? dma source addres s register_0 sar_0 32 h'ffff 86c0 dmac 8, 16, 32 reference w:3 l:6 dma destination address r egister_0 dar_0 32 h'ffff86c4 (channel 0) 8, 16, 32 dma transfer coun t register_0 dmat cr_0 32 h'ffff86c8 8, 16, 32 dma channel control register_0 chcr_0 32 h'ffff86cc 8, 16, 32 dma source addres s register_1 sar_1 32 h'ffff 86d0 dmac 8, 16, 32 dma destination address r egister_1 dar_1 32 h'ffff86d4 (channel 1) 8, 16, 32 dma transfer coun t register_1 dmat cr_1 32 h'ffff86d8 8, 16, 32 dma channel control register_1 chcr_1 32 h'ffff86dc 8, 16, 32 dma source addres s register_2 sar_2 32 h'ffff 86e0 dmac 8, 16, 32 dma destination address r egister_2 dar_2 32 h'ffff86e4 (channel 2) 8, 16, 32 dma transfer coun t register_2 dmat cr_2 32 h'ffff86e8 8, 16, 32 dma channel control register_2 chcr_2 32 h'ffff86ec 8, 16, 32 dma source addres s register_3 sar_3 32 h'ffff 86f0 dmac 8, 16, 32 dma destination address r egister_3 dar_3 32 h'ffff86f4 (channel 3) 8, 16, 32 dma transfer coun t register_3 dmat cr_3 32 h'ffff86f8 8, 16, 32 dma channel control register_3 chcr_3 32 h'ffff86fc 8, 16, 32 25. list of registers rev.4.00 mar. 27, 2008 page 743 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states dtc enable register a dtea 8 h'ffff8700 dtc 8, 16, 32 reference dtc enable register b dteb 8 h'ffff8701 8 dtc enable register c dt ec 8 h'ffff8702 8, 16 dtc enable register d dted 8 h'ffff8703 8 b:3 w:3 l:6 ? ? h'ffff8704 to h'ffff8705 ? dtc control/status register dtcsr 16 h'ffff8706 8, 16, 32 dtc information base register dtbr 16 h'ffff8708 8, 16 ? ? h'ffff870a to h'ffff870f ? dtc enable register e dt ee 8 h'ffff8710 8, 16 ? ? ? h'ffff8711 ? dtc enable register g dt eg 8 h'ffff8712 8, 16 ? ? ? h'ffff8713 to h'ffff87ef ? serial control register x scrx 8 h'ffff87f0 i 2 c [option] 8 p reference b:3 ? ? ? h'ffff87f1 to h'ffff87f3 ? ? ad trigger select register adtsr 8 h'ffff87f4 a/d 8 p reference b:3 ? ? ? h'ffff87f5 to h'ffff87f7 ? ? high-current port control register ppcr 8 h'ffff87f8 port e 8 p reference b:3 ? ? ? h'ffff87f9 to h'ffff8807 ? ? 25. list of registers rev.4.00 mar. 27, 2008 page 744 of 882 rej09b0108-0400 register name abbreviation no. of bits addr ess module access size n o. of access states i 2 c bus control register iccr 8 h'ffff8808 i 2 c 8, 16 i 2 c bus status register icsr 8 h'ffff8809 [option] 8 ? ? ? h'ffff880a to h'ffff880d ? i 2 c bus data register icdr 8 h'ffff880e * 8, 16 p reference b:2 w:4 second slave address r egister sarx 8 h'ffff880e * 8, 16 i 2 c bus mode regist er icmr 8 h'ffff880f * 8 slave address regist er sar 8 h'ffff880f * 8 ? ? ? h'ffff8810 to h'ffff8a4f ? ? instruction register sdir 16 h'ffff8a50 8, 16, 32 status register sdsr 16 h'ffff8a52 8, 16 data register h sddrh 16 h'ffff8a54 h-udi (only in f- ztat version) 8, 16, 32 data register l sddrl 16 h'ffff8a56 8, 16 p reference b:2 w:2 l:4 ? ? h'ffff8a58 to h'ffffbfff ? note: * registers that can be read from/written to diffe r according to the setting of the ice bit in the iic bus control register 0. in ice=0, the registers read from/written to are the second slave address register 0 and the slave address r egister 0. in ice=1, they are the iic bus data register 0 and the iic bus mode register 0. 25. list of registers rev.4.00 mar. 27, 2008 page 745 of 882 rej09b0108-0400 25.2 register bit list addresses and bit names of each on-chip peripheral module are shown below. as for 16-bit or 32-bit registers, they are shown in two or four rows. register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module smr_0 c/ a chr pe o/ e stop mp cks1 cks0 brr_0 scr_0 tie rie te re mpie teie cke1 cke0 tdr_0 ssr_0 tdre rdrf orer fer per tend mpb mpbt sci (channel 0) rdr_0 sdcr_0 ? ? ? ? dir sinv ? smif smr_1 c/ a chr pe o/ e stop mp cks1 cks0 brr_1 scr_1 tie rie te re mpie teie cke1 cke0 tdr_1 ssr_1 tdre rdrf orer fer per tend mpb mpbt sci (channel 1) rdr_1 sdcr_1 ? ? ? ? dir sinv ? smif smr_2 c/ a chr pe o/ e stop mp cks1 cks0 brr_2 scr_2 tie rie te re mpie teie cke1 cke0 tdr_2 ssr_2 tdre rdrf orer fer per tend mpb mpbt sci (channel 2) rdr_2 sdcr_2 ? ? ? ? dir sinv ? smif smr_3 c/ a chr pe o/ e stop mp cks1 cks0 brr_3 scr_3 tie rie te re mpie teie cke1 cke0 tdr_3 ssr_3 tdre rdrf orer fer per tend mpb mpbt sci (channel 3) rdr_3 sdcr_3 ? ? ? ? dir sinv ? smif ? ? ? ? ? ? ? ? ? ? 25. list of registers rev.4.00 mar. 27, 2008 page 746 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module tcr_3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tcr_4 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_3 ? ? bfb bfa md3 md2 md1 md0 tmdr_4 ? ? bfb bfa md3 md2 md1 md0 mtu (channels 3, 4) tiorh_3 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_3 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tiorh_4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_4 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_3 ttge ? ? tciev tgied tgiec tgieb tgiea tier_4 ttge ? ? tciev tgied tgiec tgieb tgiea toer ? ? oe4d oe4c oe3d oe4b oe4a oe3b tocr ? psye ? ? ? ? olsn olsp tgcr ? bdc n p fb wf vf uf tcnt_3 tcnt_4 tcdr tddr tgra_3 tgrb_3 tgra_4 tgrb_4 tcnts tcbr 25. list of registers rev.4.00 mar. 27, 2008 page 747 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module tgrc_3 tgrd_3 tgrc_4 tgrd_4 mtu (channels 3, 4) tsr_3 tcfd ? ? tcfv tgfd tgfc tgfb tgfa tsr_4 tcfd ? ? tcfv tgfd tgfc tgfb tgfa tstr cst4 cst3 ? ? ? cst2 cst1 cst0 tsyr sync4 sync3 ? ? ? sync2 sync1 sync0 tcr_0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tmdr_0 ? ? bfb bfa md3 md2 md1 md0 mtu (channel 0) tiorh_0 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tiorl_0 iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 tier_0 ttge ? ? tciev tgied tgiec tgieb tgiea tsr_0 ? ? ? tcfv tgfd tgfc tgfb tgfa tcnt_0 tgra_0 tgrb_0 tgrc_0 tgrd_0 25. list of registers rev.4.00 mar. 27, 2008 page 748 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module tcr_1 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 t psc1 tpsc0 tmdr_1 ? ? ? ? md3 md2 md1 md0 tior_1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_1 ttge ? tcieu tciev ? ? tgieb tgiea tsr_1 tcfd ? tcfu tcfv ? ? tgfb tgfa tcnt_1 tgra_1 tgrb_1 mtu (channel 1) tcr_2 ? cclr1 cclr0 ckeg1 c keg0 tpsc2 t psc1 tpsc0 tmdr_2 ? ? ? ? md3 md2 md1 md0 tior_2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 tier_2 ttge ? tcieu tciev ? ? tgieb tgiea tsr_2 tcfd ? tcfu tcfv ? ? tgfb tgfa mtu (channel 2) tcnt_2 tgra_2 tgrb_2 ? ? ? ? ? ? ? ? ? ? 25. list of registers rev.4.00 mar. 27, 2008 page 749 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module irq0 irq0 irq0 irq0 irq1 irq1 irq1 irq1 ipra irq2 irq2 irq2 irq2 irq3 irq3 irq3 irq3 irq4 irq4 irq4 irq4 irq5 irq5 irq5 irq5 iprb irq6 irq6 irq6 irq6 irq7 irq7 irq7 irq7 dmac0 dmac0 dmac0 dmac0 dmac1 dmac1 dmac1 dmac1 iprc dmac2 dmac2 dmac2 dmac2 dmac3 dmac3 dmac3 dmac3 intc iprd mtu0 mtu0 mtu0 mtu0 mtu0 mtu0 mtu0 mtu0 mtu1 mtu1 mtu1 mtu1 mtu1 mtu1 mtu1 mtu1 mtu2 mtu2 mtu2 mtu2 mtu2 mtu2 mtu2 mtu2 ipre mtu3 mtu3 mtu3 mtu3 mtu3 mtu3 mtu3 mtu3 mtu4 mtu4 mtu4 mtu4 mtu4 mtu4 mtu4 mtu4 iprf sci0 sci0 sci0 sci0 sci1 sci1 sci1 sci1 a/d0, 1 a/d0, 1 a/d0, 1 a/d0, 1 dtc dtc dtc dtc iprg cmt0 cmt0 cmt0 cmt0 cmt1 cmt1 cmt1 cmt1 wdt wdt wdt wdt i/o(mtu) i/o(mtu) i/o(mtu) i/o(mtu) iprh ? ? ? ? ? ? ? ? nmil ? ? ? ? ? ? nmie icr1 irq0s irq1s irq2s irq3s irq4s irq5s irq6s irq7s ? ? ? ? ? ? ? ? isr irq0f irq1f irq2f irq3f irq4f irq5f irq6f irq7f sci2 sci2 sci2 sci2 sci3 sci3 sci3 sci3 ipri ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? iprj iic iic iic iic ? ? ? ? irq0es1 irq0es0 irq1es1 irq1es0 irq2es1 irq2es0 irq3es1 irq3es0 icr2 irq4es1 irq4es0 irq5es1 irq5es0 irq6es1 irq6es0 irq7es1 irq7es0 ? ? ? ? ? ? ? ? ? ? 25. list of registers rev.4.00 mar. 27, 2008 page 750 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module ? ? ? ? ? ? ? ? port a padrh pa23dr pa22dr pa21dr pa20dr pa 19dr pa18dr pa17dr pa16dr pa15dr pa14dr pa13dr pa12dr pa11dr pa10dr pa9dr pa8dr padrl pa7dr pa6dr pa5dr pa4dr pa3 dr pa2dr pa1dr pa0dr ? ? ? ? ? ? ? ? paiorh pa23ior pa22ior pa21ior pa20ior pa19ior pa18ior pa17ior pa16ior paiorl pa15ior pa14ior pa13ior pa12 ior pa11ior pa10ior pa9ior pa8ior pa7ior pa6ior pa5ior pa4ior pa3ior pa2ior pa1ior pa0ior ? pa23md ? pa22md ? pa21md ? pa20md pacrh pa19md1 pa19md0 pa18md1 pa18md0 ? pa17md pa16md1 pa16md0 ? pa15md ? pa14md ? pa13md ? pa12md pacrl1 ? pa11md ? pa10md pa9md1 pa9md0 pa8md1 pa8md0 pa7md1 pa7md0 pa6md1 pa6md0 pa5md1 pa5md0 ? pa4md pacrl2 ? pa3md pa2md1 pa2md0 ? pa1md ? pa0md ? ? ? ? ? ? pb9dr pb8dr port b pbdr pb7dr pb6dr pb5dr pb4dr pb3 dr pb2dr pb1dr pb0dr pc15dr pc14dr pc13dr pc12dr pc11dr pc10dr pc9dr pc8dr port c pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr ? ? ? ? ? ? pb9ior pb8 ior port b pbior pb7ior pb6 ior pb5ior pb4 ior pb3 ior pb2 ior pb1 ior pb0 ior pc15ior pc14 ior pc13ior pc12 ior pc11 ior pc10 ior pc9ior pc8 ior port c pcior pc7ior pc6 ior pc5ior pc4 ior pc3 ior pc2 ior pc1 ior pc0 ior ? ? ? ? pb3md2 pb2md2 ? ? port b pbcr1 ? ? ? ? pb9md1 pb9md0 pb8md1 pb8md0 pb7md1 pb7md0 pb6md1 pb6md0 pb5md1 pb5md0 pb4md1 pb4md0 pbcr2 pb3md1 pb3md0 pb2md1 pb2md0 ? pb1md ? pb0md pccr pc15md pc14md pc13md pc12md pc11md pc10md pc9md pc8md port c pc7md pc6md pc5md pc4md pc3md pc2md pc1md pc0md 25. list of registers rev.4.00 mar. 27, 2008 page 751 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module pd31dr pd30dr pd29dr pd28dr pd27dr pd26dr pd25dr pd24dr port d pddrh pd23dr pd22dr pd21dr pd20dr pd19dr pd18dr pd17dr pd16dr pd15dr pd14dr pd13dr pd12dr pd11dr pd10dr pd9dr pd8dr pddrl pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr pd31ior pd30ior pd29ior pd28ior pd27ior pd26 ior pd25ior pd24ior pdiorh pd23ior pd22ior pd21ior pd20ior pd19ior pd18 ior pd17ior pd16ior pd15ior pd14ior pd13ior pd12ior pd11ior pd10 ior pd9ior pd8ior pdiorl pd7ior pd6ior pd5ior pd4ior pd3ior pd2 ior pd1ior pd0ior pd31md1 pd31md0 pd30md1 pd30 md0 pd29md1 pd29md0 pd28md1 pd28md0 pdcrh1 pd27md1 pd27md0 pd26md1 pd26 md0 pd25md1 pd25md0 pd24md1 pd24md0 pd23md1 pd23md0 pd22md1 pd22md0 pd21md1 pd21md0 pd20md1 pd20md0 pdcrh2 pd19md1 pd19md0 pd18md1 pd18md0 pd17md1 pd17md0 pd16md1 pd16md0 pd15md0 pd14md0 pd13md0 pd12md0 pd11md0 pd10md0 pd9md0 pd8md0 pdcrl1 pd7md pd6md pd5md pd4md pd 3md pd2md pd1md pd0md pd15md1 pd14md1 pd13md1 pd12md1 pd11md1 pd10md1 pd9md1 pd8md1 pdcrl2 ? ? ? ? ? ? ? ? pe15dr pe14dr pe13dr pe12dr pe11dr pe10dr pe9dr pe8dr pedrl pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr port e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr port f pe15ior pe14ior pe13ior pe12ior pe11ior pe10ior pe9ior pe8ior peiorl pe7ior pe6ior pe5ior pe4ior pe3ior pe2ior pe1ior pe0ior port e pe15md1 pe15md0 pe14md1 pe14md0 pe13md1 pe13md0 pe12md1 pe12md0 pecrl1 pe11md1 pe11md0 pe10md1 pe10md0 pe9md1 pe9md0 pe8md1 pe8md0 pe7md1 pe7md0 pe6md1 pe6md0 pe5md1 pe5md0 pe4md1 pe4md0 pecrl2 pe3md1 pe3md0 pe2md1 pe2md0 pe1md1 pe1md0 pe0md1 pe0md0 ? ? ? ? ? ? ? ? ? ? poe3f poe2f poe1f poe0f ? ? ? pie mtu icsr1 poe3m1 poe3m0 poe2m1 poe2m0 poe1m1 poe1m0 poe0m1 poe0m0 osf ? ? ? ? ? oce oie ocsr ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 25. list of registers rev.4.00 mar. 27, 2008 page 752 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module ? ? ? ? ? ? ? ? cmstr ? ? ? ? ? ? str1 str0 ? ? ? ? ? ? ? ? cmcsr_0 cmf cmie ? ? ? ? cks1 cks0 cmt cmcnt_0 cmcor_0 ? ? ? ? ? ? ? ? cmcsr_1 cmf cmie ? ? ? ? cks1 cks0 cmcnt_1 cmcor_1 ? ? ? ? ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 addr0 ad1 ad0 ? ? ? ? ? ? a/d ad9 ad8 ad7 ad6 ad 5 ad4 ad3 ad2 addr1 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad 5 ad4 ad3 ad2 addr2 ad1 ad0 ? ? ? ? ? ? addr3 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad 5 ad4 ad3 ad2 addr4 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad 5 ad4 ad3 ad2 addr5 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad 5 ad4 ad3 ad2 addr6 ad1 ad0 ? ? ? ? ? ? ad9 ad8 ad7 ad6 ad 5 ad4 ad3 ad2 addr7 ad1 ad0 ? ? ? ? ? ? adcsr_0 adf adie ? adm ? ? ch1 ch0 adcsr_1 adf adie ? adm ? ? ch1 ch0 25. list of registers rev.4.00 mar. 27, 2008 page 753 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module adcr_0 trge cks1 cks0 adst adcs ? ? ? a/d adcr_1 trge cks1 cks0 adst adcs ? ? ? ? ? ? ? ? ? ? ? ? ? flmcr1 fwe swe esu psu ev pv e p flash flmcr2 fler ? ? ? ? ? ? ? ebr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ebr2 ? ? ? ? eb11 eb10 eb9 eb8 (only in f-ztat version) ? ? ? ? ? ? ? ? ? ? uba31 uba30 uba29 uba28 uba27 uba26 uba25 uba24 ubarh uba23 uba22 uba21 uba20 uba19 uba18 uba17 uba16 uba15 uba14 uba13 uba12 uba11 uba10 uba9 uba8 ubarl uba7 uba6 uba5 uba4 uba3 uba2 uba1 uba0 ubm31 ubm30 ubm29 ubm28 ubm27 ubm26 ubm25 ubm24 ubamrh ubm23 ubm22 ubm21 ubm20 ubm19 ubm18 ubm17 ubm16 ubamrl ubm15 ubm14 ubm13 ub m12 ubm11 ubm10 ubm9 ubm8 ubc ubm7 ubm6 ubm5 ubm4 ubm3 ubm2 ubm1 ubm0 ? ? ? ? ? ? ? ? ubbr cp1 cp0 id1 id0 rw1 rw0 sz1 sz0 ? ? ? ? ? ? ? ? ubcr ? ? ? ? ? ? ? ubid ? ? ? ? ? ? ? ? ? ? tcsr * 1 ovf wt/it tme ? ? cks2 cks1 cks0 tcnt * 1 tcnt * 2 rstcsr * 1 rstcsr * 2 wovf rste rsts ? ? ? ? ? wdt * 1: write * 2: read ? ? ? ? ? ? ? ? ? ? sbycr ssby hi-z ? ? ? ? irqeh irqel power-down syscr ? ? ? ? ? ? audsrst rame modes ? ? ? ? mstp27 mstp26 mstp25 mstp24 mstcr1 ? ? mstp21 ? mstp19 mstp18 mstp17 mstp16 mstcr2 ? ? mstp13 mstp12 ? ? ? ? ? ? mstp5 mstp4 mstp3 mstp2 ? mstp0 25. list of registers rev.4.00 mar. 27, 2008 page 754 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module ? ? ? ? ? ? ? ? ? ? ? ? mturwe ? ? ? ? ? bsc bcr1 a3lg a2lg a1lg a0lg a3sz a2sz a1sz a0sz iw31 iw30 iw21 iw20 iw11 iw10 iw01 iw00 bcr2 cw3 cw2 cw1 cw0 sw3 sw2 sw1 sw0 w33 w32 w31 w30 w23 w22 w21 w20 wcr1 w13 w12 w11 w10 w03 w02 w01 w00 ? ? ? ? ? ? ? ? wcr2 ? ? ? ? dsw3 dsw2 dsw1 dsw0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ramer ? ? ? ? rams ram2 ram1 ram0 flash (only in f-ztat version) ? ? ? ? ? ? ? ? ? ? dmaor ? ? ? ? ? ? pr1 pr0 dmac ? ? ? ? ? ae nmif dme for all channels sar_0 dmac (channel 0) dar_0 dmatcr_0 ? ? ? ? ? ? ? ? chcr_0 ? ? ? ? ? ? ? ? ? ? ? ? ? rl am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ds tm ts1 ts0 ie te de 25. list of registers rev.4.00 mar. 27, 2008 page 755 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module sar_1 dmac (channel 1) dar_1 dmatcr_1 ? ? ? ? ? ? ? ? chcr_1 ? ? ? ? ? ? ? ? ? ? ? ? ? rl am al dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ds tm ts1 ts0 ie te de sar_2 dmac (channel 2) dar_2 dmatcr_2 ? ? ? ? ? ? ? ? chcr_2 ? ? ? ? ? ? ? ? ? ? ? ? ro ? ? ? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ? tm ts1 ts0 ie te de 25. list of registers rev.4.00 mar. 27, 2008 page 756 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module sar_3 dmac (channel 3) dar_3 dmatcr_3 ? ? ? ? ? ? ? ? chcr_3 ? ? ? ? ? ? ? ? ? ? ? di ? ? ? ? dm1 dm0 sm1 sm0 rs3 rs2 rs1 rs0 ? ? tm ts1 ts0 ie te de ? ? ? ? ? ? ? ? ? ? dtea dtea7 dtea6 dtea5 dtea4 dtea3 dtea2 dtea1 dtea0 dtc dteb dteb7 dteb6 dteb5 dteb4 dteb3 dteb2 dteb1 dteb0 dtec dtec7 dtec6 dtec5 dtec4 dtec3 dtec2 dtec1 dtec0 dted dted7 dted6 dted5 dted4 dted3 dted2 dted1 dted0 ? ? ? ? ? nmif ae swdte dtcsr dtvec7 dtvec6 dtvec5 dtvec4 dtvec3 dtvec 2 dtvec1 dtvec0 dtbr dtee ? ? dtee5 ? dtee3 dtee2 dtee1 dtee0 dteg dteg7 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? scrx ? ? iicx iice hnds ? icdrf stopim i 2 c [option] ? ? ? ? ? ? ? ? ? ? adtsr ? ? ? ? trg1s1 trg1s0 tr g0s1 trg0s0 a/d ? ? ? ? ? ? ? ? ? ? ppcr ? ? ? ? ? ? ? mzize port e ? ? ? ? ? ? ? ? ? ? 25. list of registers rev.4.00 mar. 27, 2008 page 757 of 882 rej09b0108-0400 register abbreviation bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 module iccr ice ieic mst tr s acke bbsy iric scp icsr estp stop irtr aasx al aas adz ackb icdr icdr7 icdr6 icdr5 icdr4 icdr3 icdr2 icdr1 icdr0 sarx svarx6 svarx5 svar x4 svarx3 svarx2 svarx1 svarx0 fsx icmr mls wait cks2 c ks1 cks0 bc2 bc1 bc0 sar sva6 sva5 sva4 sva3 sva2 sva1 sva0 fs i 2 c [option] ? ? ? ? ? ? ? ? ? ? sdir ts3 ts2 ts1 ts0 ? ? ? ? ? ? ? ? ? ? ? ? sdsr ? ? ? ? ? ? ? ? h-udi (only in f-ztat version) ? ? ? ? ? ? ? sdtrf sddrh sddrl 25. list of registers rev.4.00 mar. 27, 2008 page 758 of 882 rej09b0108-0400 25.3 register states in each operating mode register abbreviation power-on reset manual reset software standby module standby sleep module smr_0 initialized retained initialized initialized retained brr_0 initialized retained initialized initialized retained scr_0 initialized retained initialized initialized retained tdr_0 initialized retained initialized initialized retained ssr_0 initialized retained initialized initialized retained rdr_0 initialized retained initialized initialized retained sdcr_0 initialized retained initialized initialized retained sci (channel 0) smr_1 initialized retained initialized initialized retained brr_1 initialized retained initialized initialized retained scr_1 initialized retained initialized initialized retained tdr_1 initialized retained initialized initialized retained ssr_1 initialized retained initialized initialized retained rdr_1 initialized retained initialized initialized retained sdcr_1 initialized retained initialized initialized retained sci (channel 1) smr_2 initialized retained initialized initialized retained brr_2 initialized retained initialized initialized retained scr_2 initialized retained initialized initialized retained tdr_2 initialized retained initialized initialized retained ssr_2 initialized retained initialized initialized retained rdr_2 initialized retained initialized initialized retained sdcr_2 initialized retained initialized initialized retained sci (channel 2) smr_3 initialized retained initialized initialized retained brr_3 initialized retained initialized initialized retained scr_3 initialized retained initialized initialized retained tdr_3 initialized retained initialized initialized retained sci (channel 3) ssr_3 initialized retained initialized initialized retained rdr_3 initialized retained initialized initialized retained sdcr_3 initialized retained initialized initialized retained 25. list of registers rev.4.00 mar. 27, 2008 page 759 of 882 rej09b0108-0400 register abbreviation power-on reset manual reset software standby module standby sleep module tcr_3 initialized retained initialized initialized retained tcr_4 initialized retained initialized initialized retained tmdr_3 initialized retained initialized initialized retained tmdr_4 initialized retained initialized initialized retained tiorh_3 initialized retained initialized initialized retained tiorl_3 initialized retained initialized initialized retained mtu (channels 3, 4) tiorh_4 initialized retained initialized initialized retained tiorl_4 initialized retained initialized initialized retained tier_3 initialized retained initialized initialized retained tier_4 initialized retained initialized initialized retained toer initialized retained initialized initialized retained tocr initialized retained initialized initialized retained tgcr initialized retained initialized initialized retained tcnt_3 initialized retained initialized initialized retained tcnt_4 initialized retained initialized initialized retained tcdr initialized retained initialized initialized retained tddr initialized retained initialized initialized retained tgra_3 initialized retained initialized initialized retained tgrb_3 initialized retained initialized initialized retained tgra_4 initialized retained initialized initialized retained tgrb_4 initialized retained initialized initialized retained tcnts initialized retained initialized initialized retained tcbr initialized retained initialized initialized retained tgrc_3 initialized retained initialized initialized retained tgrd_3 initialized retained initialized initialized retained tgrc_4 initialized retained initialized initialized retained tgrd_4 initialized retained initialized initialized retained tsr_3 initialized retained initialized initialized retained tsr_4 initialized retained initialized initialized retained tstr initialized retained initialized initialized retained tsyr initialized retained initialized initialized retained 25. list of registers rev.4.00 mar. 27, 2008 page 760 of 882 rej09b0108-0400 register abbreviation power-on reset manual reset software standby module standby sleep module tcr_0 initialized retained initialized initialized retained tmdr_0 initialized retained initialized initialized retained tiorh_0 initialized retained initialized initialized retained tiorl_0 initialized retained initialized initialized retained tier_0 initialized retained initialized initialized retained tsr_0 initialized retained initialized initialized retained tcnt_0 initialized retained initialized initialized retained tgra_0 initialized retained initialized initialized retained tgrb_0 initialized retained initialized initialized retained tgrc_0 initialized retained initialized initialized retained tgrd_0 initialized retained initialized initialized retained mtu (channel 0) tcr_1 initialized retained initialized initialized retained tmdr_1 initialized retained initialized initialized retained tior_1 initialized retained initialized initialized retained tier_1 initialized retained initialized initialized retained tsr_1 initialized retained initialized initialized retained mtu (channel 1) tcnt_1 initialized retained initialized initialized retained tgra_1 initialized retained initialized initialized retained tgrb_1 initialized retained initialized initialized retained tcr_2 initialized retained initialized initialized retained mtu tmdr_2 initialized retained initialized initialized retained (channel 2) tior_2 initialized retained initialized initialized retained tier_2 initialized retained initialized initialized retained tsr_2 initialized retained initialized initialized retained tcnt_2 initialized retained initialized initialized retained tgra_2 initialized retained initialized initialized retained tgrb_2 initialized retained initialized initialized retained 25. list of registers rev.4.00 mar. 27, 2008 page 761 of 882 rej09b0108-0400 register abbreviation power-on reset manual reset software standby module standby sleep module ipra initialized initialized retained ? retained iprb initialized initialized retained ? retained iprc initialized initialized retained ? retained intc iprd initialized initialized retained ? retained ipre initialized initialized retained ? retained iprf initialized initialized retained ? retained iprg initialized initialized retained ? retained iprh initialized initialized retained ? retained icr1 initialized initialized retained ? retained isr initialized initialized retained ? retained ipri initialized initialized retained ? retained iprj initialized initialized retained ? retained icr2 initialized initialized retained ? retained padrh initialized retained retained ? retained padrl initialized retained retained ? retained paiorh initialized retained retained ? retained port a paiorl initialized retained retained ? retained pacrh initialized retained retained ? retained pacrl1 initialized retained retained ? retained pacrl2 initialized retained retained ? retained pbdr initialized retained retained ? retained port b pcdr initialized retained retained ? retained port c pbior initialized retained retained ? retained port b pcior initialized retained retained ? retained port c pbcr1 initialized retained retained ? retained pbcr2 initialized retained retained ? retained port b pccr initialized retained retained ? retained port c 25. list of registers rev.4.00 mar. 27, 2008 page 762 of 882 rej09b0108-0400 register abbreviation power-on reset manual reset software standby module standby sleep module pddrh initialized retained retained ? retained pddrl initialized retained retained ? retained pdiorh initialized retained retained ? retained port d pdiorl initialized retained retained ? retained pdcrh1 initialized retained retained ? retained pdcrh2 initialized retained retained ? retained pdcrl1 initialized retained retained ? retained pdcrl2 initialized retained retained ? retained pedrl initialized retained retained ? retained port e pfdr retained retained retained ? retained port f peiorl initialized retained retained ? retained port e pecrl1 initialized retained retained ? retained pecrl2 initialized retained retained ? retained icsr1 initialized retained retained retained retained ocsr initialized retained retained retained retained poe cmstr initialized retained initialized initialized retained cmcsr_0 initialized retained initialized initialized retained cmcnt_0 initialized retained initialized initialized retained cmcor_0 initialized retained initialized initialized retained cmcsr_1 initialized retained initialized initialized retained cmcnt_1 initialized retained initialized initialized retained cmt cmcor_1 initialized retained initialized initialized retained addr0 initialized retained initialized initialized retained a/d addr1 initialized retained initialized initialized retained addr2 initialized retained initialized initialized retained addr3 initialized retained initialized initialized retained addr4 initialized retained initialized initialized retained addr5 initialized retained initialized initialized retained addr6 initialized retained initialized initialized retained addr7 initialized retained initialized initialized retained adcsr_0 initialized retained initialized initialized retained 25. list of registers rev.4.00 mar. 27, 2008 page 763 of 882 rej09b0108-0400 register abbreviation power-on reset manual reset software standby module standby sleep module adcsr_1 initialized retained init ialized initialized retained a/d adcr_0 initialized retained initialized initialized retained adcr_1 initialized retained initialized initialized retained flmcr1 initialized retained initialized initialized retained flmcr2 initialized retained initialized initialized retained ebr1 initialized retained initialized initialized retained ebr2 initialized retained initialized initialized retained flash (only in f-ztat version) ubarh initialized retained retained initialized retained ubarl initialized retained retained initialized retained ubamrh initialized retained retained initialized retained ubamrl initialized retained retained initialized retained ubbr initialized retained retained initialized retained ubcr initialized retained retained initialized retained ubc tcsr initialized retained * 1 retained ? retained tcnt initialized retained * 1 retained ? retained rstcsr initialized * 2 retained initialized ? retained wdt sbycr initialized retained * 1 retained ? retained power-down modes syscr initialized retained retained ? retained mstcr1 initialized retained retained ? retained mstcr2 initialized retained retained ? retained bcr1 initialized retained retained ? retained bsc bcr2 initialized retained retained ? retained wcr1 initialized retained retained ? retained wcr2 initialized retained retained ? retained ramer initialized retained retained ? retained flash (only in f-ztat version) dmaor initialized retained initialized initialized retained dmac (for all channels) sar_0 initialized retained initialized initialized retained dmac dar_0 initialized retained initialized initialized retained (channel 0) dmatcr_0 initialized retained initialized initialized retained chcr_0 initialized retained initialized initialized retained 25. list of registers rev.4.00 mar. 27, 2008 page 764 of 882 rej09b0108-0400 register abbreviation power-on reset manual reset software standby module standby sleep module sar_1 initialized retained initialized initialized retained dmac dar_1 initialized retained initialized initialized retained (channel 1) dmatcr_1 initialized retained initialized initialized retained chcr_1 initialized retained initialized initialized retained sar_2 initialized retained initialized initialized retained dmac dar_2 initialized retained initialized initialized retained (channel 2) dmatcr_2 initialized retained initialized initialized retained chcr_2 initialized retained initialized initialized retained sar_3 initialized retained initialized initialized retained dmac dar_3 initialized retained initialized initialized retained (channel 3) dmatcr_3 initialized retained initialized initialized retained chcr_3 initialized retained initialized initialized retained dtea initialized retained initialized initialized retained dteb initialized retained initialized initialized retained dtec initialized retained initialized initialized retained dted initialized retained initialized initialized retained dtcsr initialized retained initialized initialized retained dtbr retained retained retained retained retained dtc dtee initialized retained initialized initialized retained dteg initialized retained initialized initialized retained scrx initialized retained retained retained retained i 2 c [option] adtsr initialized retained retained retained retained a/d ppcr initialized retained retained ? retained port e iccr initialized retained retained retained retained icsr initialized retained retained retained retained icdr initialized retained retained retained retained sarx initialized retained retained retained retained icmr initialized retained retained retained retained sar initialized retained retained retained retained i 2 c [option] sdir initialized retained retained retained retained sdsr initialized retained retained retained retained sddrh retained retained retained retained retained h-udi (only in f-ztat version) sddrl retained retained retained retained retained 25. list of registers rev.4.00 mar. 27, 2008 page 765 of 882 rej09b0108-0400 notes: 1. initialized by internal manual reset due to wdt overflow. 2. not initialized by internal power-on reset due to wdt overflow. 25. list of registers rev.4.00 mar. 27, 2008 page 766 of 882 rej09b0108-0400 26. electrical characteristics rev.4.00 mar. 27, 2008 page 767 of 882 rej09b0108-0400 section 26 electrical characteristics 26.1 absolute maximum ratings table 26.1 shows the absolute maximum ratings. table 26.1 absolute maximum ratings item symbol rating unit power supply voltage v cc ?0.3 to +4.3 v all pins other than analog input pins vin ?0.3 to v cc +0.3 v input voltage analog input pins vin ?0.3 to av cc +0.3 v analog supply voltage av cc ?0.3 to +4.3 v analog reference voltage (only in sh7145) av ref ?0.3 to av cc +0.3 v analog input voltage v an ?0.3 to av cc +0.3 v regular specifications ?20 to +75 operating temperature (except programming or erasing flash memory) wide range specifications t opr ?40 to +85 c operating temperature (programming or erasing flash memory) t weopr ?20 to +75 c storage temperature t stg ?55 to +125 c [operating precautions] operating the lsi in excess of the absolute ma ximum ratings may result in permanent damage. 26. electrical characteristics rev.4.00 mar. 27, 2008 page 768 of 882 rej09b0108-0400 26.2 dc characteristics table 26.2 dc characteristics conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. typ. max. unit measurement conditions res , mres , nmi, fwp, md3 to md0, dbgmd v cc ? 0.5 ? v cc +0.3 v input high-level voltage (except schmitt trigger input voltage) extal v ih v cc ? 0.5 ? v cc +0.3 v a/d port 2.2 ? av cc +0.3 v other input pins 2.2 ? v cc +0.3 v res , mres , nmi, fwp, md3 to md0, extal, dbgmd ? 0.3 ? 0.5 v input low-level voltage (except schmitt trigger input voltage) other input pins v il ? 0.3 ? 0.8 v v t+ (v ih ) v cc ? 0.5 ? ? v v t? (v il ) ? ? 0.5 v schmitt trigger input voltage irq7 to irq0 , poe3 to poe0 , tclka to tclkd, tioc0a to tioc0d, tioc1a, tioc1b, tioc2a, tioc2b, tioc3a to tioc3d, tioc4a to tioc4d, sck3 to sck0, rxd3 to rxd0 v t+ ?v t? 0.2 ? ? v input leak current res , mres , nmi, fwp, md3 to md0, dbgmd | i in | ? ? 1.0 a a/d port ? ? 1.0 a other input pins ? ? 1.0 a three-state leak current (off state) port a, b, c, d, e, | i tsi | ? ? 1.0 a output high- level voltage all output pins v oh v cc ? 0.5 ? ? v i oh = ?200 a all output pins ? ? 0.4 v i ol = 1.6 ma output low- level voltage pe9, pe11 to pe15 v ol ? ? 0.8 v i ol = 15 ma 26. electrical characteristics rev.4.00 mar. 27, 2008 page 769 of 882 rej09b0108-0400 item symbol min. typ. max. unit measurement conditions res ? ? 20 pf nmi ? ? 20 pf input capacitance all other input pins c in ? ? 20 pf vin = 0 v f = 1 mhz ta = 25 c clock 1:1 ? 150 210 ma f = 40 mhz normal operation clock 1:1/2 ? 160 220 ma f = 50 mhz clock 1:1 ? 110 170 ma f = 40 mhz sleep clock 1:1/2 ? 120 180 ma f = 50 mhz ? 3 50 a t a 50 c standby ? ? 500 a 50 c < t a clock 1:1 ? 150 210 ma v cc = 3.3 v f = 40 mhz current consumption * 2 flash program ming clock 1:1/2 icc ? 160 220 ma v cc = 3.3 v f = 50 mhz during a/d conversion ? 2 5 ma waiting for a/d conversion ? ? 2 ma analog power supply current standby ai cc ? ? 5 a during a/d conversion ? ? 2 ma waiting for a/d conversion ? ? 2 ma reference power supply current standby ai ref ? ? 5 a ram standby voltage v ram 2.0 ? ? v v cc [operating precautions] 1. when the a/d converter is not used, do not leave the av cc , and av ss pins open. 2. the current consumptio n is measured when v ih min = v cc ? 0.5 v, v il = 0.5 v, with all output pins unloaded. 26. electrical characteristics rev.4.00 mar. 27, 2008 page 770 of 882 rej09b0108-0400 table 26.3 permitted output current values conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. typ. max. unit output low-level permissible current (per pin) i ol ? ? 2.0 * ma output low-level permissible current (total) i ol ? ? 80 ma output high-level permissible current (per pin) ?i oh ? ? 2.0 ma output high-level permissible current (total) ?i oh ? ? 25 ma [operating precautions] to assure lsi reliability, do not exceed the output values listed in this table. note: * i ol = 15ma (max) about the pins pe9, pe11 to pe 15. however, at least three pins are permitted to have simultaneously i ol 2.0 ma among these pins. 26. electrical characteristics rev.4.00 mar. 27, 2008 page 771 of 882 rej09b0108-0400 26.3 ac characteristics 26.3.1 test conditions for the ac characteristics input reference levels high level: v ih minimum value, low level: v il maximum value output reference levels high level: 2.0 v, low level: 0.8 v i ol i oh c l v ref v dut output lsi output pin cl is a total value that includes the capacitance of measurement equipment, and is set as follows: 30 pf: ck, cs7 to cs0 , breq , back , dack1, dack0, irqout , audck 50 pf: a21 to a0, d31 to d0, rd , wrxx , tdo 100 pf: audata3 to audata0, audsync 70 pf: port output pin other than the above and peripheral module output pins it is assumed that i ol = 1.6 ma, i oh = 200 a in the test conditions. figure 26.1 output load circuit 26. electrical characteristics rev.4.00 mar. 27, 2008 page 772 of 882 rej09b0108-0400 26.3.2 clock timing table 26.4 shows the clock timing. table 26.4 clock timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure operating frequency f op 4 50 mhz figure 26.2 clock cycle time t cyc 20 250 ns clock low-level pulse width t cl 1/2 t cyc ? 5 ? ns clock high-level pulse width t ch 1/2 t cyc ? 5 ? ns clock rise time t cr ? 5 ns clock fall time t cf ? 5 ns extal clock input frequency f ex 4 12.5 mhz figure 26.3 extal clock input cycle time t excyc 80 250 ns extal clock input low-level pulse width t exl 35 ? ns extal clock input high-level pulse width t exh 35 ? ns extal clock input rise time t exr ? 5 ns extal clock input fall time t exf ? 5 ns reset oscillation settling time t osc1 10 ? ms figure 26.4 standby return oscillation settling time t osc2 10 ? ms clock cycle time for peripheral modules t pcyc 25 500 ns 26. electrical characteristics rev.4.00 mar. 27, 2008 page 773 of 882 rej09b0108-0400 t cyc t ch t cf t cr v oh ck v oh 1/2v cc 1/2v cc v oh v ol v ol t cl figure 26.2 system clock timing t excyc t exh t exf t exr v ih extal v ih 1/2v cc 1/2v cc v ih v il v il t exl figure 26.3 extal clock input timing ck v cc v cc min t osc1 t osc2 res figure 26.4 oscillation settling time 26. electrical characteristics rev.4.00 mar. 27, 2008 page 774 of 882 rej09b0108-0400 26.3.3 control signal timing table 26.5 shows control signal timing. table 26.5 control signal timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure res rise time, fall time t resr , t resf ? 200 ns figure 26.5 res pulse width t resw 25 ? t cyc res setup time t ress 35 ? ns mres pulse width t mresw 20 ? t cyc mres setup time t mress 35 ? ns md3 to md0 setup time t mds 20 ? t cyc nmi rise time, fall time t nmir , t nmif ? 200 ns figure 26.6 nmi setup time t nmis 35 ? ns nmi hold time t nmih 35 ? ns irq7 to irq0 setup time * (edge detection) t irqes 19 ? ns irq7 to irq0 setup time * (level detection) t irqls 19 ? ns irq7 to irq0 hold time t irqeh 19 ? ns irqout output delay time t irqod ? 100 ns figure 26.7 bus request setup time t brqs 19 ? ns figure 26.8 bus acknowledge delay time 1 t backd1 ? 35 ns bus acknowledge delay time 2 t backd2 ? 35 ns bus three-state delay time t bzd ? 35 ns [operating precautions] * the res , mres, nmi and irq7 to irq0 signals are asynchronous inputs, but when the setup times shown here are observed, the signals are considered to have been changed at clock rise ( res , mres ) or fall (nmi and irq7 to irq0 ). if the setup times are not observed, the recognition of these signals may be delayed until the next clock rise or fall. 26. electrical characteristics rev.4.00 mar. 27, 2008 page 775 of 882 rej09b0108-0400 t ress t mds t resf t resr v oh v ih v ih v ih v il v il v il t ress t resw ck md3 to md0 res mres t mresw t mress t mress v ih v il v il figure 26.5 reset input timing v ih v ih v il v il t nmis t nmir t nmif t nmih v ih v ol v ol v il v il t irqes t irqeh t irqls ck nmi i rq ed g e irq level figure 26.6 interrupt signal input timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 776 of 882 rej09b0108-0400 t irqod v oh v ol t irqod ck irqout v oh figure 26.7 interrupt signal outp ut timing t brqs t backd1 t brqs t bzd t bzd hi-z hi-z v ol v ol v ol v oh v oh v oh v oh v ih t backd2 ck breq (input) back (output) rd , csn , wrxx a21 to a0, d31 to d0 figure 26.8 bus release timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 777 of 882 rej09b0108-0400 26.3.4 bus timing table 26.6 shows bus timing. table 26.6 bus timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure address delay time t ad ? 25 ns cs delay time 1 t csd1 ? 28 ns cs delay time 2 t csd2 ? 28 ns read strobe delay time 1 t rsd1 ? 25 ns read strobe delay time 2 t rsd2 ? 25 ns read data setup time t rds 15 ? ns read data hold time t rdh 0 ? ns write strobe delay time 1 t wsd1 ? 25 ns write strobe delay time 2 t wsd2 ? 25 ns write data delay time t wdd ? 30 ns write data hold time t wdh 0 ? ns figures 26.9, 26.10 wait setup time t wts 12 ? ns wait hold time t wth 3 ? ns figure 26.11 read data access time t acc * 5 t cyc (n + 2) ? 35 * 1 * 2 ? ns access time from read strobe t oe * 5 t cyc (n + 1.5) ? 33 * 1 ? ns address setup time (read) t asr 0 * 3 ? ns figures 26.9, 26.10 address setup time (write) t asw 0 * 3 ? ns address hold time (write) t wr 5 * 4 ? ns write data hold time t wrh 0 * 3 ? ns dack delay time t dackd ? 28 ns notes: 1. the letter n me ans the number of waits. 2. when cs assert time is extended, this value is equal to t cyc (n + 3) ? 35. 3. when cs assert time is extended, this value is equal to t cyc . 4. when cs assert time is extended, this value is equal to 5 + t cyc . 5. if access time is satisfied, there is no need that t rds is satisfied. 26. electrical characteristics rev.4.00 mar. 27, 2008 page 778 of 882 rej09b0108-0400 t 1 t ad v oh v ol t 2 t dackd t csd1 t rsd1 t oe t rsd2 t rds t acc t asw t rdh t wsd2 t wr t wsd1 t wrh t csd2 t wdh t dackd t wdd t asr note: t rdh is specified from the ne g ate timin g of a21 to a0, csn , or rd , whichever is first. ck dackn a21 to a0 csn rd (read) wrx (write) d31 to d0 (read) d31 to d0 (write) figure 26.9 basi c cycle (no waits) 26. electrical characteristics rev.4.00 mar. 27, 2008 page 779 of 882 rej09b0108-0400 t 1 t ad t w t 2 t csd1 v ol v oh t rsd1 t oe t rsd2 t rds t acc t asw t rdh t wsd2 t wr t wsd1 t csd2 t wdh t dackd t dackd t wrh t wdd t asr note: t rdh is specified from the ne g ate timin g of a21 to a0, csn , or rd , whichever is first. ck a21 to a0 csn rd (read) wrx (write) d31 to d0 (read) d31 to d0 (write) dackn figure 26.10 basic cycl e (one software wait) 26. electrical characteristics rev.4.00 mar. 27, 2008 page 780 of 882 rej09b0108-0400 t wth t wth t wts t wts ck a21 to a0 csn rd (read) d31 to d0 (read) d31 to d0 (write) wrx (write) wait t 1 t w t w t wo t 2 note: t rdh is specified from the ne g ate timin g of a21 to a0, csn , or rd , whichever is first. dackn figure 26.11 basic cycl e (two software waits + waits by wait signal) 26. electrical characteristics rev.4.00 mar. 27, 2008 page 781 of 882 rej09b0108-0400 26.3.5 direct memory access controller (dmac) timing table 26.7 shows direct me mory access controller timing. table 26.7 direct memory access controller timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure dreq0 , dreq1 setup time t drqs 10 ? ns figure 26.12 dreq0 , dreq1 hold time t drqh 1.5 t cyc ? 10 ? ns dreq0 , dreq1 pulse width t drqw 1.5 ? t cyc figure 26.13 drak0, drak1 output delay time t drakd ? 30 ns figure 26.14 ck dreq0 dreq1 level input dreq0 dreq1 ed g e input dreq0 dreq1 level cancel t drqs t drqs t drqs t drqh figure 26.12 dreq0 , dreq1 input timing (1) 26. electrical characteristics rev.4.00 mar. 27, 2008 page 782 of 882 rej09b0108-0400 ck dreq0 dreq1 ed g e input t drqw figure 26.13 dreq0 , dreq1 input timing (2) ck drak0 drak1 output t drakd t drakd figure 26.14 drak output delay time 26. electrical characteristics rev.4.00 mar. 27, 2008 page 783 of 882 rej09b0108-0400 26.3.6 multi-function timer pulse unit (mtu)timing table 26.8 shows multi-function timer pulse unit timing. table 26.8 multi-function timer pulse unit timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure output compare output delay time t tocd ? 100 ns figure 26.15 input capture input setup time t tics 19 ? ns timer input setup time t tcks 19 ? ns timer clock pulse width (single edge specified) t tckwh/l 1.5 ? t pcyc figure 26.16 timer clock pulse width (both edges specified) t tckwh/l 2.5 ? t pcyc timer clock pulse width (phase count mode) t tckwh/l 2.5 ? t pcyc ck output compare output input capture input t tocd t tics figure 26.15 mtu input/output timing ck tclka to tclkd t tcks t tcks t tckwh t tckwl figure 26.16 mtu clock input timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 784 of 882 rej09b0108-0400 26.3.7 i/o port timing table 26.9 shows i/o port timing. table 26.9 i/o port timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure port output data delay time t pwd ? 100 ns figure 26.17 port input hold time t prh 19 ? ns port input setup time t prs 19 ? ns [operating precautions] the port input signals are asynchronous. they are, however, considered to have been changed at ck clock fall with two-state intervals shown in figure 26.17. if the setup times shown here are not observed, recognition may be delayed until the clock fall two states after that timing. t prs t prh t pwd ck port (read) port (write) figure 26.17 i/o port input/output timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 785 of 882 rej09b0108-0400 26.3.8 watchdog timer (wdt)timing table 26.10 shows watchdog timer timing. table 26.10 watchdog timer timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure wdtovf delay time t wovd ? 100 ns figure 26.18 t wovd t wovd v oh v oh ck wdtovf figure 26.18 wdt timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 786 of 882 rej09b0108-0400 26.3.9 serial communication interface (sci) timing table 26.11 shows serial co mmunication interface timing. table 26.11 serial communi cation interface timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure input clock cycle (asynchronous) t scyc 4 ? t pcyc input clock cycle (clock sync) t scyc 6 ? t pcyc figure 26.19 input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr ? 1.5 t pcyc input clock fall time t sckf ? 1.5 t pcyc transmit data delay time t txd ? 100 ns received data setup time t rxs 100 ? ns received data hold time asynchronous t rxh 100 ? ns transmit data delay time t txd ? t pcyc + 43 ns received data setup time t rxs t pcyc + 25 ? ns received data hold time clock sync (when sck input) t rxh t pcyc + 25 ? ns transmit data delay time t txd ? 65 ns received data setup time t rxs 0.5 t pcyc + 50 ? ns received data hold time clock sync (when sck output) t rxh 1.5 t pcyc ? ns figure 26.20 26. electrical characteristics rev.4.00 mar. 27, 2008 page 787 of 882 rej09b0108-0400 [operating precautions] the inputs and outputs are asynchronous in asynchronous mode, but as shown in figure 26.20, the received data is considered to have been change d at ck clock rise (two -clock intervals). the transmit signals change with a reference of ck clock rise (two-clock intervals). t sckw v ih v ih v ih v ih v il v il v il sck0 to sck3 t sckr t sckf t scyc figure 26.19 sci input timing t scyc sck0 to sck3 (input/output) txd0 to txd3 (transmit data) rxd0 to rxd3 (received data) sci input/output timin g (clock synchronous mode) t txd t rxs t rxh v oh v oh t 1 ck txd0 to txd3 (transmit data) rxd0 to rxd3 (received data) sci input/output timin g (asynchronous mode) t n t txd t rxs t rxh figure 26.20 sci input/output timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 788 of 882 rej09b0108-0400 26.3.10 i 2 c bus interface timing table 26.12 shows i 2 c bus interface timing. table 26.12 i 2 c bus interface timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. typ. max. unit figure scl input cycle time t scl 12 t pcyc * 1 ? ? ns scl input high pulse width t sclh 3 t pcyc ? ? ns scl input low pulse width t scll 5 t pcyc ? ? ns scl and sda input rise time t sr ? ? 7.5 t pcyc * 2 ns scl and sda input fall time t sf ? ? 300 ns scl and sda input spike pulse removal time t sp ? ? 1 t pcyc ns sda input bus free time t buf 5 t pcyc ? ? ns start condition input hold time t stah 3 t pcyc ? ? ns retransmission start condition input setup time t stas 3 t pcyc ? ? ns halt condition input setup time t stos 3 t pcyc ? ? ns data input setup time t sdas 35 ? ? ns data input hold time t sdah 0 ? ? ns figure 26.21 scl and sda capacity load c b ? ? 400 pf notes: 1. t pcyc (ns) = 1/(p supplied to i 2 c module (mhz) ) 2. can be set to 17.5 t pcyc by selecting the clock to be used for the i 2 c module. for details, refer to section 14.5, usage notes. 26. electrical characteristics rev.4.00 mar. 27, 2008 page 789 of 882 rej09b0108-0400 scl0 v ih v il t stah t buf p * s * t sf t sr t scl t sdah t sclh t scll sda0 sr * t stas t sp t stos t sdas p * note: * s, p, and sr represent the followin g conditions s: start p: halt sr: retransmission start figure 26.21 i 2 c bus interface timing 26.3.11 port output enable (poe) timing table 26.13 shows port output enable (poe) timing. table 26.13 port output enable timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure poe input setup time t poes 100 ? ns figure 26.22 poe input pulse width t poew 1.5 ? tpcyc ck poe input t poes t poew figure 26.22 poe input/output timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 790 of 882 rej09b0108-0400 26.3.12 a/d converter timing table 26.14 shows a/d converter timing. table 26.14 a/d converter timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. typ. max. unit figure external trigger input start delay time t trgs 50 ? ? ns figure 26.23 ck adtrg input adcrn re g ister (adst = 1 set) 3?5 states t trgs v oh figure 26.23 external trigger input timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 791 of 882 rej09b0108-0400 26.3.13 h-udi timing table 26.15 shows h-udi timing. table 26.15 h-udi timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure tck clock cycle t tcyc 60 * 500 ns figure 26.24 tck clock high-level width t tckh 0.4 0.6 t tcyc tck clock low-level width t tckl 0.4 0.6 t tcyc trst pulse width t trsw 20 ? t tcyc figure 26.25 trst setup time t trss 30 ? ns tms setup time t tmss 15 ? ns figure 26.26 tms hold time t tmsh 10 ? ns tdi setup time t tdis 15 ? ns tdi hold time t tdih 10 ? ns tdo delay time t tdod ? 30 ns note: * the value must not be under 2 t cyc . t tckh t tcyc v ih tck v ih v il v il v ih t tckl figure 26.24 h-udi clock timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 792 of 882 rej09b0108-0400 t trss t trss v il v il v ih v il tck trst t trsw figure 26.25 h-udi trst timing tck tms tdi tdo t tmss t tmsh v il v ih v ih t tdis t tdih t tdod t tdod figure 26.26 h-udi input/output timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 793 of 882 rej09b0108-0400 26.3.14 aud timing table 26.16 shows aud timing. table 26.16 aud timing conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min. max. unit figure audrst pulse width (branch trace) t audrstw 20 ? t cyc figure 26.27 audrst pulse width (ram monitor) t audrstw 5 ? t rmcyc audmd setup time (branch trace) t audmds 20 ? t cyc audmd setup time (ram monitor) t audmds 5 ? t rmcyc branch trace clock cycle t btcyc 2 2 t cyc figure 26.28 branch trace clock duty t btckw 40 60 % branch trace data delay time t btdd ? 11 ns branch trace data hold time t btdh ? 10 ? ns branch trace sync delay time t btsd ? 10 ns branch trace sync hold time t btsh ? 10 ? ns ram monitor clock cycle t rmcyc 80 ? ns figure 26.29 ram monitor clock low pulse width t rmckw 35 ? ns ram monitor output data delay time t rmdd 7 t rmcyc ? 20 ns ram monitor output data hold time t rmdhd 5 ? ns ram monitor input data setup time t rmds 10 ? ns pe3/audata3, pe4/audata2 15 + t rmcyc ? t rmckw ? ns ram monitor input data hold time other audata pins t rmdh 15 ? ns ram monitor sync setup time t rmss 10 ? ns ram monitor sync hold time pa16/ audsync t rmsh 13 + t rmcyc ? t rmckw ? ns other audsync pins 13 ? ns load conditions: audck (output): cl = 30 pf audsync : cl = 100 pf audata3 to audata0: cl = 100 pf 26. electrical characteristics rev.4.00 mar. 27, 2008 page 794 of 882 rej09b0108-0400 t rmcyc t audrstw t audmds t cyc ck (branch trace) audck (input) (ram monitor) audrst audmd figure 26.27 aud reset timing audck (output) audata3 to audata0 (output) audsync (output) t btdd t btsd t btckw t btcyc t btdh t btsh figure 26.28 branch trace timing audck (input) audata3 to audata0 (output) audata3 to audata0 (input) audsync (input) t rmdd t rmds t rmss t rmdh t rmcyc t rmckw t rmdhd t rmsh figure 26.29 ram monitor timing 26. electrical characteristics rev.4.00 mar. 27, 2008 page 795 of 882 rej09b0108-0400 26.4 a/d converter characteristics table 26.17 shows a/d co nverter characteristics. table 26.17 a/d converter characteristics conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications), t a = ?40 c to +85 c (wide-range sp ecifications), when programming or erasing flash memory, t a = ?20 c to +75 c. item min. typ. max. unit resolution 10 10 10 bit a/d conversion time ? ? 6.7 * 1 /5.4 * 2 s analog input capacitance ? ? 20 pf permitted analog signal source impedance ? ? 1 k non-linear error (reference value) ? ? 3.0 * 3 * 4 * 5 / 5.0 * 6 lsb offset error (reference value) ? ? 3.0 * 3 * 4 * 5 / 5.0 * 6 lsb full-scale error (reference value) ? ? 3.0 * 3 * 4 * 5 / 5.0 * 6 lsb quantization error ? ? 0.5 lsb absolute error ? ? 4.0 * 3 * 4 * 5 / 6.0 * 6 lsb notes: 1. this is a value when (cks1, 0) = (1,1) and t pcyc = 50 ns. 2. this is a value when (cks1, 0) = (1,1) and t pcyc = 40 ns. 3. this is a value when (cks1, 0) = (1,1), t pcyc = 50 ns, and t a = ? 20 to + 75 c (regular specifications). 4. this is a value when (cks1, 0) = (1,1), t pcyc = 40 ns, and t a = ? 20 to + 75 c (regular specifications). 5. this is a value when (cks1, 0) = (1,1), t pcyc = 50 ns, and t a = ? 40 to + 85 c (wide-range specifications). 6. this is a value when (cks1, 0) = (1,1), t pcyc = 40 ns, and t a = ? 40 to + 85 c (wide-range specifications). 26. electrical characteristics rev.4.00 mar. 27, 2008 page 796 of 882 rej09b0108-0400 26.5 flash memory characteristics table 26.18 shows flash memory characteristics. table 26.18 flash memory characteristics conditions: v cc = pllv cc =3.3 v 0.3 v, av cc = 3.3 v 0.3 v, av cc = v cc 0.3 v, av ref = 3.0 v to av cc , v ss = pllv ss = av ss = 0 v, t a = ?20 c to +75 c (regular specifications* 6 ), t a = ?40 c to +85 c (wide-range specifications* 6 ), when programming or erasing flash memory, t a = ?20 c to +75 c. item symbol min typ max unit remarks programming time * 1, * 2, * 4 t p ? 10 200 ms/ 128 bytes erase time * 1, * 3, * 5 t e ? 100 1200 ms/block reprogramming count n wec 100 * 7 10000 * 8 ? times standard product n wec ? ? 100 times wide temperature- range product data retained time t drp 10 * 9 ? ? years programming wait time after swe bit setting * 1 t sswe 1 1 ? s wait time after psu bit setting * 1 t spsu 50 50 ? s t sp30 28 30 32 s programming time wait t sp200 198 200 202 s programming time wait wait time after p bit setting * 1 * 4 t sp10 8 10 12 s additional- programming time wait wait time after p bit clear * 1 t cp 5 5 ? s wait time after psu bit clear * 1 t cpsu 5 5 ? s wait time after pv bit setting * 1 t spv 4 4 ? s wait time after h'ff dummy write * 1 t spvr 2 2 ? s wait time after pv bit clear * 1 t cpv 2 2 ? s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum programming count * 1, * 4 n ? ? 1000 times 26. electrical characteristics rev.4.00 mar. 27, 2008 page 797 of 882 rej09b0108-0400 item symbol min typ max unit remarks erase wait time after swe bit setting * 1 t sswe 1 1 ? s wait time after esu bit setting * 1 t sesu 100 100 ? s wait time after e bit setting * 1 * 5 t se 10 10 100 ms erase time wait wait time after e bit clear * 1 t ce 10 10 ? s wait time after esu bit clear * 1 t cesu 10 10 ? s wait time after ev bit setting * 1 t sev 20 20 ? s wait time after h'ff dummy write * 1 t sevr 2 2 ? s wait time after ev bit clear * 1 t cev 4 4 ? s wait time after swe bit clear * 1 t cswe 100 100 ? s maximum erase count * 1 * 5 n 12 ? 120 times notes: 1. make each time setting in accordance with the program/program-verify algorithm or erase/erase- verify algorithm. 2. programming time per 128 bytes (shows the total period for which the p-bit in the flash memory control register (flmcr1) is set. it does not include the programming verification time.) 3. 1-block erase time (shows the total period for which the e-bit in flmcr1 is set. it does not include the erase verification time.) 4. to specify the maximum programming time value (t p (max)) in the 128-bytes programming algorithm, set the max. value (1000) fo r the maximum programming count (n). the wait time after p bit setting should be change d as follows according to the value of the programming counter (n). programming counter (n) = 1 to 6: t sp30 = 30 s programming counter (n) = 7 to 1000: t sp200 = 200 s [in additional programming] programming counter (n) = 1 to 6: t sp10 = 10 s 5. for the maximum erase time (t e (max)), the following relationship applies between the wait time after e bit setting (t se ) and the maximum erase count (n): t e (max) = wait time after e bit setting (t se ) x maximum erase count (n) to set the maximum erase time, the values of (t se ) and (n) should be set so as to satisfy the above formula. examples: when t se = 100 ms, n = 12 times when t se = 10 ms, n = 120 times 6. see appendix c, product code lineup for correspondence of the standard product, wide temperature-range product, and product model name. 7. all characteristics after rewriting are guaranteed up to this minimum rewriting times (therefore 1 to min. times). 8. reference value at 25 c (a rough rewriting target number to which a rewriting usually functions) 9. data retention characteristics when rewriting is executed within the specification values including minimum values. 26. electrical characteristics rev.4.00 mar. 27, 2008 page 798 of 882 rej09b0108-0400 a. pin states rev.4.00 mar. 27, 2008 page 799 of 882 rej09b0108-0400 appendix a pin states a. pin state pin initial states differ according to mcu oper ating modes. refer to section 17, pin function controller (pfc), for details. table a.1 pin states (sh7144) pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master- ship release ck o o o z o h * 1 o o o xtal o o o o o l o o l extal i i i i i i i i i clock pllcap i i i i i i i i i res i i i i i i i i i mres z z z z i z i i z wdtovf o * 2 o * 2 o * 2 o * 2 o o o o o breq z z z z i z i i i system control back z z z z o z o l l md0 to md3 i i i i i i i i i dbgmd i i i i i i i i i operation mode control fwp i i i i i i i i i interrupt nmi i i i i i i i i i irq0 to irq3 z z z z i z * 3 i i z * 3 irq4 to irq7 z z z z i z * 4 i i z * 4 a. pin states rev.4.00 mar. 27, 2008 page 800 of 882 rej09b0108-0400 pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master- ship release interrupt irqout z z z z o z * 6 (mzize in ppcr=0) h * 1 (mzize in ppcr=1) o o z * 6 (mzize in ppcr=0) h * 1 (mzize in ppcr=1) a0 to a17 o o z z o z o z z address bus a18 to a21 z z z z o z o z z data bus d0 to d15 z z z z i/o z i/o z z wait z z z z i z i z z cs0 , cs1 h h z z o z o z z cs2 , cs3 cs6, cs7 z z z z o z o z z rd h h z z o z o z z bus control wrh , wrl h h z z o z o z z dreq0 , dreq1 z z z z i z i i z drak0, drak1 z z z z o o * 1 o o o * 1 dmac dack0, dack1 z z z z o z (mzize in ppcr=0) o * 1 (mzize in ppcr=1) o o z (mzize in ppcr=0) o * 1 (mzize in ppcr=1) mtu tclka to tclkd z z z z i z i i z a. pin states rev.4.00 mar. 27, 2008 page 801 of 882 rej09b0108-0400 pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master- ship release tioc0a to tioc0d tioc1a, tioc1b tioc2a, tioc2b tioc3a, tioc3c z z z z i/o k * 1 i/o i/o k * 1 tioc3b, tioc3d mtu tioc4a to tioc4d z z z z i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) i/o i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) port control poe0 to poe3 z z z z i z i i z sci sck0 to sck2, sck3(pe6) sck3(pe9) z z z z i/o z i/o i/o z rxd0 to rxd2, rxd3(pe4) rxd3(pe11) z z z z i z i i z txd0 to txd2, txd3(pe5) z z z z o o * 1 o o o * 1 txd3 (pe12) z z z z o z * 6 (mzize in ppcr=0) o * 1 (mzize in ppcr=1) o o z * 6 (mzize in ppcr=0) o * 1 (mzize in ppcr=1) a. pin states rev.4.00 mar. 27, 2008 page 802 of 882 rej09b0108-0400 pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master-ship release an0 to an7 z z z z i z i i z a/d converter adtrg z z z z i z i i z scl0 z z z z i/o z i/o i/o z i 2 c sda0 z z z z i/o z i/o i/o z i/o port pa0 to pa15 pb0 to pb9 pc0 to pc15 pd0 to pd15 pe0 to pe8, pe10 z z z z i/o k * 1 i/o i/o k * 1 pe9, pe11 to pe15 z z z z i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) i/o i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) pf0 to pf7 z z z z i z i i z [legend] i: input o: output h: high-level output l: low-level output z: high-impedance k: input pins become high-impedance, and output pins retain their state. a. pin states rev.4.00 mar. 27, 2008 page 803 of 882 rej09b0108-0400 table a.2 pin states (sh7145) pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master- ship release ck o o o z o h * 1 o o o xtal o o o o o l o o l extal i i i i i i i i i clock pllcap i i i i i i i i i res i i i i i i i i i mres z z z z i z i i z wdtovf o * 2 o * 2 o * 2 o * 2 o o o o o breq z z z z i z i i i system control back z z z z o z o l l md0 to md3 i i i i i i i i i dbgmd i i i i i i i i i operation mode control fwp i i i i i i i i i nmi i i i i i i i i i irq0 to irq3 z z z z i z * 3 i i z * 3 irq4 to irq7 z z z z i z * 4 i i z * 4 irqout (pd30) z z z z o h * 1 o o h * 1 interrupt irqout (pe15) z z z z o z * 6 (mzize in ppcr=0) h * 1 (mzize in ppcr=1) o o z * 6 (mzize in ppcr=0) h * 1 (mzize in ppcr=1) a0 to a17 o o z z o z o z z address bus a18 to a21 z z z z o z o z z data bus d0 to d31 z z z z i/o z i/o z z a. pin states rev.4.00 mar. 27, 2008 page 804 of 882 rej09b0108-0400 pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master- ship release wait z z z z i z i z z cs0 , cs1 h h z z o z o z z cs2 , to cs7 z z z z o z o z z rd h h z z o z o z z wrh , wrl h h z z o z o z z bus control wrhh , wrhl z h z z o z o z z dreq0 , dreq1 z z z z i z i i z dmac drak0, drak1 z z z z o o * 1 o o o * 1 dack0 (pd26), dack1 (pd27) z z z z o o * 1 * 5 o o o * 1 * 5 dack0 (pe14), dack1 (pe15) z z z z o z (mzize in ppcr=0) o * 1 (mzize in ppcr=1) o o z (mzize in ppcr=0) o * 1 (mzize in ppcr=1) mtu tclka to tclkd z z z z i z i i z tioc0a to tioc0d z z z z i/o k * 1 i/o i/o k * 1 tioc1a, tioc1b tioc2a, tioc2b tioc3a, tioc3c a. pin states rev.4.00 mar. 27, 2008 page 805 of 882 rej09b0108-0400 pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master- ship release tioc3b, tioc3d mtu tioc4a to tioc4d z z z z i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) i/o i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) port control poe0 to poe3 z z z z i z i i z sck0 to sck2, sck3(pe6) sck3(pe9) z z z z i/o z i/o i/o z rxd0 to rxd2, rxd3(pe4) rxd3(pe11) z z z z i z i i z txd0 to txd2, txd3(pe5) z z z z o o * 1 o o o * 1 sci txd3 (pe12) z z z z o z * 6 (mzize in ppcr=0) o * 1 (mzize in ppcr=1) o o z * 6 (mzize in ppcr=0) o * 1 (mzize in ppcr=1) an0 to an7 z z z z i z i i z a/d converter adtrg z z z z i z i i z i 2 c scl0 z z z z i/o z i/o i/o z sda0 z z z z i/o z i/o i/o z a. pin states rev.4.00 mar. 27, 2008 page 806 of 882 rej09b0108-0400 pin function pin state reset state power-down state power-on expansion without rom type pin name 8 bits 16 bits expansion with rom single- chip manual software standby sleep bus master- ship release software standby in bus master- ship release i/o port pa0 to pa23 pb0 to pb9 pc0 to pc15 pd0 to pd31 pe0 to pe8, pe10 z z z z i/o k * 1 i/o i/o k * 1 pe9, pe11 to pe15 z z z z i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) i/o i/o z (mzize in ppcr=0) k * 1 (mzize in ppcr=1) pf0 to pf7 z z z z i z i i z [legend] i: input o: output h: high-level output l: low-level output z: high impedance k: input pins become high-impedance, and output pins retain their state. a. pin states rev.4.00 mar. 27, 2008 page 807 of 882 rej09b0108-0400 table a.3 pin states pin function pin state reset power-down type pin name power-on (dbgmd=l) power-on (dbgmd=h) manual test reset software standby sleep no connection h-udi tms z i i i i i prohibited trst z i i i i i prohibited tdi z i i i i i prohibited tdo z o/z o/z z o/z o/z o/z tck z i i i i i prohibited table a.4 pin states pin function pin state reset power-down type pin name power- on manual aud reset software standby sleep aud module standby no connection aud audrst z high-level input low-level input high-level input high-level input z prohibited audmd z i i i i z prohibited audata0 to audata3 z audmd = high: i/o audmd = low: o audmd = high: i audmd = low: h audmd = high: i/o audmd = low: o audmd = high: i/o audmd = low: o z prohibited audck z audmd = high: i audmd = low: o audmd = high: i audmd = low: h audmd = high: i audmd = low: o audmd = high: i audmd = low: o z prohibited audsync z audmd = high: i audmd = low: o audmd = high: i audmd = low: h audmd = high: i audmd = low: o audmd =high: i audmd = low: o z prohibited a. pin states rev.4.00 mar. 27, 2008 page 808 of 882 rej09b0108-0400 table a.5 pin states pin function pin state reset power-down type pin name power-on (dbgmd = l) power-on (dbgmd = h) manual software standby sleep operating mode control asebrkak z o o o o [legend] i: input o: output h: high-level output l: low-level output z: high impedance k: input pins become high-impedance, and output pins retain their state. notes: 1. when the hi-z bit in sbycr is set to 1, the output pins ent er their high-impedance state. 2. this pin operates as an input pin duri ng power-on reset period. this pin should be pulled up to prevent malfunction. in th is case, the resistance value must be 1m or higher. 3. this pin operates as an input pin when the irqel bit in sbycr is set to 0. 4. this pin operates as an input pin when the irqeh bit in sbycr is set to 0. 5. this pin becomes high-impedance in the emulator. 6. in the emulator, this pin operates as an in put pin when the hi-z bit in sbycr is set to 0. b. pin states of bus related signals rev.4.00 mar. 27, 2008 page 809 of 882 rej09b0108-0400 appendix b pin states of bus related signals b. pin states of bus related signals table b.1 pin states of bus related signals (1) on-chip peripheral module 16-bit space pin name on-chip rom space on-chip ram space 8-bit space upper byte lower byte word/longword cs0 to cs7 h h h h h h r h h h h h h rd w ? h h h h h r h h h h h h wrhh w ? h h h h h r h h h h h h wrhl w ? h h h h h r h h h h h h wrh w ? h h h h h r h h h h h h wrl w ? h h h h h a21 to a0 address address a ddress address a ddress address d31 to d24 hi-z hi-z hi-z hi-z hi-z hi-z d23 to d16 hi-z hi-z hi-z hi-z hi-z hi-z d15 to d8 hi-z hi-z hi-z hi-z hi-z hi-z d7 to d0 hi-z hi-z hi-z hi-z hi-z hi-z [legend] r: read w: write enabled: chip select signals corresponding to accessed areas = low the other chip select signals = high b. pin states of bus related signals rev.4.00 mar. 27, 2008 page 810 of 882 rej09b0108-0400 table b.1 pin states of bus related signals (2) normal external space 16-bit space pin name 8-bit space upper byte lower byte word/longword cs0 to cs7 enabled enabled enabled enabled r l l l l rd w h h h h r h h h h wrhh w h h h h r h h h h wrhl w h h h h r h h h h wrh w h l h l r h h h h wrl w l h l l a21 to a0 address a ddress address address d31 to d24 hi-z hi-z hi-z hi-z d23 to d16 hi-z hi-z hi-z hi-z d15 to d8 hi-z data hi-z data d7 to d0 data hi-z data data [legend] r: read w: write enabled: chip select signals corresponding to accessed areas = low the other chip select signals = high b. pin states of bus related signals rev.4.00 mar. 27, 2008 page 811 of 882 rej09b0108-0400 table b.1 pin states of bus related signals (3) normal external space 32-bit space pin name most significant byte second byte third byte least significant byte upper word lower word longword cs0 to cs7 enabled enabled enabled e nabled enabled enabled enabled r l l l l l l l rd w h h h h h h h r h h h h h h h wrhh w l h h h l h l r h h h h h h h wrhl w h l h h l h l r h h h h h h h wrh w h h l h h l l r h h h h h h h wrl w h h h l h l l a21 to a0 address address addres s address address address address d31 to d24 data hi-z hi-z hi-z data hi-z data d23 to d16 hi-z data hi-z hi-z data hi-z data d15 to d8 hi-z hi-z data hi-z hi-z data data d7 to d0 hi-z hi-z hi-z data hi-z data data [legend] r: read w: write enabled: chip select signals corresponding to accessed areas = low the other chip select signals = high c. product code lineup rev.4.00 mar. 27, 2008 page 812 of 882 rej09b0108-0400 appendix c product code lineup product type part no. package (package code) standard product hd64f7144f50 flash memory version wide temperature range product hd64f7144fw50 standard product hd6437144f50 wide temperature range product hd6437144fw50 i 2 c bus interface function product hd6437144wf50 masked rom version i 2 c bus interface function/wide temperature range product hd6437144wfw50 standard product hd6417144f50 sh7144 rom less version wide temperature range product hd6417144fw50 qfp-112 (fp-112b) sh7145 standard product hd64f7145f50 lqfp-144 (fp-144f) flash memory version wide temperature range product hd64f7145fw50 standard product hd6437145f50 wide temperature range product hd6437145fw50 i 2 c bus interface function product hd6437145wf50 masked rom version i 2 c bus interface function/wide temperature range product hd6437145wfw50 rom less version standard product hd6417145f50 wide temperature range product hd6417145fw50 d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 813 of 882 rej09b0108-0400 appendix d i/o port block diagrams pan/rxdm q panmd q panior qd r pandr res padrl.wr padrl.rd rxdm (sci) pfc sbycr software standby peripheral data bus c q hi-z res: reset si g nal padrl.rd: port a data re g ister l read si g nal padrl.wr: port a data re g ister l write si g nal figure d.1 pan/rxdm symbol in figure d.1 available products sh7144 sh7145 pins pan rxdm f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa0/rxd0 pa0 rxd0 (sci) pa3/rxd1 pa3 rxd1 (sci) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 814 of 882 rej09b0108-0400 pan/txdm q panmd q panior qd r pandr res padrl.wr padrl.rd txdm (sci) pfc sbycr software standby peripheral data bus c q hi-z res: reset si g nal padrl.rd: port a data re g ister l read si g nal padrl.wr: port a data re g ister l write si g nal figure d.2 pan/txdm symbol in figure d.2 available products sh7144 sh7145 pins pan txdm f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa1/txd0 pa1 txd0 (sci) pa4/txd1 pa4 txd1 (sci) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 815 of 882 rej09b0108-0400 pan/sckm/ dreqm / irqm q panmd0 q panmd1 q panior qd r pa n d r res padrl.wr padrl.rd sckm (sci) sckm (sci) dreqm (dmac) irqm (intc) pfc sbycr software standby peripheral data bus c q irqel res: reset si g nal padrl.rd: port a data re g ister l read si g nal padrl.wr: port a data re g ister l write si g nal q hi-z figure d.3 pan/sckm/ dreqm / irqm symbol in figure d. 3 available products sh7144 sh7145 pins pan sckm dreqm irqm f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa6/tclka/ cs2 pa6 tclka (mtu) cs2 (bsc) pa7/tclkb/ cs3 pa7 tclkb (mtu) cs3 (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 816 of 882 rej09b0108-0400 pan/tclkm/ csx q panmd0 q panmd1 q panior qd r pandr res padrl.wr padrl.rd csx (bsc) tclkm (mtu) pfc sbycr software standby bus release peripheral data bus c res: reset si g nal padrl.rd: port a data re g ister l read si g nal padrl.wr: port a data re g ister l write si g nal q hi-z figure d.4 pan/tclkm/ csx symbol in figure d. 4 available products sh7144 sh7145 pins pan tclkm csx f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa6/tclka/ cs2 pa6 tclka (mtu) cs2 (bsc) pa7/tclkb/ cs3 pa7 tclkb (mtu) cs3 (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 817 of 882 rej09b0108-0400 pan/tclkm/ irqx q panmd0 q panmd1 q panior qd r pandr res padrl.wr padrl.rd tclkm (mtu) pfc sbycr software standby peripheral data bus c res: reset si g nal padrl.rd: port a data re g ister l read si g nal padrl.wr: port a data re g ister l write si g nal irqx (intc) q hi-z q irqel figure d.5 pan/tclkm/ irqx symbol in figure d. 5 available products sh7144 sh7145 pins pan tclkm irqx f-ztat version masked rom version/ rom less version f-ztat version masked rom version/rom less version pa8/tclkc/ irq2 pa8 tclkc (mtu) irq2 (intc) pa9/tclkd/ irq3 pa9 tclkd (mtu) irq3 (intc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 818 of 882 rej09b0108-0400 pan/function 1 q panmd q panior qd r pa n d r res padrl.wr padrl.rd function 1 pfc sbycr software standby bus release peripheral data bus c res: reset si g nal padrl.rd: port a data re g ister l read si g nal padrl.wr: port a data re g ister l write si g nal q hi-z figure d.6 pan/function 1 symbol in figure d.6 available products sh7144 sh7145 pins pan function 1 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa10/ cs0 pa10 cs0 (bsc) pa11/ cs1 pa11 cs1 (bsc) pa12/ wrl pa12 wrl (bsc) pa13/ wrh pa13 wrh (bsc) pa14/ rd pa14 rd (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 819 of 882 rej09b0108-0400 pa15/ck q pa15md q pa15ior qd r pa15dr res padrl.wr padrl.rd ck (cpg) pfc sbycr software standby bus release peripheral data bus c res: reset si g nal padrl.rd: port a data re g ister l read si g nal padrl.wr: port a data re g ister l write si g nal q hi-z figure d.7 pa15/ck symbol in figure d.7 available products sh7144 sh7145 pins pa15 ck f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa15/ck pa15 ck (cpg) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 820 of 882 rej09b0108-0400 pa16/ audsync q pa16md0 q pa16md1 q pa16ior qd r pa16dr res padrh.wr padrh.rd audsync (aud) pfc sbycr software standby aud module standby peripheral data bus c res: reset si g nal padrh.rd: port a data re g ister h read si g nal padrh.wr: port a data re g ister h write si g nal q hi-z audmd audsync (aud) figure d.8 pa16/ audsync symbol in figure d.8 available products sh7144 sh7145 pins pa16 audsync f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa16/audsync pa16 audsync (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 821 of 882 rej09b0108-0400 pa 1 7 / wait q pa17md q pa17ior qd r pa17dr res padrh.wr padrh.rd wait (bsc) pfc sbycr bus release software standby peripheral data bus c res: reset si g nal padrh.rd: port a data re g ister h read si g nal padrh.wr: port a data re g ister h write si g nal q hi-z figure d.9 pa17/ wait symbol in figure d. 9 available products sh7144 sh7145 pins pa17 wait f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa17/ wait pa17 wait (bsc) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 822 of 882 rej09b0108-0400 pa18/ breq /drak0 q pa18md0 q pa18md1 q pa18ior qd r pa18dr res padrh.wr padrh.rd pfc sbycr software standby bus release peripheral data bus c res: reset si g nal padrh.rd: port a data re g ister h read si g nal padrh.wr: port a data re g ister h write si g nal breq (bsc) q hi-z drak0 (dmac) figure d.10 pa18/ breq /drak0 symbol in figure d. 10 available products sh7144 sh7145 pins pa18 breq drak0 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa18/ breq / drak0 pa18 breq (bsc) drak0 (dmac) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 823 of 882 rej09b0108-0400 pa19/ back /drak1 q pa19md0 q pa19md1 q pa19ior qd r pa19dr res padrh.wr padrh.rd pfc sbycr software standby bus release peripheral data bus c res: reset si g nal padrh.rd: port a data re g ister h read si g nal padrh.wr: port a data re g ister h write si g nal q hi-z drak1 (dmac) back (bsc) figure d.11 pa19/ back /drak1 symbol in figure d. 11 available products sh7144 sh7145 pins pa19 back drak1 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa19/ back / drak1 pa19 back (bsc) drak1 (dmac) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 824 of 882 rej09b0108-0400 pa n q panmd q panior qd r pandr res padrh.wr padrh.rd pfc sbycr software standby peripheral data bus c q hi-z res: reset si g nal padrh.rd: port a data re g ister h read si g nal padrh.wr: port a data re g ister h write si g nal figure d.12 pan symbol in figure d. 12 available products sh7144 sh7145 pins pan panmd f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa16 pa16 pa16md0 ? ? ? pa20 pa20 pa20md ? ? ? pa21 pa21 pa21md ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 825 of 882 rej09b0108-0400 pan/function 2 q panmd q panior qd r pa n d r res padrh.wr padrh.rd function 2 pfc sbycr software standby bus release peripheral data bus c res: reset si g nal padrh.rd: port a data re g ister h read si g nal padrh.wr: port a data re g ister h write si g nal q hi-z figure d.13 pan/function 2 symbol in figure d. 13 available products sh7144 sh7145 pins pan function 2 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pa20/ cs4 pa20 cs4 (bsc) ? ? ? pa21/ cs5 pa21 cs5 (bsc) ? ? ? pa22/ wrhl pa22 wrhl (bsc) ? ? pa23/ wrhh pa23 wrhh (bsc) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 826 of 882 rej09b0108-0400 pbn/am q pbnmd q pbnior qd r pbndr res pbdr.wr pbdr.rd am (bsc) pfc sbycr software standby bus release peripheral data bus c res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal q hi-z figure d.14 pbn/am symbol in figure d. 14 available products sh7144 sh7145 pins pbn am f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb0/a16 pb0 a16 (bsc) pb1/a17 pb1 a17 (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 827 of 882 rej09b0108-0400 pbn/irqm/pqem/function 1 q pbnmd0 q pbnmd1 q pbnmd2 q pbnior qd r pbndr res pbdr.wr pbdr.rd irqm (intc) poem (poe) function 1 function 1 pfc sbycr peripheral data bus c q irqel res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal q hi-z software standby figure d.15 pbn/ irqm / poem /function 1 symbol in figure d. 15 available products sh7144 sh7145 pins pbn irqm poem function 1 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb2/ irq0 / poe0 /scl0 pb2 irq0 (intc) poe0 (poe) scl0 (iic) pb3/ irq1 / poe1 /sda0 pb3 irq1 (intc) poe1 (poe) sda0 (iic) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 828 of 882 rej09b0108-0400 pbn/ irqm / poem q pbnmd0 q pbnmd1 q pbnior qd r pbndr res pbdr.wr pbdr.rd irqm (intc) pfc sbycr software standby peripheral data bus c res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal poem (poe) q hi-z q irqel figure d.16 pbn/ irqm / poem symbol in figure d. 16 available products sh7144 sh7145 pins pbn irqm poem f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb4/irq2/ poe2 pb4 irq2 (intc) poe2 (poe) ? ? pb5/irq3/ poe3 pb5 irq3 (intc) poe3 (poe) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 829 of 882 rej09b0108-0400 pbn/ irqm / poem / csx q pbnmd0 q pbnmd1 q pbnior qd r pbndr res pbdr.wr pbdr.rd pfc sbycr software standby bus release peripheral data bus c res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal q hi-z q irqel irqm (intc) poem (poe) csx (bsc) figure d.17 pbn/ irqm / poem / csx symbol in figure d. 17 available products sh7144 sh7145 pins pbn irqm poem csx f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb4/irq2/ poe2/cs6 pb4 irq2 (intc) poe2 (poe) cs6 (bsc) ? ? pb5/irq3/ poe3/cs7 pb5 irq3 (intc) poe3 (poe) cs7 (bsc) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 830 of 882 rej09b0108-0400 pb6/ irq4 /a18/ back q pb6md0 q pb6md1 q pb6ior qd r pb6dr res pbdr.wr pbdr.rd pfc sbycr software standby bus release peripheral data bus c res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal q hi-z q irqeh back (bsc) irq4 (intc) a18 (bsc) figure d.18 pb6/ irq4 /a18/ back symbol in figure d. 18 available products sh7144 sh7145 pins pb6 irq4 a18 back f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb6/ irq4 / a18/ back pb6 irq4 (intc) a18 (bsc) back (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 831 of 882 rej09b0108-0400 pb7/ irq5 /a19/ breq q pb7md0 q pb7md1 q pb7ior qd r pb7dr res pbdr.wr pbdr.rd a19 (bsc) irq5 (intc) breq (bsc) pfc sbycr software standby bus release peripheral data bus c q irqeh res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal q hi-z figure d.19 pb7/ irq5 /a19/ breq symbol in figure d. 19 available products sh7144 sh7145 pins pb7 irq5 a19 breq f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb7/ irq5 / a19/ breq pb7 irq5 (intc) a19 (bsc) breq (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 832 of 882 rej09b0108-0400 pb8/ irq6 /a20/ wait q pb8md0 q pb8md1 q pb8ior qd r pb8dr res pbdr.wr pbdr.rd a20 (bsc) irq6 (intc) wait (bsc) pfc sbycr software standby bus release peripheral data bus c q irqeh res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal q hi-z figure d.20 pb8/ irq6 /a20/ wait symbol in figure d. 20 available products sh7144 sh7145 pins pb8 irq6 a20 wait f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb8/ irq6 / a20/ wait pb8 irq6 (intc) a20 (bsc) wait (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 833 of 882 rej09b0108-0400 pb9/ irq7 /a21/ adtrg q pb9md0 q pb9md1 q pb9ior qd r pb9dr res pbdr.wr pbdr.rd a21 (bsc) irq7 (intc) adtrg (a/d) pfc sbycr software standby bus release peripheral data bus c q irqeh res: reset si g nal pbdr.rd: port b data re g ister read si g nal pbdr.wr: port b data re g ister write si g nal q hi-z figure d.21 pb9/ irq7 /a21/ adtrg symbol in figure d. 21 available products sh7144 sh7145 pins pb9 irq7 a21 adtrg f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pb9/ irq7 / a21/ adtrg pb9 irq7 (intc) a21 (bsc) adtrg (a/d) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 834 of 882 rej09b0108-0400 pcn/an q pcnmd q pcnior qd r pcndr res pcdr.wr pcdr.rd an (bsc) pfc sbycr software standby bus release peripheral data bus c res: reset si g nal pcdr.rd: port c data re g ister read si g nal pcdr.wr: port c data re g ister write si g nal q hi-z figure d.22 pcn/an symbol in figure d. 22 available products sh7144 sh7145 pins pcn an f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pc0/a0 pc0 a0 (bsc) pc1/a1 pc1 a1 (bsc) pc2/a2 pc2 a2 (bsc) pc3/a3 pc3 a3 (bsc) pc4/a4 pc4 a4 (bsc) pc5/a5 pc5 a5 (bsc) pc6/a6 pc6 a6 (bsc) pc7/a7 pc7 a7 (bsc) pc8/a8 pc8 a8 (bsc) pc9/a9 pc9 a9 (bsc) pc10/a10 pc10 a10 (bsc) pc11/a11 pc11 a11 (bsc) pc12/a12 pc12 a12 (bsc) pc13/a13 pc13 a13 (bsc) pc14/a14 pc14 a14 (bsc) pc15/a15 pc15 a15 (bsc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 835 of 882 rej09b0108-0400 pdn/dn q pdnmd q pdnior qd r pdndr res pddrl.wr pddrl.rd din dout dn (bsc) pfc sbycr software standby bus release peripheral data bus c internal data bus res: reset si g nal pddrl.rd: port d data re g ister l read si g nal pddrl.wr: port d data re g ister l write si g nal din: data input timin g si g nal dout: data output timin g si g nal q hi-z figure d.23 pdn/dn symbol in figure d.23 available products sh7144 sh7145 pins pdn dn pdnmd f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd0/d0 pd0 d0 (bsc) pd0md pd1/d1 pd1 d1 (bsc) pd1md pd2/d2 pd2 d2 (bsc) pd2md pd3/d3 pd3 d3 (bsc) pd3md pd4/d4 pd4 d4 (bsc) pd4md pd5/d5 pd5 d5 (bsc) pd5md pd6/d6 pd6 d6 (bsc) pd6md pd7/d7 pd7 d7 (bsc) pd7md pd8/d8 pd8 d8 (bsc) pd8md0 ? pd9/d9 pd9 d9 (bsc) pd9md0 ? pd10/d10 pd10 d10 (bsc) pd10md0 ? pd11/d11 pd11 d11 (bsc) pd11md0 ? pd12/d12 pd12 d12 (bsc) pd12md0 ? pd13/d13 pd13 d13 (bsc) pd13md0 ? pd14/d14 pd14 d14 (bsc) pd14md0 ? pd15/d15 pd15 d15 (bsc) pd15md0 ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 836 of 882 rej09b0108-0400 pdn/dn/audatam q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrl.wr pddrl.rd pfc dout din sbycr aud module standby bus release peripheral data bus c res: reset si g nal pddrl.rd: port d data re g ister l read si g nal pddrl.wr: port d data re g ister l write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z audatam (aud) audatam (aud) audsync aud reset audmd dn (bsc) internal data bus figure d.24 pdn/dn/audatam symbol in figure d. 24 available products sh7144 sh7145 pins pdn dn audatam f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd8/d8/ audata0 pd8 d8 (bsc) audata0 (aud) ? ? ? pd9/d9/ audata1 pd9 d9 (bsc) audata1 (aud) ? ? ? pd10/d10/ audata2 pd10 d10 (bsc) audata2 (aud) ? ? ? pd11/d11/ audata3 pd11 d11 (bsc) audata3 (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 837 of 882 rej09b0108-0400 pdn/dn/function 1 q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrl.wr pddrl.rd pfc dout din sbycr bus release peripheral data bus c res: reset si g nal pddrl.rd: port d data re g ister l read si g nal pddrl.wr: port d data re g ister l write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z aud module standby function 1 dn (bsc) internal data bus figure d.25 pdn/dn/function 1 symbol in figure d. 25 available products sh7144 sh7145 pins pdn dn function 1 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd12/d12/ audrst pd12 d12 (bsc) audrst (aud) ? ? ? pd13/d13 /audmd pd13 d13 (bsc) audmd (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 838 of 882 rej09b0108-0400 pdn/dn/function 2 q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrl.wr pddrl.rd pfc dout audmd din sbycr aud module standby bus release peripheral data bus c res: reset si g nal pddrl.rd: port d data re g ister l read si g nal pddrl.wr: port d data re g ister l write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z function 2 function 2 dn (bsc) internal data bus figure d.26 pdn/dn/function 2 symbol in figure d. 26 available products sh7144 sh7145 pins pdn dn function 2 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd14/d14/ audck pd14 d14 (bsc) audck (aud) ? ? ? pd15/d15/ audsync pd15 d15 (bsc) audsyn c (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 839 of 882 rej09b0108-0400 pdn/dn/ irqm q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrh.wr pddrh.rd pfc dout din sbycr bus release peripheral data bus c res: reset si g nal pddrh.rd: port d data re g ister h read si g nal pddrh.wr: port d data re g ister h write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z q irqel(h) irqm (intc) dn (bsc) internal data bus figure d.27 pdn/dn/ irqm symbol in figure d.27 available products sh7144 sh7145 pins pdn dn irqm f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd16/d16/ irq0 pd16 d16 (bsc) irq0 (intc) ? ? ? pd17/d17/ irq1 pd17 d17 (bsc) irq1 (intc) ? ? ? pd18/d18/ irq2 pd18 d18 (bsc) irq2 (intc) ? ? ? pd19/d19/ irq3 pd19 d19 (bsc) irq3 (intc) ? ? ? pd20/d20/ irq4 pd20 d20 (bsc) irq4 (intc) ? ? ? pd21/d21/ irq5 pd21 d21 (bsc) irq5 (intc) ? ? ? pd22/d22/ irq6 pd22 d22 (bsc) irq6 (intc) ? ? ? pd23/d23/ irq7 pd23 d23 (bsc) irq7 (intc) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 840 of 882 rej09b0108-0400 pdn/dn/ irqm /audatam q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrh.wr pddrh.rd pfc dout din sbycr aud module standby bus release peripheral data bus c res: reset si g nal pddrh.rd: port d data re g ister h read si g nal pddrh.wr: port d data re g ister h write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z q irqel audatam (aud) audatam (aud) irqm (intc) audsync aud reset audmd dn (bsc) internal data bus figure d.28 pdn/dn/ irqm /audatam symbol in figure d.28 available products sh7144 sh7145 pins pdn dn irqm audatam f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd16/d16/ irq0 / audata0 pd16 d16 (bsc) irq0 (intc) audata0 (aud) ? ? ? pd17/d17/ irq1 / audata1 pd17 d17 (bsc) irq1 (intc) audata1 (aud) ? ? ? pd18/d18/ irq2 / audata2 pd18 d18 (bsc) irq2 (intc) audata2 (aud) ? ? ? pd19/d19/ irq3 / audata3 pd19 d19 (bsc) irq3 (intc) audata3 (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 841 of 882 rej09b0108-0400 pdn/dn/irqm/function 1 q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrh.wr pddrh.rd pfc dout din sbycr bus release peripheral data bus c res: reset si g nal pddrh.rd: port d data re g ister h read si g nal pddrh.wr: port d data re g ister h write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z q irqeh aud module standby irqm (intc) function 1 dn (bsc) internal data bus figure d.29 pdn/dn/ irqm /function 1 symbol in figure d. 29 available products sh7144 sh7145 pins pdn dn irqm function 1 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd20/d20/ irq4 / audrst pd20 d20 (bsc) irq4 (intc) audrst (aud) ? ? ? pd21/d21/ irq5 / audmd pd21 d21 (bsc) irq5 (intc) audmd (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 842 of 882 rej09b0108-0400 pdn/dn/irqm/function 2 q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrh.wr pddrh.rd pfc dout audmd din sbycr aud module standby bus release peripheral data bus c res: reset si g nal pddrh.rd: port d data re g ister h read si g nal pddrh.wr: port d data re g ister h write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z q irqeh function 2 function 2 irqm (intc) dn (bsc) internal data bus figure d.30 pdn/dn/ irqm /function 2 symbol in figure d. 30 available products sh7144 sh7145 pins pdn dn irqm function 2 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd22/d22/ irq6 / audck pd22 d22 (bsc) irq6 (intc) audck (aud) ? ? ? pd23/d23/ irq7 / audsync pd23 d23 (bsc) irq7 (intc) audsyn c (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 843 of 882 rej09b0108-0400 pdn/dn/function 3 q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrh.wr pddrh.rd pfc dout din sbycr bus release peripheral data bus c res: reset si g nal pddrh.rd: port d data re g ister h read si g nal pddrh.wr: port d data re g ister h write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z function 3 dn (bsc) internal data bus figure d.31 pdn/dn/function 3 symbol in figure d. 31 available products sh7144 sh7145 pins pdn dn function 3 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd24/d24/ dreq0 pd24 d24 (bsc) dreq0 (dmac) ? ? pd25/d25/ dreq1 pd25 d25 (bsc) dreq1 (dmac) ? ? pd31/d31/ adtrg pd31 d31 (bsc) adtrg (a/d) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 844 of 882 rej09b0108-0400 pdn/dn/function 4 q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrh.wr pddrh.rd pfc dout din sbycr bus release peripheral data bus c res: reset si g nal pddrh.rd: port d data re g ister h read si g nal pddrh.wr: port d data re g ister h write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z function 4 dn (bsc) internal data bus figure d.32 pdn/dn/function 4 symbol in figure d. 32 available products sh7144 sh7145 pins pdn dn function 4 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd26/d26/ dack0 pd26 d26 (bsc) dack0 (dmac) ? ? pd27/d27/ dack1 pd27 d27 (bsc) dack1 (dmac) ? ? pd30/d30/ irqout pd30 d30 (bsc) irqout (intc) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 845 of 882 rej09b0108-0400 pdn/dn/ csm q pdnmd0 q pdnmd1 q pdnior qd r pdndr res pddrh.wr pddrh.rd pfc dout din sbycr bus release peripheral data bus c res: reset si g nal pddrh.rd: port d data re g ister h read si g nal pddrh.wr: port d data re g ister h write si g nal din: data input timin g si g nal dout: data output timin g si g nal software standby q hi-z csm (bsc) dn (bsc) internal data bus figure d.33 pdn/dn/ csm symbol in figure d. 33 available products sh7144 sh7145 pins pdn dn csm f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pd28/d28/ cs2 pd28 d28 (bsc) cs2 (bsc) ? ? pd29/d29/ cs3 pd29 d29 (bsc) cs3 (bsc) ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 846 of 882 rej09b0108-0400 pen/tiocxx/function 1 q penmd0 q penmd1 q penior qd r pendr res pedrl.wr pedrl.rd tiocxx (mtu) tiocxx (mtu) function 1 pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z figure d.34 pen/tiocxx/function 1 symbol in figure d. 34 available products sh7144 sh7145 pins pen tiocxx function 1 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe0/tioc0a/ dreq0 pe0 tioc0a (mtu) dreq0 (dmac) ? ? pe2/tioc0c/ dreq1 pe2 tioc0c (mtu) dreq1 (dmac) ? ? pe4/tioc1a/ rxd3 pe4 tioc1a (mtu) rxd3 (sci) ? ? pe7/tioc2b/ rxd2 pe7 tioc2b (mtu) rxd2 (sci) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 847 of 882 rej09b0108-0400 pen/tiocxx/function 2 q penmd0 q penmd1 q penior qd r pendr res pedrl.wr pedrl.rd pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z function 2 tiocxx (mtu) tiocxx (mtu) figure d.35 pen/tiocxx/function 2 symbol in figure d. 35 available products sh7144 sh7145 pins pen tiocxx function 2 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe1/tioc0b/ drak0 pe1 tioc0b (mtu) drak0 (dmac) ? ? pe3/tioc0d/ drak1 pe3 tioc0d (mtu) drak1 (dmac) ? ? pe5/tioc1b/ txd3 pe5 tioc1b (mtu) txd3 (sci) ? pe10/tioc3c/ txd2 pe10 tioc3c (mtu) txd2 (sci) ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 848 of 882 rej09b0108-0400 pen/tiocxx/sckm q penmd0 q penmd1 q penior qd r pendr res pedrl.wr pedrl.rd pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z sckm (sci) tiocxx (mtu) tiocxx (mtu) sckm (sci) figure d.36 pen/tiocxx/sckm symbol in figure d. 36 available products sh7144 sh7145 pins pen tiocxx sckm f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe9/tioc3b/ sck3 pe9 tioc3b (mtu) sck3 (sci) ? pe8/tioc3a/ sck2 pe8 tioc3a (mtu) sck2 (sci) ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 849 of 882 rej09b0108-0400 pe9/tioc3b/sck3 q pe9md0 q pe9md1 q pe9ior qd r pe9dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize sck3 (sci) tioc3b (mtu) tioc3b (mtu) sck3 (sci) figure d.37 pe9/tioc3b/sck3 symbol in figure d. 37 available products sh7144 sh7145 pins pe9 tioc3b sck3 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe9/tioc3b/ sck3 pe9 tioc3b (mtu) sck3 (sci) ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 850 of 882 rej09b0108-0400 pe11/tioc3d/rxd3 q pe11md0 q pe11md1 q pe11ior qd r pe11dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize tioc3d (mtu) tioc3d (mtu) rxd3 (sci) figure d.38 pe11/tioc3d/rxd3 symbol in figure d. 38 available products sh7144 sh7145 pins pe11 tioc3d rxd3 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe11/tioc3d/ rxd3 pe11 tioc3d (mtu) rxd3 (sci) ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 851 of 882 rej09b0108-0400 pe12/tioc4a/txd3 q pe12md0 q pe12md1 q pe12ior qd r pe12dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize txd3 (sci) tioc4a (mtu) tioc4a (mtu) figure d.39 pe12/tioc4a/txd3 symbol in figure d. 39 available products sh7144 sh7145 pins pe12 tioc4a txd3 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe12/tioc4a/ txd3 pe12 tioc4a (mtu) txd3 (sci) ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 852 of 882 rej09b0108-0400 pe13/tioc4b/ mres q pe13md0 q pe13md1 q pe13ior qd r pe13dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize tioc4b (mtu) tioc4b (mtu) mres (intc) figure d.40 pe13/tioc4b/ mres symbol in figure d. 40 available products sh7144 sh7145 pins pe13 tioc4b mres f-ztat version masked rom version rom less version f-ztat version masked rom version/ rom less version pe13/tioc4b/ mres pe13 tioc4b (mtu) mres (intc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 853 of 882 rej09b0108-0400 pe14/tioc4c/dack0 q pe14md0 q pe14md1 q pe14ior qd r pe14dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize dack0 (dmac) tioc4c (mtu) tioc4c (mtu) figure d.41 pe14/tioc4c/dack0 symbol in figure d. 41 available products sh7144 sh7145 pins pe14 tioc4c dack0 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe14/tioc4c/ dack0 pe14 tioc4c (mtu) dack0 (dmac) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 854 of 882 rej09b0108-0400 pe15/tioc4d/dack1/ irqout q pe15md0 q pe15md1 q pe15ior qd r pe15dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize dack1 (dmac) irqout (intc) tioc4d (mtu) tioc4d (mtu) figure d.42 pe15/tioc4d/dack1/ irqout symbol in figure d. 42 available products sh7144 sh7145 pins pe15 tioc4d dack1 irqout f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe15/tioc4d/ dack1/ irqout pe15 tioc4d (mtu) dack1 (dmac) irqout (intc) d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 855 of 882 rej09b0108-0400 pen/tiocxx/function 1/ function 2 q penmd0 q penmd1 q penior dbgmd qd r pendr res pedrl.wr pedrl.rd pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z tiocxx (mtu) tiocxx (mtu) function 1 function 2 figure d.43 pen/tiocxx/function 1/function 2 symbol in figure d.43 available products sh7144 sh7145 pins pen tiocxx function 1 function 2 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe0/tioc0a/ dreq0 /tms pe0 tioc0a (mtu) dreq0 (dmac) tms (h-udi) ? ? ? pe2/tioc0c/ dreq1 /tdi pe2 tioc0c (mtu) dreq1 (dmac) tdi (h-udi) ? ? ? pe4/tioc1a/ rxd3/tck pe4 tioc1a (mtu) rxd3 (sci) tck (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 856 of 882 rej09b0108-0400 pe1/tioc0b/drak0/ trst q pe1md0 q pe1md1 q pe1ior dbgmd qd r pe1dr res pedrl.wr pedrl.rd pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z drak0 (dmac) tioc0b (mtu) tioc0b (mtu) trst (h-udi) figure d.44 pe1/tioc0b/drak0/ trst symbol in figure d.44 available products sh7144 sh7145 pins pe1 tioc0b drak0 trst f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe1/tioc0b/ drak0/ trst pe1 tioc0b (mtu) drak0 (dmac) trst (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 857 of 882 rej09b0108-0400 pe3/tioc0d/drak1/tdo q pe3md0 q pe3md1 q pe3ior dbgmd qd r pe3dr res pedrl.wr pedrl.rd pfc sbycr software standby test reset peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z drak1 (dmac) tdo (h-udi) tioc0d (mtu) tioc0d (mtu) figure d.45 pe3/tioc0d/drak1/tdo symbol in figure d.45 available products sh7144 sh7145 pins pe3 tioc0d drak1 tdo f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe3/tioc0d/ drak1/tdo pe3 tioc0d (mtu) drak1 (dmac) tdo (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 858 of 882 rej09b0108-0400 pe0/tioc0a/ dreq0 /audck q pe0md0 q pe0md1 q pe0ior qd r pe0dr res pedrl.wr pedrl.rd pfc sbycr audmd software standby aud module standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z audck (aud) tioc0a (mtu) tioc0a (mtu) dreq0 (dmac) audck (aud) figure d.46 pe0/tioc0a/ dreq0 /audck symbol in figure d.46 available products sh7144 sh7145 pins pe0 tioc0a dreq0 audck f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe0/tioc0a/ dreq0 / audck pe0 tioc0a (mtu) dreq0 (dmac) audck (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 859 of 882 rej09b0108-0400 pe1/tioc0b/drak0/audmd q pe1md0 q pe1md1 q pe1ior qd r pe1dr res pedrl.wr pedrl.rd pfc sbycr software standby aud module standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z drak0 (dmac) tioc0b (mtu) tioc0b (mtu) audmd (aud) figure d.47 pe1/tioc0b/drak0/audmd symbol in figure d.47 available products sh7144 sh7145 pins pe1 tioc0b drak0 audmd f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe1/tioc0b/ drak0/ audmd pe1 tioc0b (mtu) drak0 (dmac) audmd (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 860 of 882 rej09b0108-0400 pe2/tioc0c/ dreq1 / audrst q pe2md0 q pe2md1 q pe2ior qd r pe2dr res pedrl.wr pedrl.rd pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z aud module standby tioc0c (mtu) tioc0c (mtu) dreq1 (dmac) audrst (aud) figure d.48 pe2/tioc0c/ dreq1 / audrst symbol in figure d.48 available products sh7144 sh7145 pins pe2 tioc0c dreq1 audrst f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe2/tioc0c/ dreq1 / audrst pe2 tioc0c (mtu) dreq1 (dmac) audrst (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 861 of 882 rej09b0108-0400 pen/tiocxx/function 1/audatam q penmd0 q penmd1 q penior qd r pendr res pedrl.wr pedrl.rd pfc audsync aud reset audmd sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z aud module standby function 1 audatam (aud) tiocxx (mtu) tiocxx (mtu) audatam (aud) figure d.49 pen/tiocxx/function 1/audatam symbol in figure d.49 available products sh7144 sh7145 pins pen tiocxx function 1 audatam f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe3/tioc0d/ drak1/ audata3 pe3 tioc0d (mtu) drak1 (dmac) audata3 (aud) ? ? ? pe5/tioc1b/ txd3/ audata1 pe5 tioc1b (mtu) txd3 (sci) audata1 (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 862 of 882 rej09b0108-0400 pe4/tioc1a/rxd3/audata2 q pe4md0 q pe4md1 q pe4ior qd r pe4dr res pedrl.wr pedrl.rd pfc sbycr audmd audsync aud reset software standby aud module standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z audata2 (aud) tioc1a (mtu) tioc1a (mtu) rxd3 (sci) audata2 (aud) figure d.50 pe4/tioc1a/rxd3/audata2 symbol in figure d.50 available products sh7144 sh7145 pins pe4 tioc1a rxd3 audata2 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe4/tioc1a/ rxd3/ audata2 pe4 tioc1a (mtu) rxd3 (sci) audata2 (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 863 of 882 rej09b0108-0400 pe6/tioc2a/sck3/audata0 q pe6md0 q pe6md1 q pe6ior qd r pe6dr res pedrl.wr pedrl.rd pfc audsync aud reset audmd sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z aud module standby sck3 (sci) audata0 (aud) tioc2a (mtu) tioc2a (mtu) sck3 (sci) audata0 (aud) figure d.51 pe6/tioc2a/sck3/audata0 symbol in figure d.51 available products sh7144 sh7145 pins pe6 tioc2a sck3 audata0 f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe6/tioc2a/ sck3/ audata0 pe6 tioc2a (mtu) sck3 (sci) audata0 (aud) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 864 of 882 rej09b0108-0400 pe8/tioc3a/sck2/tms q pe8md0 q pe8md1 q pe8ior dbgmd qd r pe8dr res pedrl.wr pedrl.rd pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z sck2 (sci) tioc3a (mtu) tioc3a (mtu) sck2 (sci) tms (h-udi) figure d.52 pe8/tioc3a/sck2/tms symbol in figure d.52 available products sh7144 sh7145 pins pe8 tioc3a sck2 tms f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe8/tioc3a/ sck2/tms pe8 tioc3a (mtu) sck2 (sci) tms (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 865 of 882 rej09b0108-0400 pe9/tioc3b/sck3/ trst q pe9md0 q pe9md1 q pe9ior dbgmd qd r pe9dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize sck3 (sci) tioc3b (mtu) tioc3b (mtu) sck3 (sci) trst (h-udi) figure d.53 pe9/tioc3b/sck3/ trst symbol in figure d.53 available products sh7144 sh7145 pins pe9 tioc3b sck3 trst f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe9/tioc3b/ sck3/ trst pe9 tioc3b (mtu) sck3 (sci) trst (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 866 of 882 rej09b0108-0400 pe10/tioc3c/txd2/tdi q pe10md0 q pe10md1 q pe10ior dbgmd qd r pe10dr res pedrl.wr pedrl.rd pfc sbycr software standby peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z txd2 (sci) tioc3c (mtu) tioc3c (mtu) tdi (h-udi) figure d.54 pe10/tioc3c/txd2/tdi symbol in figure d.54 available products sh7144 sh7145 pins pe10 tioc3c txd2 tdi f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe10/tioc3c/ txd2/tdi pe10 tioc3c (mtu) txd2 (sci) tdi (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 867 of 882 rej09b0108-0400 pe11/tioc3d/rxd3/tdo q pe11md0 q pe11md1 q pe11ior dbgmd qd r pe11dr res pedrl.wr pedrl.rd pfc sbycr test reset software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize tdo (h-udi) tioc3d (mtu) tioc3d (mtu) rxd3 (sci) figure d.55 pe11/tioc3d/rxd3/tdo symbol in figure d.55 available products sh7144 sh7145 pins pe11 tioc3d rxd3 tdo f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe11/tioc3d/ rxd3/tdo pe11 tioc3d (mtu) rxd3 (sci) tdo (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 868 of 882 rej09b0108-0400 pe12/tioc4a/txd3/tck q pe12md0 q pe12md1 q pe12ior dbgmd qd r pe12dr res pedrl.wr pedrl.rd pfc sbycr software standby poe oscillation halt peripheral data bus c res: reset si g nal pedrl.rd: port e data re g ister l read si g nal pedrl.wr: port e data re g ister l write si g nal q hi-z ppcr q mzize txd3 (sci) tioc4a (mtu) tioc4a (mtu) tck (h-udi) figure d.56 pe12/tioc4a/txd3/tck symbol in figure d.56 available products sh7144 sh7145 pins pe12 tioc4a txd3 tck f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pe12/tioc4a/ txd3/tck pe12 tioc4a (mtu) txd3 (sci) tck (h-udi) ? ? ? d. i/o port block diagrams rev.4.00 mar. 27, 2008 page 869 of 882 rej09b0108-0400 pfn/ann peripheral data bus pfdr.rd: port f data re g ister read si g nal ann (a/d) pfdr.rd software standby figure d.57 pfn/ann symbol in figure d. 57 available products sh7144 sh7145 pins pfn ann f-ztat version masked rom version/ rom less version f-ztat version masked rom version/ rom less version pf0/an0 pf0 an0 (a/d) pf1/an1 pf1 an1 (a/d) pf2/an2 pf2 an2 (a/d) pf3/an3 pf3 an3 (a/d) pf4/an4 pf4 an4 (a/d) pf5/an5 pf5 an5 (a/d) pf6/an6 pf6 an6 (a/d) pf7/an7 pf7 an7 (a/d) e. package dimensions rev.4.00 mar. 27, 2008 page 870 of 882 rej09b0108-0400 appendix e package dimensions the package dimensions that are shown in the renesas semiconductor package data book have priority. note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. * 1 * 2 * 3 p e d e d xm y f 112 128 29 85 84 57 56 d h e h b z z 2 1 1 detail f c a a l a l terminal cross section 1 1 p c b c b h e l e c 1 a 1 d e a 2 h d a b p b 1 c x y z d z e l 1 max nom min dimension in millimeters symbol reference 1.6 0.10 0 ? 8 ? 0.65 0.12 0.17 0.22 0.24 0.32 0.40 0.00 0.10 0.25 3.05 23.0 23.2 23.4 2.70 20 0.30 0.15 0.6 0.8 1.0 0.13 23.4 23.2 23.0 1.23 20 1.23 e p-qfp112-20x20-0.65 2.4g mass[typ.] fp-112b/fp-112bv prqp0112jb-a renesas code jeita package code previous code figure e.1 fp-112b e. package dimensions rev.4.00 mar. 27, 2008 page 871 of 882 rej09b0108-0400 note) 1. dimensions" * 1"and" * 2" do not include mold flash 2. dimension" * 3"does not include trim offset. 1.25 1.25 0.08 0.10 0.5 0.15 8 ? 0 ? 0.20 0.10 0.20 0.00 0.27 0.22 0.17 0.22 0.17 0.12 1.70 22.2 21.8 22.0 h e l 1 z e z d y x c b 1 b p a h d a 2 e d a 1 c 1 e e l 20 0.6 0.5 0.4 max nom min dimension in millimeters symbol reference 20 1.40 22.2 22.0 21.8 1.0 index mark * 1 * 2 * 3 p e d e d xm y f 144 1 37 36 109 108 72 73 z z h e h d b 2 1 1 detail f c a a l a l terminal cross section p 1 1 c b c b p-lqfp144-20x20-0.50 1.4g mass[typ.] fp-144f/fp-144fv plqp0144kb-a renesas code jeita package code previous code figure e.2 fp-144f e. package dimensions rev.4.00 mar. 27, 2008 page 872 of 882 rej09b0108-0400 main revisions for this edition rev.4.00 mar. 27, 2008 page 873 of 882 rej09b0108-0400 main revisions for this edition item page revision (see manual for details) 5.1.3 exception processing vector table table 5.3 exception processing vector table 64 table and note amended exception sources vector numbers vector table address offset on-chip peripheral module * 2 72 : 255 h'00000120 to h'00000123 : h'000003fc to h'000003ff notes: 1. only in the f-ztat version. 2. the vector numbers and vector table address offsets for each on-chip peripheral module interrupt are g iven in table 6.2. 11.4.5 pwm modes figure 11.23 example of pwm mode operation (3) 275 figure amended tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not chan g e when cycle re g ister and duty re g ister compare matches occur simultaneously 11.4.8 complementary pwm mode figure 11.34 complementary pwm mode counter operation 290 figure amended counter value tgra_3 tcdr tddr h'0000 tcnt_4 tcnts tcnt_3 tcnt_3 tcnt_4 tcnts time main revisions for this edition rev.4.00 mar. 27, 2008 page 874 of 882 rej09b0108-0400 item page revision (s ee manual for details) 11.7.16 contention between overflow/underflow and counter clearing figure 11.83 contention between overflow and counter clearing 333 figure amended counter clear si g nal tcnt tcnt input clock p h'ffff h'0000 tgf tcfv disabled 11.7.17 contention between tcnt write and overflow/underflow figure 11.84 contention between tcnt write and overflow 334 figure amended write si g nal address p tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv fla g 11.7.22 note on buffer operation setting 335 newly added 12.1 features 379 description replaced 13.4.4 sci initialization (asynchronous mode) figure 13.5 sample sci initialization flowchart 430 figure replaced main revisions for this edition rev.4.00 mar. 27, 2008 page 875 of 882 rej09b0108-0400 item page revision (see manual for details) 13.6.1 clock 443 description added eight serial clock pulses are output in the transfer of one character, and when no transfer is performed, the clock is fixed high. however, during receive-only operation the synchronization clock is output until an overrun error occurs or the re bit is cleared to 0. when receive operation in single- character units is desired, select an external clock as the clock source. 13.6.2 sci initialization (clocked synchronous mode) figure 13.15 sample sci initialization flowchart 444 figure replaced 14.3.4 i2c bus mode register (icmr) table 14.3 setting of the transfer rate 476 table and note amended transfer rate p = 10mhz p 357khz 571khz * 714khz * 893khz * 1.18mhz * 1.43mhz * 250khz 400khz 500khz * 625khz * 825khz * 1.00mhz * 208khz 333khz 417khz * 521khz * 688khz * 833khz * 156khz 250khz 313khz 391khz 516khz * 625khz * 125khz 200khz 250khz 313khz 413khz * 500khz * 100khz 160khz 200khz 250khz 330khz 400khz 89.3khz 143khz 179khz 223khz 295khz 357khz 78.1khz 125khz 156khz 195khz 258khz 313khz note: * out of the i 2 c bus interface specification (normal mode: maximum100 khz, high speed mode: maximum 400 khz) due to factors such as load conditions, it may not be possible to obtain the designated transfer rate when the value of iicx is 0 and the peripheral clock frequency exceeds 16 mhz. set iicx to 1 when p is greater than 16 mhz. 14.5 usage notes 10. notes on wait function 535, 536 description added main revisions for this edition rev.4.00 mar. 27, 2008 page 876 of 882 rej09b0108-0400 item page revision (s ee manual for details) 15.3.2 a/d control/status register_0, 1 (adcsr_0, adcsr_1) 545 table amended bit bit name initial value r/w description 7 adf 0 r/(w) * a/d end fla g a status fla g that indicates the end of a/d conversion. [settin g conditions] ? when a/d conversion ends in sin g le mode ? when a/d conversion ends on all specified channels in scan mode [clearin g conditions] ? when 0 is written after readin g adf = 1 ? when the dmac or the dtc is activated by an adi interrupt and data is read from addr while the dtmr bit in the dtc is cleared to 0 16.2.2 compare match timer control/status register_0, 1 (cmcsr_0, cmcsr_1) 561 table amended bit bit name initial value r/w description 7 cmf 0 r/(w) * compare match fla g this fla g indicates whether or not the cmcnt and cmcor values have matched. 0: cmcnt and cmcor values have not matched 1: cmcnt and cmcor values have matched [clearin g condition] ? write 0 to cmf after readin g 1 from it ? when the dtc is activated by an cmi interrupt and data is transferred with the disel bit in dtmr of dtc = 0 19.1 features 657 description amended ? reprogramming capability see section 26.5, flash memory characteristics. 19.8.3 interrupt handling when programming/erasing flash memory figure 19.10 erase/erase-verify flowchart 679 figure amended * 1 * 3 erase start set ebr1 and ebr2 swe bit 1 n 1 wait (t sswe ) s 19.11.3 notes on flash memory programming and erasing 683 to 685 description replaced 23.5.7 settings of aud- related pins when using e10a 717 newly added main revisions for this edition rev.4.00 mar. 27, 2008 page 877 of 882 rej09b0108-0400 item page revision (see manual for details) 24.3.1 sleep mode transition to sleep mode 727 in sleep mode, data should not be accessed by the dmac, dtc, or aud. clearing sleep mode ? clearing by the interrupt (masked version and rom less version) ? clearing by the dmac/dtc address error (masked version and rom less version) ? description deleted 24.4.5 dmac, dtc, or aud operation in sleep mode 731 description amended in sleep mode, data should not be accessed by the dmac, dtc, or aud. 26.2 dc characteristics table 26.2 dc characteristics 768 table amended item symbol min. typ. max. unit measurement conditions v t+ (v ih ) v cc ? 0.5 ? ? v v t? (v il ) ? ? 0.5 v schmitt tri gg er input volta g e irq7 to irq0 , poe3 to poe0 , tclka to tclkd, tioc0a to tioc0d, tioc1a, tioc1b, tioc2a, tioc2b, tioc3a to tioc3d, tioc4a to tioc4d, sck3 to sck0, rxd3 to rxd0 v t+ ?v t? 0.2 ? ? v 26.4 a/d converter characteristics table 26.17 a/d converter characteristics 795 table amended item min. typ. max. unit non-linear error (reference value) ? ? 3.0 * 3 * 4 * 5 / 5.0 * 6 lsb offset error (reference value) ? ? 3.0 * 3 * 4 * 5 / 5.0 * 6 lsb full-scale error (reference value) ? ? 3.0 * 3 * 4 * 5 / 5.0 * 6 lsb 26.5 flash memory characteristics table 26.18 flash memory characteristics 796, 797 table replaced appendix e package dimensions figure e.1 fp-112b 870 figure replaced figure e.2 fp-144f 871 main revisions for this edition rev.4.00 mar. 27, 2008 page 878 of 882 rej09b0108-0400 index rev.4.00 mar. 27, 2008 page 879 of 882 rej09b0108-0400 index a/d conversion time............................... 550 a/d converter ......................................... 541 absolute maximum ratings ..................... 767 activation by interrupt............................ 134 activation by software............................ 134 address error exception processing .......... 68 address map ..................................... 51, 141 addressing modes..................................... 25 advanced user debugger (aud) ............ 705 asynchronous serial communication ...... 426 auto-request mode.................................. 182 block configuration ................................ 663 block transfer mode................................ 129 boot mode............................................... 671 branch trace mode .................................. 708 buffer operation...................................... 266 burst mode.............................................. 195 bus arbitration ........................................ 161 bus masters............................................. 161 bus release state........................................ 46 bus state controller (bsc) ...................... 137 byte data ................................................... 19 cascaded operation ................................. 269 chain transfer.......................................... 130 clock mode............................................... 48 clock pulse generator ............................... 53 clocked synchronous communication .... 443 compare match....................................... 261 compare match timer (cmt) ................. 559 complementary pwm mode .................. 285 continuous scan mode ............................ 549 control registers........................................ 17 cpu .......................................................... 15 crystal oscillator....................................... 55 cycle-steal mode .................................... 195 data format in registers............................. 19 data formats.............................................. 19 data formats in memory ........................... 19 data transfer controller (dtc)................113 delayed branch instructions......................21 direct memory access controller (dmac) ................................................................167 dtc vector addresses .............................124 dual address mode ..................................190 effective address .......................................25 electrical charact eristics..........................767 error protection.......................................681 exception processing ................................61 exception processing state ........................46 exception processing vector table.............63 external clock input ..................................56 external request mode.............................182 fixed mode..............................................184 flash memory..........................................657 flash memory emula tion in ram...........674 free-running counters .............................260 function for detecting the oscillator halt...57 functions of multiplexed pins.................569 general illegal in structions .......................72 general registers (rn) ...............................15 global base register (gbr).......................18 hardware protection................................680 i/o ports ..................................................633 i 2 c bus format .........................................493 i 2 c bus interface......................................467 illegal slot in structions ..............................72 immediate data format ..............................20 input capture function .............................263 internal clock ............................................53 interrupt controller (intc) .......................77 interrupt exception processing ..................70 interrupt response time..............................96 interval timer mode.................................386 irq interrupts .....................................84, 87 longword data ..........................................19 manual reset..............................................66 index rev.4.00 mar. 27, 2008 page 880 of 882 rej09b0108-0400 mask rom ............................................. 689 master device.......................................... 496 mcu operating modes.............................. 47 module sta ndby mode ............................. 730 multi-function timer pulse unit (mtu) .. 213 multiply-and-accumulate registers (mac) ...................................................... 18 multiprocessor communication function 437 nmi interrupts .......................................... 87 normal mode .......................................... 127 on-board progra mming modes............... 670 on-chip peripheral module interrupts....... 88 on-chip peripheral module request mode ....................................................... 183 permissible signal source impedance...... 558 phase counting mode .............................. 276 pin function contro ller (pfc) ................. 569 pin functions in eac h operating mode..... 569 port output enable (poe)........................ 368 power-down modes ................................ 719 power-down state...................................... 46 power-on reset .......................................... 65 procedure register (pr)............................. 18 processing states ....................................... 45 program counter (pc) ............................... 18 program execution state............................ 46 pwm mode............................................. 271 ram ....................................................... 691 ram emula tion ...................................... 674 ram monitor mode................................ 709 reading from tcnt, tcsr, and rstcsr ................................................................ 390 register adcr ......................... 547, 740, 753, 763 adcsr....................... 545, 740, 752, 762 addr......................... 544, 740, 752, 762 adtsr ....................... 548, 743, 756, 764 bcr1 .......................... 144, 742, 754, 763 bcr2 .......................... 147, 742, 754, 763 brr ............................ 416, 734, 745, 758 chcr.......................... 172, 742, 754, 763 cmcnt ...................... 562, 740, 752, 762 cmcor ...................... 562, 740, 752, 762 cmcsr....................... 561, 740, 752, 762 cmstr....................... 560, 740, 752, 762 dar ............................ 171, 742, 754, 763 dmaor...................... 178, 742, 754, 763 dmatcr ................... 171, 742, 754, 763 dtbr.......................... 121, 743, 756, 764 dtcra............................................... 118 dtcrb ............................................... 119 dtcsr........................ 120, 743, 756, 764 dtdar............................................... 118 dter .......................... 119, 743, 756, 764 dtiar ................................................ 118 dtmr................................................. 116 dtsar ............................................... 118 ebr1........................... 667, 741, 753, 763 ebr2........................... 668, 741, 753, 763 flmcr1..................... 665, 741, 753, 763 flmcr2..................... 666, 741, 753, 763 iccr ........................... 477, 744, 757, 764 icdr........................... 471, 744, 757, 764 icmr .......................... 474, 744, 757, 764 icr1.............................. 80, 738, 749, 761 icr2.............................. 82, 738, 749, 761 icsr.................................... 486, 744, 757 icsr1.................. 370, 377, 739, 751, 762 ipr ................................ 85, 738, 749, 761 isr ................................ 84, 738, 749, 761 mstcr....................... 725, 741, 753, 763 ocsr .......................... 374, 739, 751, 762 pacr .......................... 597, 738, 750, 761 padr.......................... 636, 738, 750, 761 paior ........................ 596, 738, 750, 761 pbcr .......................... 605, 738, 750, 761 pbdr .......................... 640, 738, 750, 761 pbior......................... 605, 738, 750, 761 pccr .......................... 609, 738, 750, 761 pcdr .......................... 643, 738, 750, 761 index rev.4.00 mar. 27, 2008 page 881 of 882 rej09b0108-0400 pcior ........................ 609, 738, 750, 761 pdcr.......................... 612, 739, 751, 762 pddr.......................... 647, 739, 751, 762 pdior ........................ 611, 739, 751, 762 pecr .......................... 622, 739, 751, 762 pedrl........................ 652, 739, 751, 762 peiorl ...................... 621, 739, 751, 762 pfdr .......................... 654, 739, 751, 762 ppcr .......................... 630, 743, 756, 764 ramer .............. 153, 668, 742, 754, 763 rdr ............................ 398, 734, 745, 758 rsr..................................................... 398 rstcsr ..................... 384, 741, 753, 763 sar (dmac)............. 170, 742, 754, 763 sar (iic).................... 472, 744, 757, 764 sarx.......................... 473, 744, 757, 764 sbycr ....................... 722, 741, 753, 763 scr............................. 402, 734, 745, 758 scrx.......................... 490, 743, 756, 764 sdbpr................................................ 699 sdcr.......................... 415, 734, 745, 758 sddr.......................... 699, 744, 757, 764 sdir ........................... 697, 744, 757, 764 sdsr .......................... 698, 744, 757, 764 smr............................ 399, 734, 745, 758 ssr ............................. 407, 734, 745, 758 syscr........................ 724, 741, 753, 763 tcbr.......................... 257, 736, 746, 759 tcdr.......................... 257, 735, 746, 759 tcnt (mtu) ............. 249, 735, 746, 760 tcnt (wdt) ............. 381, 741, 753, 763 tcnts........................ 257, 736, 746, 759 tcr ............................ 220, 735, 746, 759 tcsr .......................... 382, 741, 753, 763 tddr ......................... 257, 735, 746, 759 tdr ............................ 398, 734, 745, 758 tgcr.......................... 255, 735, 746, 759 tgr .................................... 735, 746, 759 tgra ................................................. 249 tgrb.................................................. 249 tgrc..................................................249 tgrd..................................................249 tier............................ 244, 735, 746, 759 tior ........................... 226, 735, 746, 759 tmdr ......................... 224, 735, 746, 759 tocr.......................... 253, 735, 746, 759 toer .......................... 252, 735, 746, 759 tsr (mtu)................. 246, 736, 747, 759 tsr (sci) ...........................................398 tstr........................... 250, 736, 747, 759 tsyr .......................... 250, 736, 747, 759 ubamr...................... 103, 741, 753, 763 ubar ......................... 103, 741, 753, 763 ubbr.......................... 104, 741, 753, 763 ubcr.......................... 105, 741, 753, 763 wcr1 ......................... 152, 742, 754, 763 wcr2 ......................... 153, 742, 754, 763 register address table..............................733 register b it list ........................................745 register states in each operating mode ...758 repeat mode............................................127 reset state .................................................46 reset-synchronized pwm mode.............282 risc-type .................................................21 round robin mode...................................184 serial communication interface (sci).....393 serial format............................................493 single address mode................................188 single mode ............................................549 single-cycle scan mode...........................550 slave device ............................................509 sleep mode..............................................727 smart card interface ................................451 software protection .................................681 software standby mode ...........................728 status register (sr) ...................................17 synchronous op eration............................264 system clock ( ) .......................................53 system registers ........................................18 trap instructions .......................................71 index rev.4.00 mar. 27, 2008 page 882 of 882 rej09b0108-0400 user break controller (ubc)................... 101 user break interrupt .................................. 88 user debugging interface (h-udi) ......... 693 user debugging interf ace (h-udi) interrupt .................................................................. 89 user program mode ................................ 673 vector base register (vbr)....................... 18 vector no. ................................................ 90 vectors table ............................................. 90 watchdog timer....................................... 379 watchdog timer mode............................. 385 word data.................................................. 19 writing to rs tcsr ................................ 389 writing to tcnt and tcsr................... 389 renesas 32-bit risc microcomputer hardware manual sh7144 group, sh7145 group publication date: 1st edition, january, 2002 rev.4.00, march 27, 2008 published by: sales strategic planning div. renesas technology corp. edited by: customer support department global strategic communication div. renesas solutions corp. ? 2008. renesas technology corp., all rights reserved. printed in japan. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7858/7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2377-3473 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 3518-3399 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, m alaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices colophon 6.2 sh7144 group, sh7145 group rej09b0108-0400 hardware manual 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan |
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